Application Note 073 Using the TNT4882 in an MC68340 System Andrew Thomson Faisal Habib Introduction This application note is written for GPIB instrument designers who use the Motorola MC68340 processor. It describes the hardware interface required to create a fully functional GPIB device using the National Instruments TNT4882 GPIB interface chip with the Motorola MC68340. In this document we show how to create an interface that will meet the following specifications: • Complete IEEE 488.
MC68340 TNT4882AQ 5 ADDR4-0 A6-2 16 DATA15-0 D15-0 R/W RDN DACKN1 DSN WRN DAKN DREQN1 DRQ IRQN3 INTR XTAL1 40 MHz CMOS OSCILLATOR RESETN CSN ABSUN RESETN CSN2 A0 BBUSN SIZ0 RDY1 DSACKN1 CPUACC PAGED Figure 1. MC68340 and TNT4882 Interface Hardware Diagram Synchronous Bus Operation TNT4882 Address Lines Address lines A6-A2 of MC68340 connect directly to the address lines of TNT4882. Although TNT4882 only requires 32 bytes of address space a total of 256 bytes are assigned.
TNT4882 ABUSN, BBUSN Signals The TNT4882 has the capability of using either of its data busses for 8-bit I/O accesses. Either Bus A (D15-8) or Bus B (D7-0) can be selected using the ABUSN and BBUSN signals. These two signals can be controlled by using SIZ0 and A0 signals of the processor. Whenever accesses are made to an odd byte address, the processor uses the lower byte of the data bus and whenever accesses are made to an even byte address, the processor uses the upper byte of the data bus.
TNT4882 RDN, WRN Signals During write accesses, the TNT4882 latches data on the rising edge of WRN. The TNT4882 drives its data buses when RDN is asserted during read accesses. The processor asserts DSN to indicate that an external device should place valid data on the bus during a read access, and that valid data is on the data bus during a write access. The R/W signal indicates the direction of data transfer on the bus.
CPU Cycle CLK S0 S1 S2 S3 DMA Cycle S4 S5 S0 S1 S2 S3 S4 S5 S0 ADDR ASN DSN R/W DATA DRQ (TNT) DACKN RDN Figure 5. DMA Write (TNT4882 to Memory) Timing Diagram Asynchronous Bus Operation Normally, the TNT4882 is used in one chip mode. See Chapter 2 in the TNT4882 Programmer Reference Manual. To maintain backwards compatibility, the TNT4882 can be used in two chip mode. In the two chip mode, the TNT4882 duplicates the Turbo488/NAT4882 chipset.
Interrupt Acknowledge Bus Operation The TNT4882 can interrupt the processor by asserting its interrupt signal. The MC68340 will acknowledge the interrupt if its priority is higher than the interrupt mask in the status register. For the above example, interrupt level three has been selected. Since the TNT4882 cannot supply a vector number, it requests an automatically generated vector (autovector).
MODE Pin The MODE pin determines whether the TNT4882 enters Turbo+7210 mode or Turbo+9914 mode after a hardware reset. For the above interface, MODE was left unconnected so that the TNT4882 enters the Turbo+7210 mode. See the MODE & SWAPN Pin Recommendations section of the TNT4882 Programmer Reference Manual. SWAPN Pin The TNT4882 samples the SWAPN pin during a hardware reset. If SWAPN is asserted during a hardware reset, the SWAP bit is set. For the above interface, SWAPN pin was left unconnected.
Software Consideration Once the hardware interface has been constructed, a few initialization routines need to be performed. Once these initialization sequences are complete, the CPU can be programmed to implement any GPIB device. System Configuration System configuration must be performed before the TNT4882 can be used. Configuration of the system requires you to initialize and configure the System Integration Module (SIM), the interrupt registers, and the DMA channel.
Interrupt Configuration Since the above setup requires an autovector, we need to program the autovector register so that the vector number is generated internally when an interrupt is acknowledged. In the above case, we are using interrupt level three, therefore $08 should be stored in the autovector register. The vector table should also be modified to point to the new interrupt handler. For interrupt level three, the vector is stored at location $06C.
Downloading Procedures A Widows terminal settings file is also included on the disk. Execute the following steps to download a program: 1. Start Windows. 2. Choose RUN from the FILE menu. 3. Type A:\MC68340.TRM to start the Windows Terminal program. 4. Type LO and press . 5. Choose Send Text File from the Transfers menu. 6. Select HARDWARE.ABS from A:\HARDWARE directory. 7. When download has completed, hit twice.
In the DMA I/O test routine, the channel is initialized by clearing the status register and loading the byte transfer value in the byte counter register. The channel is then started, and DMA takes place when the DREQN1 pin of MC68340 goes low. DMA read takes place first where values are written to the FIFOs. DMA write takes place later where values are read back from the FIFOs. MC340BUG Library A Library is also included with the software package.
puts() Purpose Output a line to the output port Parameters string to be written Return Type void Example puts("hello"); puts(str) where str = "how are you?"; PrintHex() Purpose Output a number in hexadecimal form Parameters unsigned short int (0 - 65535) Return Type void Example PrintHex(321); PrintHex(num) where num = 3245; RET340BUG() Purpose Restore control to 340Bug from the target program Parameters NONE Return Type void Example RET340BUG(); References 1.
Register.
#define #define #define #define #define #define B_S3 B_S4 B_S5 B_S6 B_PEND B_S8 (SPSR (SPSR (SPSR (SPSR (SPSR (SPSR & & & & & & 0x04) 0x08) 0x10) 0x20) 0x40) 0x80) #define SPMR *(unsigned char *) (BASE + 0x18) #define E_S1 0x01 #define E_S2 0x02 #define E_S3 0x04 #define E_S4 0x08 #define E_S5 0x10 #define E_S6 0x20 #define E_PEND 0x40 #define E_S8 0x80 #define INTR *(unsigned char *) (BASE + 0x1D) #define ADSR *(unsigned #define B_MJMN (ADSR #define B_TA (ADSR #define B_LA (ADSR #define B_TPAS (ADSR
#define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define ClrREN REQT REQF TCSE LTNnCont LUN RPPL SetIFC SetREN PageIn HLDI ClrDET ClrEND ClrDEC ClrERR ClrSRQI ClrLOKC ClrREMC ClrADSC ClrIFCI ClrATNI ClrSYNC SetSYNC 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x50 0x51 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F #define PPR 0x60 #define P(value) (PPR | value) #def
#define AUXRJ 0xF0 #define TM(value) (AUXRJ | value) #define #define #define #define CNT3 CNT2 CNT1 CNT0 *(unsigned *(unsigned *(unsigned *(unsigned #define ADR0 *(unsigned #define F_ADR0 (ADR0 #define B_DL0 (ADR0 #define B_DT0 (ADR0 char char char char *) *) *) *) (BASE (BASE (BASE (BASE + + + + 0x2D) 0x25) 0x58) 0x50) char *) (BASE + 0x30) & 0x1F) & 0x20) & 0x40) #define ADR *(unsigned char *) (BASE + 0x30) #define ADDR(val) (ADR | val) #define E_DL 0x20 #define E_DT 0x40 #define E_ARS 0x80 #def
#define t13 0xC0 #define T13(value) (t13 | value) #define HIER *(unsigned char *) (BASE + 0x4D) #define E_PMTwEOS 0x01 #define E_NTSETUP 0x10 #define E_DGB 0x40 #define E_DGA 0x80 #define MISC *(unsigned char *) (BASE + 0x55) #define E_NOTS 0x01 #define E_NOAS 0x02 #define E_WRAP 0x04 #define E_SLOW 0x08 #define E_HSE 0x10 #define CSR *(unsigned char *) (BASE + 0x5D) #define KEYREG *(unsigned char *) (BASE + 0x5D) #define FIFO *(unsigned short int *) (BASE + 0x60) #define FIFOB *(unsigned char *) (BA
#define #define B_bsrDAV B_ATN (BSR & 0x40) (BSR & 0x80) #define BCR *(unsigned char *) (BASE + 0x7D) #define E_REN 0x01 #define E_IFC 0x02 #define E_bcrSRQ 0x04 #define E_EOI 0x08 #define E_NRFD 0x10 #define E_NDAC 0x20 #define E_bcrDAV 0x40 #define E_ATN 0x80 #endif 18
MC68340.
#define MR2A *(unsigned char *) (MCBASE + 0x720) #define MR1B *(unsigned char *) (MCBASE + 0x718) #define SRB *(unsigned char *) (MCBASE + 0x719) #define CSRB *(unsigned char *) (MCBASE + 0x719) #define CRB *(unsigned char *) (MCBASE + 0x71A) #define RBB *(unsigned char *) (MCBASE + 0x71B) #define TBB *(unsigned char *) (MCBASE + 0x71B) #define MR2B *(unsigned char *) (MCBASE + 0x721) #define IPCR *(unsigned char *) (MCBASE + 0x714) #define ACR *(unsigned char *) (MCBASE + 0x714) #define ISR *(unsigned char
MC340BUG.H /*************************************************************************/ /* File Name : MC340BUG.H */ /* File Type : Header File */ /* Created On : 03/17/95 */ /* Modified On: 06/05/95 */ /* Created By : Faisal Habib */ /* Description: This header file declares the fuctions that are */ /* provided in the 340Bug Monitor. The functions use */ /* 340Bug Trap #15 handler, which allow system calls from */ /* user programs.
HARDWARE.H /**************************************************************************/ /* File Name : HARDWARE.H */ /* File Type : C header file */ /* Created On : 05/04/95 */ /* Modified On: 05/23/95 */ /* Created By : Faisal Habib */ /* Description: This header file contains macros and function prototypes */ /* for the source program. The source program will test the */ /* hardware interface for the TNT and MC68340.
HARDWARE.C /**************************************************************************/ /* File Name : HARDWARE.C */ /* File Type : C source file */ /* Created On : 05/04/95 */ /* Modified On: 05/24/95 */ /* Created By : Faisal Habib */ /* Description: This program will test the hardware interface for the */ /* TNT and MC68340. In particular it will test the three */ /* different types of I/O: Programmed, Interrupts, and DMA.
{ NEWLN(); PrintHex(counter); puts("Loop"); fail |= Programmed_IO_Test(); fail |= Interrupt_IO_Test(); /*fail |= DMA_IO_Test();*/ } break; default: NEWLN(); RET340BUG(); } if (fail) puts("\nHardware Diagnostics Completed. Board is not fully functional.\n"); else puts("\nHardware Diagnostics Completed. Board is fully functional.
/* 1. 8 Bit accesses to FIFO A */ /* 2. 8 Bit accesses to FIFO B */ /* 3. 16 Bit accesses to FIFOs */ /* 4. 8 Bit WRITES and 16 Bit READS */ /* 5. 16 Bit WRITES and 8 Bit READS */ /* */ /* Reference : MC68340 & TNT4882 Application Notes */ /**************************************************************************/ /**************************************************************************/ char Programmed_IO_Test() { char result = FALSE; HSSEL |= E_NODMA; puts("\nPerforming Programmed I/O Test.
formed.
/**************************************************************************/ /**************************************************************************/ char SetupDMA(unsigned char ioType,unsigned int count,unsigned short int *buffer) { DMAMCR1 = DMA_CONF; INTR1 = DMA_INTR; CCR1 = 0; CSR1 = 0x7C; /*clear status register */ FCR1 = DMA_SPACE; /*set for DMA space */ BTC1 = count; /*set the number of bytes */ switch (ioType) { case READ: /*READ from Memory */ CCR1 = DMA_READ; SAR1 = (unsigned int)buffer; break
/* Created On : 05/23/95 */ /* Modified On : 05/23/95 */ /* Description : This routine prints a selection screen so that the user */ /* can select a particular test. */ /* Reference : MC68340 & TNT4882 Application Notes */ /**************************************************************************/ /**************************************************************************/ char Select() { puts(" 1. Test Interface"); puts(" 2. Loop Test"); puts(" 3.
TEST4882.H /**************************************************************************/ /* File Name : TEST4882.H */ /* File Type : C header file */ /* Created On : 05/04/95 */ /* Modified On: 05/23/95 */ /* Created By : Faisal Habib */ /* Description: This header file contains function prototypes for the C */ /* source program.
TEST4882.C /**************************************************************************/ /* File Name : TEST4882.C */ /* File Type : C source file */ /* Created On : 05/04/95 */ /* Modified On: 05/24/95 */ /* Created By : Faisal Habib */ /* Description: This file contains routines that are used by the hardware */ /* test program to test the MC68340 & TNT4882 Interface.
} /**************************************************************************/ /**************************************************************************/ /* Module : InitializeTNT() */ /* Parameters : NONE */ /* Return Type : void */ /* Created On : 05/04/95 */ /* Modified On : 05/24/95 */ /* Description : This is the Initialization routine. This routine should*/ /* be called during the start up sequence. */ /* */ /* InitializeTNT places the TNT in one chip mode.
} return result; } /**************************************************************************/ /**************************************************************************/ /* Module : Test16BitRegister() */ /* Parameters : NONE */ /* Return Type : char */ /* Created On : 05/04/95 */ /* Modified On : 05/24/95 */ /* Description : This routine tests 16 bit accesses to the fifos. It */ /* writes then reads the pattern stored in TestBit16[].
if (StoredValue != TestBit16[Loop]) /*compare w/ values in TestBit16[]*/ { DisplayErrorMessage(StoredValue,TestBit16[Loop]); if (!(AskUser())) return ERROR; result = ERROR; } } return result; } /**************************************************************************/ /**************************************************************************/ /* Module : Test16Write8Read() */ /* Parameters : NONE */ /* Return Type : char */ /* Created On : 05/04/95 */ /* Modified On : 05/23/95 */ /* Description : This r
/* the fifos. The values are read during a READ interrupt.
puts(": Received Value"); } /**************************************************************************/ /**************************************************************************/ /* Module : AskUser() */ /* Parameters : NONE */ /* Return Type : char */ /* Created On : 05/04/95 */ /* Modified On : 05/04/95 */ /* Description : This routine prompts the user for the continuation of */ /* of a test.
