Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... µ MOTOROLA MC68340 Integrated Processor with DMA User’s Manual ©MOTOROLA INC., 1992 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Freescale Semiconductor, Inc. PREFACE Freescale Semiconductor, Inc... The complete documentation package for the MC68340 consists of the MC68340UM/AD, MC68340 Integrated Processor with DMA User’s Manual, M68000PM/AD, MC68000 Family Programmer’s Reference Manual, and the MC68340P/D, MC68340 Integrated Processor with DMA Product Brief.
11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS Paragraph Number Title Page Number Freescale Semiconductor, Inc... Section 1 Device Overview 1.1 1.1.1 1.1.2 1.2 1.2.1 1.2.2 1.3 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.1.5 1.3.1.6 1.3.1.7 1.3.2 1.3.3 1.3.4 1.4 1.5 1.6 1.7 M68300 Family..................................................................................................1-2 Organization ..................................................................
11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.9 2.9.1 2.9.2 2.9.3 2.10 2.10.1 2.10.2 2.10.3 2.10.4 2.11 2.11.1 2.11.2 2.11.3 2.11.4 2.12 2.12.1 2.12.2 2.12.3 2.13 2.13.1 2.13.2 2.13.3 2.13.4 2.13.5 2.13.6 2.13.7 2.13.8 2.14 2.14.1 2.14.2 2.14.3 iv Title Page Number Bus Control Signals .....................................................
11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Paragraph Number Freescale Semiconductor, Inc... 2.15 2.15.1 2.15.2 2.15.3 2.15.4 2.16 2.17 2.18 Title Page Number Test Signals.......................................................................................................2-13 Test Clock (TCK)...........................................................................................2-13 Test Mode Select (TMS)......................................
11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.4.1 3.4.4.2 3.4.4.3 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.7 Title Page Number CPU Space Cycles........................................................................................... 3-21 Breakpoint Acknowledge Cycle.................................................................
11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 4.2.4.2 4.2.5 4.2.5.1 4.2.5.2 4.2.6 4.2.7 4.3 4.3.1 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.2.4 4.3.2.5 4.3.2.6 4.3.2.7 4.3.2.8 4.3.3 4.3.4 4.3.4.1 4.3.4.2 4.3.4.3 4.3.5 4.3.5.1 4.3.5.2 4.3.5.3 4.3.5.4 4.3.5.5 4.3.5.6 4.3.5.7 4.4 4.4.1 4.4.2 4.4.3 Title Page Number Global Chip Select Operation ................................................................
11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 5.1.4 5.1.5 5.1.6 5.1.7 5.1.7.1 5.1.7.2 5.1.8 5.1.9 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.1.1 5.3.1.1.1 5.3.1.1.2 5.3.1.2 5.3.2 5.3.3 5.3.3.1 5.3.3.2 5.3.3.3 5.3.3.4 5.3.3.5 5.3.3.6 5.3.3.7 5.3.3.8 5.3.3.9 5.3.3.10 5.3.4 5.3.4.1 5.3.4.2 5.3.4.3 5.3.4.4 5.3.4.5 5.3.5 5.3.6 5.4 5.4.1 5.4.2 5.4.2.1 5.4.2.2 viii Title Page Number Vector Base Register.................
11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 5.4.2.3 5.5 5.5.1 5.5.1.1 5.5.1.2 5.5.1.3 5.5.1.4 5.5.2 5.5.2.1 5.5.2.2 5.5.2.3 5.5.2.4 5.5.2.5 5.5.2.6 5.5.2.7 5.5.2.8 5.5.2.9 5.5.2.10 5.5.2.11 5.5.2.12 5.5.3 5.5.3.1 5.5.3.1.1 5.5.3.1.2 5.5.3.1.3 5.5.3.1.4 5.5.3.2 5.5.3.2.1 5.5.3.2.2 5.5.3.2.3 5.5.3.2.4 5.5.3.2.5 5.5.3.2.6 5.5.3.2.7 5.5.4 5.5.4.1 5.5.4.2 5.5.4.3 5.6 5.6.1 5.6.1.1 5.6.1.
/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 5.6.1.3 5.6.2 5.6.2.1 5.6.2.2 5.6.2.2.1 5.6.2.2.2 5.6.2.2.3 5.6.2.3 5.6.2.4 5.6.2.5 5.6.2.5.1 5.6.2.5.2 5.6.2.5.3 5.6.2.6 5.6.2.7 5.6.2.7.1 5.6.2.7.2 5.6.2.8 5.6.2.8.1 5.6.2.8.2 5.6.2.8.3 5.6.2.8.4 5.6.2.8.5 5.6.2.8.6 5.6.2.8.7 5.6.2.8.8 5.6.2.8.9 5.6.2.8.10 5.6.2.8.11 5.6.2.8.12 5.6.2.8.13 5.6.2.8.14 5.6.2.8.15 5.6.2.8.16 5.6.3 5.6.3.1 5.6.3.2 5.6.3.3 5.7 5.
11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 5.7.1.3 5.7.1.3.1 5.7.1.3.2 5.7.1.3.3 5.7.1.4 5.7.1.5 5.7.1.6 5.7.1.7 5.7.2 5.7.2.1 5.7.2.2 5.7.2.3 5.7.3 5.7.3.1 5.7.3.2 5.7.3.3 5.7.3.4 5.7.3.5 5.7.3.6 5.7.3.7 5.7.3.8 5.7.3.9 5.7.3.10 5.7.3.11 5.7.3.12 5.7.3.13 5.7.3.14 Title Page Number Bus Controller Resources .......................................................................
11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 6.3.2.2 6.4 6.4.1 6.4.1.1 6.4.1.2 6.4.2 6.4.2.1 6.4.2.2 6.5 6.6 6.6.1 6.6.2 6.6.2.1 6.6.2.2 6.6.3 6.6.3.1 6.6.3.2 6.6.3.3 6.7 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.7.7 6.7.8 6.8 6.9 6.9.1 6.9.1.1 6.9.1.2 6.9.2 Title Page Number External Cycle Steal Mode .....................................................................6-5 Data Transfer Modes............
11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 7.1.5 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.8.1 7.2.8.2 7.2.9 7.2.9.1 7.2.9.2 7.2.10 7.2.11 7.2.12 7.2.12.1 7.2.12.2 7.2.13 7.2.13.1 7.2.13.2 7.2.13.3 7.3 7.3.1 7.3.2 7.3.2.1 7.3.2.2 7.3.2.3 7.3.3 7.3.3.1 7.3.3.2 7.3.3.3 7.3.4 7.3.5 7.3.5.1 7.3.5.2 7.3.5.3 7.4 7.4.1 7.4.1.
11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 7.4.1.2 7.4.1.3 7.4.1.4 7.4.1.5 7.4.1.6 7.4.1.7 7.4.1.8 7.4.1.9 7.4.1.10 7.4.1.11 7.4.1.12 7.4.1.13 7.4.1.14 7.4.1.15 7.4.1.16 7.4.1.17 7.4.2 7.4.2.1 7.4.2.2 7.4.2.3 7.5 7.5.1 7.5.2 Title Page Number Interrupt Level Register (ILR)..................................................................7-21 Interrupt Vector Register (IVR)..........................
11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.9.1 8.3.9.2 8.3.9.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.5 8.5.1 8.5.2 Title Page Number Variable Duty-Cycle Square-Wave Generator........................................8-9 Variable-Width Single-Shot Pulse Generator.........................................8-10 Pulse-Width Measurement..........
11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Concluded) Freescale Semiconductor, Inc... Paragraph Number 10.1.2 10.1.3 10.1.4 10.1.5 10.2 10.2.1 10.2.2 10.2.3 10.2.4 Title Page Number 10.3 10.3.1 10.3.2 Reset Circuitry .............................................................................................10-3 SRAM Interface ...........................................................................................10-3 ROM Interface.....................
SECTION 1: OVERVIEW Freescale Semiconductor, Inc. 11/2/95 UM Rev 1 LIST OF ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number Title Page Number 1-1 Block Diagram.........................................................................................................1-1 2-1 Functional Signal Groups .....................................................................................
SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 11/2/95 LIST OF ILLUSTRATIONS (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 4-5 4-6 4-7 4-8 MC68340 Crystal Oscillator..................................................................................4-10 Clock Block Diagram for External Oscillator Operation...................................4-11 Full Interrupt Request Multiplexer........................................................................
SECTION 1: OVERVIEW Freescale Semiconductor, Inc. 11/2/95 UM Rev 1 LIST OF ILLUSTRATIONS (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 DMA Block Diagram...............................................................................................6-1 Single-Address Transfers .....................................................................................6-3 Dual-Address Transfer................
SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 11/2/95 LIST OF ILLUSTRATIONS (Continued) Figure Number Freescale Semiconductor, Inc... 9-3 9-4 9-5 9-6 9-7 9-8 9-9 Title Page Number Output Latch Cell (O.Latch)...................................................................................9-7 Input Pin Cell (I.Pin)................................................................................................9-7 Active-High Output Control Cell (IO.Ctl1)..................................
SECTION 1: OVERVIEW Freescale Semiconductor, Inc. 11/2/95 UM Rev 1 LIST OF ILLUSTRATIONS (Concluded) Figure Number Serial Module Asynchronous Mode Timing (X1)............................................11-23 Serial Module Asynchronous Mode Timing (SCLK–16X)............................11-23 Serial Module Synchronous Mode Timing Diagram .....................................11-23 Test Clock Input Timing Diagram.......................................................................
SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 11/2/95 LIST OF TABLES Freescale Semiconductor, Inc... Table Number Title Page Number 2-1 2-2 2-3 2-4 2-5 Signal Index.............................................................................................................2-2 Address Space Encoding .....................................................................................2-5 DSACK≈ Encoding......................................................................................
SECTION 1: OVERVIEW Freescale Semiconductor, Inc. 11/2/95 UM Rev 1 LIST OF TABLES (Continued) Freescale Semiconductor, Inc... Table Number Title Page Number 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 8-Bit Independent Variable Entries .....................................................................5-33 Exception Vector Assignments.............................................................................5-40 Exception Priority Groups....................................................
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 1 DEVICE OVERVIEW The MC68340 is a high-performance 32-bit integrated processor with direct memory access (DMA), combining an enhanced M68000-compatible processor, 32-bit DMA, and other peripheral subsystems on a single integrated circuit. The MC68340 CPU32 delivers 32-bit CISC processor performance from a lower cost 16-bit memory system.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. 1.1.1 Organization Freescale Semiconductor, Inc... The M68300 family of integrated processors and controllers is built on an M68000 core processor, an on-chip bus, and a selection of intelligent peripherals appropriate for a set of applications. The CPU32 is a powerful central processor with nearly the performance of the MC68020.
Freescale Semiconductor, Inc. 1.2.1 CPU32 Freescale Semiconductor, Inc... The CPU32 is an M68000 family processor specially designed for use as a 32-bit core processor and for operation over the intermodule bus (IMB). Designers used the MC68020 as a model and included advances of the later M68000 family processors, resulting in an instruction execution performance of 4 MIPS (VAX-equivalent) at 25.16 MHz. The powerful and flexible M68000 architecture is the basis of the CPU32.
Freescale Semiconductor, Inc. Commands are received over a dedicated, high-speed, full-duplex serial interface. Commands allow the manual reading or writing of CPU32 registers, reading or writing of external memory locations, and diversion to user-specified patch code. This background debug mode permits a much simpler emulation environment while leaving the processor chip in the target system, running its own debugging operations. 1.3 ON-CHIP PERIPHERALS Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. memory system to signal the CPU32 or DMA when the transfer is complete and to note the number of bits in the transfer. An external master can arbitrate for the bus using a three-line handshaking interface. Freescale Semiconductor, Inc... 1.3.1.2 SYSTEM CONFIGURATION AND PROTECTION. The M68000 family of processors is designed with the concept of providing maximum system safeguards. System configuration and various monitors and timers are provided in the MC68340.
Freescale Semiconductor, Inc. 1.3.1.7 IEEE 1149.1 TEST ACCESS PORT. To aid in system diagnostics, the MC68340 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (Joint Test Action Group). 1.3.2 Direct Memory Access Module Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive buffers and two-byte transmit buffers minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is provided on each channel. Full-duplex, autoecho loopback, local loopback, and remote loopback modes can be selected. Multidrop applications are supported.
Freescale Semiconductor, Inc. requires only a 3.3-V power supply, reduces current consumption by 40–60% in all modes of operation (as well as reducing noise emissions). Freescale Semiconductor, Inc... The MC68340 has many additional methods of dynamically controlling power consumption during operation. The frequency of operation can be lowered under software control to reduce current consumption when performance is less critical.
Freescale Semiconductor, Inc. 1.7 MORE INFORMATION The following table lists available documentation related to the MC68340: Document Number BR1114/D MC68340/D MC68340UM/AD M68000PM/AD AN1063/D Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. 2.1 SIGNAL INDEX The input and output signals for the MC68340 are listed in Table 2-1. The name, mnemonic, and brief functional description are presented. For more detail on each signal, refer to the signal paragraph. Guaranteed timing specifications for the signals listed in Table 2-1 can be found in Section 11 Electrical Characteristics. Table 2-1. Signal Index Signal Name Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 2-1.
Freescale Semiconductor, Inc. NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 2.2 ADDRESS BUS Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68340 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle. 2.4 FUNCTION CODES (FC3–FC0) Freescale Semiconductor, Inc... These signals are outputs that indicate one of 16 address spaces to which the address applies.
Freescale Semiconductor, Inc. Port B4, B2, B1, AVEC This signal group functions as three bits of parallel I/O and the autovector input. AVEC requests an automatic vector during an interrupt acknowledge cycle. 2.6 INTERRUPT REQUEST LEVEL (IRQ7, IRQ6, IRQ5, IRQ3) These pins can be programmed to be either prioritized interrupt request lines or port B parallel I/O. Freescale Semiconductor, Inc... IRQ7, IRQ6, IRQ5, IRQ3 IRQ7 , the highest priority, is nonmaskable. IRQ6–IRQ1 are internally maskable interrupts.
Freescale Semiconductor, Inc. 2.7.3 Data Strobe (DS) DS is an output timing signal that applies to the data bus. For a read cycle, the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus. For a write cycle, DS signals to the external device that the data to be written is valid. The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle. 2.7.
Freescale Semiconductor, Inc. 2.8.4 Read-Modify-Write Cycle (RMC) This output signal identifies the bus cycle as part of an indivisible read-modify-write operation. It remains asserted during all bus cycles of the read-modify-write operation to indicate that bus ownership cannot be transferred. 2.9 EXCEPTION CONTROL SIGNALS These signals are used by the MC68340 to recover from an exception. Freescale Semiconductor, Inc... 2.9.
Freescale Semiconductor, Inc. 2.10.2 Crystal Oscillator (EXTAL, XTAL) These two pins are the connections for an external crystal to the internal oscillator circuit. If an external oscillator is used, it should be connected to EXTAL, with XTAL left open. 2.10.3 External Filter Capacitor (XFC) This pin is used to add an external capacitor to the filter circuit of the phase-locked loop. The capacitor should be connected between XFC and VCCSYN. 2.10.4 Clock Mode Select (MODCK) Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. IPIPE This active-low output signal is used to track movement of words through the instruction pipeline. DSO This development serial output signal helps to provide serial communications for background debug mode. 2.11.3 Breakpoint (BKPT) Freescale Semiconductor, Inc... This pin functions as BKPT in normal operation and as DSCLK in background debug mode. BKPT This active-low input signal is used to signal a hardware breakpoint to the CPU32.
Freescale Semiconductor, Inc. 2.13 SERIAL MODULE SIGNALS The following signals are used by the serial module for data and clock signals. See Section 7 Serial Module for more information on these signals. 2.13.1 Serial Crystal Oscillator (X2, X1) These pins furnish the connection to a crystal or external clock, which must be supplied when using the baud rate generator. An external clock is connected to the X1 pin; X2 is left floating. Freescale Semiconductor, Inc... 2.13.
Freescale Semiconductor, Inc. T≈RDYA When used for this function, this signal reflects the complement of the status of bit 2 of the channel A status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character. OP6 When used for this function, this output is controlled by bit 6 in the output port data registers. 2.13.8 Receiver Ready (R≈RDYA) Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 2.15 TEST SIGNALS The following signals are used with the on-board test logic defined by the IEEE 1149.1 standard. See Section 9 IEEE 1149.1 Test Access Port for more information on the use of these signals. 2.15.1 Test Clock (TCK) This input provides a clock for on-board test logic defined by the IEEE 1149.1 standard. 2.15.2 Test Mode Select (TMS) Freescale Semiconductor, Inc... This input controls test mode operations for on-board test logic defined by the IEEE 1149.
Freescale Semiconductor, Inc. Table 2-5.
Freescale Semiconductor, Inc. Table 2-5.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 3 BUS OPERATION This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and reset operation. Operation of the external bus is the same whether the MC68340 or an external device is the bus master; the names and descriptions of bus cycles are from the viewpoint of the bus master.
Freescale Semiconductor, Inc. the sample window. If an input makes a transition during the window time period, the level recognized by the MC68340 is not predictable; however, the MC68340 always resolves the latched level to either a logic high or low before using it. In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section. t su th Freescale Semiconductor, Inc... CLKOUT EXT SAMPLE WINDOW Figure 3-1.
Freescale Semiconductor, Inc. Table 3-1. SIZx Signal Encoding SIZ1 SIZ0 Transfer Size 0 1 Byte 1 0 Word 1 1 Three Bytes 0 0 Long Word Freescale Semiconductor, Inc... 3.1.2 Function Code Signals FC3–FC0 are outputs that indicate one of 16 address spaces to which the address applies. Fifteen of these spaces are designated as either user or supervisor, program or data, and normal or direct memory access (DMA) spaces.
Freescale Semiconductor, Inc. 3.1.3 Address Bus (A31–A0) These signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MC68340 places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. 3.1.4 Address Strobe ( AS) This output timing signal indicates the validity of many control signals and the address on the address bus.
Freescale Semiconductor, Inc. 3.1.7.2 BUS ERROR (BERR). This signal is also a bus cycle termination indicator and can be used in the absence of DSACK≈ to indicate a bus error condition. BERR can also be asserted in conjunction with DSACK≈ to indicate a bus error condition, provided it meets the appropriate timing described in this section and in Section 11 Electrical Characteristics. Additionally, BERR and HALT can be asserted together to indicate a retry termination. Refer to 3.
Freescale Semiconductor, Inc. For example, if the MC68340 is executing an instruction that reads a long-word operand from a 16-bit port, the MC68340 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation from an 8-bit port is similar, but requires four read cycles. The addressed device uses DSACK≈ to indicate the port width. For instance, a 16-bit device always returns DSACK≈ for a 16-bit port (regardless of whether the bus cycle is a byte or word operation).
Freescale Semiconductor, Inc. OPERAND OP0 OP1 OP0 31 OP3 OP2 OP1 OP0 OP2 OP1 OP0 23 15 7 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. BYTE OPERAND OP0 0 7 DATA BUS CYCLE 1 D15 D8 D7 D0 OP0 (OP0) SIZ1 0 SIZ0 1 A0 X DSACK1 DSACK0 1 0 Freescale Semiconductor, Inc... For a read operation, the slave responds by placing data on bits 15–8 of the data bus, asserting DSACK0 and negating DSACK1 to indicate an 8-bit port. The MC68340 then reads the operand byte from bits 15–8 and ignores bits 7–0.
Freescale Semiconductor, Inc. 3.2.3.3 BYTE OPERAND TO 16-BIT PORT, ODD (A0 = 1). The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single-byte operand. BYTE OPERAND OP0 0 7 DATA BUS CYCLE 1 D15 D8 D7 D0 (OP0) OP0 SIZ1 0 SIZ0 1 A0 1 DSACK1 DSACK0 0 X Freescale Semiconductor, Inc... For a read operation, the slave responds by placing data on bits 7–0 of the data bus and asserting DSACK1 to indicate a 16-bit port.
Freescale Semiconductor, Inc. 3.2.3.5 WORD OPERAND TO 16-BIT PORT, ALIGNED. The MC68340 drives the address bus with the desired address and the size pins to indicate a word operand. WORD OPERAND OP0 OP1 15 0 D15 D8 D7 D0 DATA BUS CYCLE 1 OP0 OP1 SIZ1 1 SIZ0 0 A0 0 DSACK1 DSACK0 0 X Freescale Semiconductor, Inc... For a read operation, the slave responds by placing the data on bits 15–0 of the data bus and asserting DSACK1 to indicate a 16-bit port.
Freescale Semiconductor, Inc. S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 CLKOUT A31–A0 Freescale Semiconductor, Inc... FC3–FC0 R/W AS DS SIZ0 4 BYTES 3 BYTES 2 BYTES 1 BYTE SIZ1 DSACK0 DSACK1 OP0 D15–D8 OP1 OP3 OP2 D7–D0 BYTE READ BYTE BYTE READ READ LONG-WORD OPERAND READ FROM 8-BIT BUS BYTE READ Figure 3-3. Long-Word Operand Read Timing from 8-Bit Port MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 CLKOUT A31–A0 FC3–FC0 R/W AS Freescale Semiconductor, Inc... DS SIZ0 3 BYTES 4 BYTES 1 BYTE 2 BYTES SIZ1 DSACK0 DSACK1 D15–D8 OP0 OP1 OP2 OP3 D7–D0 (OP1) (OP1) (OP3) (OP3) WRITE WRITE WRITE WRITE LONG-WORD OPERAND WRITE TO 8-BIT BUS Figure 3-4. Long-Word Operand Write Timing to 8-Bit Port 3.2.3.7 LONG-WORD OPERAND TO 16-BIT PORT, ALIGNED.
Freescale Semiconductor, Inc. S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S4 S2 CLKOUT A31–A0 FC3–FC0 R/W AS Freescale Semiconductor, Inc... DS SIZ0 2 BYTES 4 BYTES 2 BYTES 4 BYTES 2 BYTES 2 BYTES SIZ1 DSACK0 DSACK1 D15–D8 OP0 OP2 OP0 OP0 OP2 OP0 D7–D0 OP1 OP3 OP1 OP1 OP3 OP1 LONG WORD READ FROM 16-BIT BUS WORD READ FROM 16-BIT BUS LONG WORD WRITE TO 16-BIT BUS WORD WRITE TO 16-BIT BUS Figure 3-5.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 3.2.4 Bus Operation The MC68340 bus is asynchronous, allowing external devices connected to the bus to operate at clock frequencies different from the clock for the MC68340. Bus operation uses the handshake lines (AS, DS, DSACK1/DSACK0, BERR, and HALT ) to control data transfers. AS signals a valid address on the address bus, and DS is used as a condition for valid data on a write cycle.
Freescale Semiconductor, Inc. If a system asserts DSACK≈ for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACK≈ (and/or BERR/ HALT) until and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles terminated with DSACK≈ (three clocks per cycle).
Freescale Semiconductor, Inc. 3.3 DATA TRANSFER CYCLES The transfer of data between the MC68340 and other devices involves the following signals: • Address Bus A31–A0 • Data Bus D15–D0 Freescale Semiconductor, Inc... • Control Signals The address bus and data bus are parallel, nonmultiplexed buses. The bus master moves data on the bus by issuing control signals, and the bus uses a handshake protocol to ensure correct movement of the data.
Freescale Semiconductor, Inc. State 0—The read cycle starts in state 0 (S0). During S0, the MC68340 places a valid address on A31–A0 and valid function codes on FC3–FC0. The function codes select the address space for the cycle. The MC68340 drives R/ W high for a read cycle. SIZ1/SIZ0 become valid, indicating the number of bytes requested for transfer. State 1—One-half clock later, in state 1 (S1), the MC68340 asserts AS indicating a valid address on the address bus. The MC68340 also asserts DS during S1.
Freescale Semiconductor, Inc. 3.3.2 Write Cycle During a write cycle, the MC68340 transfers data to memory or a peripheral device. Figure 3-8 is a flowchart of a word write cycle. BUS MASTER SLAVE ADDRESS DEVICE Freescale Semiconductor, Inc... 1. 2. 3. 4. 5. 6. 7. SET R/W TO WRITE DRIVE ADDRESS ON A31–A0 DRIVE FUNCTION CODE ON FC3–FC0 DRIVE SIZE PINS FOR OPERAND SIZE ASSERT AS PLACE DATA ON D15–D0 ASSERT DS TERMINATE OUTPUT TRANSFER ACCEPT DATA 1. DECODE ADDRESS 2. LATCH DATA FROM D15–D0 3.
Freescale Semiconductor, Inc. State 4—The MC68340 issues no new control signals during S4. State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/ W, SIZ1/SIZ0, and FC3– FC0 also remain valid throughout S5. The external device must keep DSACK≈ asserted until it detects the negation of AS or DS (whichever it detects first).
Freescale Semiconductor, Inc. State 0—The MC68340 asserts RMC in S0 to identify a read-modify-write cycle. The MC68340 places a valid address on A31–A0 and valid function codes on FC3–FC0. The function codes select the address space for the operation. SIZ1/SIZ0 become valid in S0 to indicate the operand size. The MC68340 drives R/W high for the read cycle. State 1—One-half clock later during S1, the MC68340 asserts AS indicating a valid address on the address bus. The MC68340 also asserts DS during S1.
Freescale Semiconductor, Inc. proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK≈ on the falling edges of the clock until one is recognized. The selected device uses R/ W, DS, SIZ1/SIZ0, and A0 to latch data from the appropriate section(s) of D15–D8 and D7–D0. SIZ1/SIZ0 and A0 select the data bus sections.
Freescale Semiconductor, Inc. 3.4.1 Breakpoint Acknowledge Cycle Freescale Semiconductor, Inc... The breakpoint acknowledge cycle allows external hardware to insert an instruction directly into the instruction pipeline as the program executes. The breakpoint acknowledge cycle is generated by the execution of a breakpoint instruction (BKPT) or the assertion of the BKPT pin. The T-bit state (shown in Figure 3-10) differentiates a software breakpoint cycle (T = 0) from a hardware breakpoint cycle (T = 1).
Freescale Semiconductor, Inc. 3.4.2 LPSTOP Broadcast Cycle Freescale Semiconductor, Inc... The low power stop (LPSTOP) broadcast cycle is generated by the CPU32 executing the LPSTOP instruction. Since the external bus interface must get a copy of the interrupt mask level from the CPU32, the CPU32 performs a CPU space type 3 write with the mask level encoded on the data bus, as shown in the following figure.
Freescale Semiconductor, Inc. BREAKPOINT OPERATION FLOW EXTERNAL DEVICE PROCESSOR ACKNOWLEDGE BREAKPOINT Freescale Semiconductor, Inc... IF BREAKPOINT INSTRUCTION EXECUTED: 1. SET R/W TO READ 2. SET FUNCTION CODE TO CPU SPACE 3. PLACE CPU SPACE TYPE 0 ON A19–A16 4. PLACE BREAKPOINT NUMBER ON A2–A4 5. CLEAR T-BIT (A1) 6. SET SIZE TO WORD 7. ASSERT AS AND DS IF BKPT PIN ASSERTED: 1. SET R/W TO READ 2. SET FUNCTION CODE TO CPU SPACE 3. PLACE CPU SPACE TYPE 0 ON A19–A16 4. PLACE ALL ONE'S ON A4–A2 5.
Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 CLKOUT A31–A20 A19–A16 BREAKPOINT ENCODING (0000) A4–A1 BREAKPOINT NUMBER/T-BIT Freescale Semiconductor, Inc... A15–A5,A0 FC3–FC0 CPU SPACE SIZ0 SIZ1 AS DS R/W DSACKx D7–D0 D15–D8 BERR HALT BKPT BREAKPOINT OCCURS READ BREAKPOINT ACKNOWLEDGE INSTRUCTION WORD FETCH FETCHED INSTRUCTION EXECUTION Figure 3-12.
Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 CLKOUT A31–A20 BREAKPOINT ENCODING (0000) A19–A16 BREAKPOINT NUMBER/T-BIT A4–A1 Freescale Semiconductor, Inc... A15–A5, A0 FC3–FC0 CPU SPACE SIZ0 SIZ1 AS DS R/W DSACKx D7–D0 D15–D8 BERR HALT BKPT BREAKPOINT OCCURS READ BREAKPOINT ACKNOWLEDGE BUS ERROR ASSERTED EXCEPTION STACKING Figure 3-13.
Freescale Semiconductor, Inc. 3.4.3 Module Base Address Register Access All internal module registers, including the SIM40, occupy a single 4-Kbyte block that is relocatable along 4-Kbyte boundaries. The location is fixed by writing the desired base address of the SIM40 block to the module base address register using the MOVES instruction. The module base address register is only accessible in CPU space at address $0003FF00.
Freescale Semiconductor, Inc. The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in 3.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences are as follows: 1. FC3–FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space. Freescale Semiconductor, Inc... 2. A3, A2, and A1 are set to the interrupt request level, and the IACK≈ strobe corresponding to the current interrupt level is asserted.
Freescale Semiconductor, Inc. S0 S2 S4 S0 0–2 CLOCKS* S1 S2 S4 S0 S2 CLKOUT A31–A4 A3–A1 INTERRUPT LEVEL A0 Freescale Semiconductor, Inc... FC3–FC0 CPU SPACE SIZ0 1 BYTE SIZ1 R/W AS DS VECTOR FROM 16-BIT PORT DSACKx VECTOR FROM 8-BIT PORT D7–D0 D15–D8 IRQ7–IRQ1 IACK7–IACK1 READ CYCLE WRITE STACK INTERNAL ARBITRATION IACK CYCLE *Internal Arbitration may take between 0–2 clock cycles. Figure 3-15. Interrupt Acknowledge Cycle Timing 3.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... data will be ignored if AVEC is asserted before or at the same time as the DSACK≈ signals. The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When AVEC is asserted instead of DSACK≈ during an interrupt acknowledge cycle, the MC68340 ignores the state of the data bus and internally generates the vector number (the sum of the interrupt level plus 24 ($18)).
Freescale Semiconductor, Inc. S0 S2 S4 S0 0–2 CLOCKS* S1 S2 S4 S0 S2 CLKOUT A31–A4 A3–A1 INTERRUPT LEVEL Freescale Semiconductor, Inc... A0 FC3–FC0 CPU SPACE SIZ0 1 BYTE SIZ1 R/W AS DS DSACKx D15–D0 AVEC IRQ7–IRQ1 IACK7–IACK1 CYCLE READ WRITE STACK INTERNAL ARBITRATION IACK CYCLE * Internal Arbitration may take between 0–2 clocks. Figure 3-16. Autovector Operation Timing MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 3.5 BUS EXCEPTION CONTROL CYCLES The bus architecture requires assertion of DSACK≈ from an external device to signal that a bus cycle is complete. Neither DSACK≈ nor AVEC is asserted in the following cases: • DSACK≈/AVEC is programmed to respond internally. • The external device does not respond. Freescale Semiconductor, Inc... • Various other application-dependent errors occur.
Freescale Semiconductor, Inc. EXAMPLE B: A system uses error detection and correction on RAM contents. The designer may: 1. Delay DSACK≈ until data is verified and assert BERR and HALT simultaneously to indicate to the MC68340 to automatically retry the error cycle (case 5), or if data is valid, assert DSACK≈ (case 1). 2. Delay DSACK≈ until data is verified and assert BERR with or without DSACK≈ if data is in error (case 3). This initiates exception processing for software handling of the condition.
Freescale Semiconductor, Inc. 3.5.1 Bus Errors Freescale Semiconductor, Inc... BERR can be used to abort the bus cycle and the instruction being executed. BERR takes precedence over DSACK≈ provided it meets the timing constraints described in Section 11 Electrical Characteristics. If BERR does not meet these constraints, it may cause unpredictable operation of the MC68340. If BERR remains asserted into the next bus cycle, it may cause incorrect operation of that cycle.
Freescale Semiconductor, Inc. S0 S2 SW SW S4 S0 S2 S4 CLKOUT Freescale Semiconductor, Inc... A31–A0 FC3–FC0 R/W AS DS DSACKx D15–D0 BERR READ CYCLE WITH BUS ERROR INTERNAL PROCESSING STACK WRITE Figure 3-17. Bus Error without DSACK≈ MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. S0 S2 S4 S0 S2 S4 CLKOUT A31–A0 FC3–FC0 R/W Freescale Semiconductor, Inc... AS DS DSACKx D15–D0 BERR WRITE CYCLE INTERNAL PROCESSING STACK WRITE Figure 3-18. Late Bus Error with DSACK≈ 3.5.2 Retry Operation When both BERR and HALT are asserted by an external device during a bus cycle, the MC68340 enters the retry sequence shown in Figure 3-19. A delayed retry, which is similar to the delayed BERR signal described previously, can also occur (see Figure 3-20).
Freescale Semiconductor, Inc. S0 S2 SW SW S4 S0 S2 S4 CLKOUT A31–A0 FC3–FC0 R/W Freescale Semiconductor, Inc... AS DS DSACKx D15–D0 DATA IGNORED BERR HALT READ CYCLE WITH RETRY HALT READ RERUN Figure 3-19. Retry Sequence The MC68340 retries any read or write cycle of a read-modify-write operation separately; RMC remains asserted during the entire retry sequence. Asserting BR along with BERR and HALT provides a relinquish and retry operation.
Freescale Semiconductor, Inc. S0 S2 S4 S0 S2 S4 CLKOUT A31–A0 FC3–FC0 R/W AS Freescale Semiconductor, Inc... DS DSACKx D15–D10 BERR HALT WRITE CYCLE HALT WRITE RERUN Figure 3-20. Late Retry Sequence 3.5.3 Halt Operation When HALT is asserted and BERR is not asserted, the MC68340 halts external bus activity at the next bus cycle boundary (see Figure 3-21). HALT by itself does not terminate a bus cycle.
Freescale Semiconductor, Inc. asserted, the A31–A0, FCx, SIZx, and R/ W signals are again driven to their previous states. The MC68340 does not service interrupt requests while it is halted. S0 S2 S0 S4 S2 S4 S0 CLKOUT A31–A0 FC3–FC0 Freescale Semiconductor, Inc... R/W AS DS DSACKx D15–D10 HALT BR BG BGACK READ HALT (ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) READ Figure 3-21. HALT Timing 3.5.
Freescale Semiconductor, Inc. occurs during the stacking operation, the second error is considered a double bus fault. When a double bus fault occurs, the MC68340 halts and asserts HALT. Only a reset operation can restart a halted MC68340. However, bus arbitration can still occur (see 3.6 Bus Arbitration). A second bus error or address error that occurs after exception processing has completed (during the execution of the exception handler routine or later) does not cause a double bus fault.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Figure 3-22 is a flowchart showing bus arbitration for a single device. This technique allows processing of bus requests during data transfer cycles. Refer to Figures 3-23 and 3-24 for bus arbitration timing diagrams. BR is negated at the time that BGACK is asserted. This type of operation applies to a system consisting of the MC68340 and one device capable of bus mastership.
Freescale Semiconductor, Inc. CLKOUT A31–A0 D15–D0 AS BR Freescale Semiconductor, Inc... BG BGACK Figure 3-23. Bus Arbitration Timing Diagram—Idle Bus Case S0 S1 S2 S3 S4 S5 CLKOUT A31–A0 D15–D0 AS DS R/W DSACK0, DSACK1 BR BG BGACK Figure 3-24. Bus Arbitration Timing Diagram—Active Bus Case 3-42 MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 3.6.1 Bus Request External devices capable of becoming bus masters request the bus by asserting BR. This signal can be wire-ORed to indicate to the MC68340 that some external device requires control of the bus. The MC68340 is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started).
Freescale Semiconductor, Inc. 3.6.4 Bus Arbitration Control Freescale Semiconductor, Inc... The bus arbitration control unit in the MC68340 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68340 are internally synchronized in a maximum of two cycles of the clock. As shown in Figure 3-25 input signals labeled R and A are internally synchronized versions of B R and BGACK respectively.
Freescale Semiconductor, Inc. RA + B GTV AB STATE 0 RA Freescale Semiconductor, Inc... RAB RA G TV RA STATE 3 R+A G TV STATE 2 R A +A G TV R R STATE 5 RA G TV RA STATE 6 RA R - BUS REQUEST A - BUS GRANT ACKNOWLEDGE B - BUS CYCLE IN PROGRESS G - BUS GRANT T - THREE-STATE SIGNAL TO BUS CONTROL V - BUS AVAILABLE TO BUS CONTROL Figure 3-25. Bus Arbitration State Diagram MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. State 0—During state 0, the A31–A0 and FCx become valid, R/ W is driven to indicate a show read or write cycle, and the SIZx pins indicate the number of bytes to transfer. During a read, the addressed peripheral is driving the data bus, and the user must take care to avoid bus conflicts. State 41—One-half clock cycle later, DS (rather than AS ) is asserted to indicate that address information is valid. Freescale Semiconductor, Inc... State 42—No action occurs in state 42.
Freescale Semiconductor, Inc. 3. INTRST (internal reset) goes to all other internal circuits. Synchronous reset sources are not asserted until the end of the current bus cycle, whether or not RMC is asserted. The internal bus monitor is automatically enabled for synchronous resets; therefore, if the current bus cycle does not terminate normally, the bus monitor terminates it. Only single-byte or word transfers are guaranteed valid for synchronous resets.
Freescale Semiconductor, Inc. CLKOUT VCO LOCK VCC 328 × TCLKIN 512 × TCLKOUT ≤ 14 CLOCKS RESET BUS CYCLES ADDRESS AND CONTROL SIGNALS THREE-STATED Freescale Semiconductor, Inc... BUS STATE UNKNOWN 1 2 3 4 NOTES: 1. Internal start-up time. 2. SSP read here. 3. PC read here. 4. First instruction fetched here. Figure 3-28. Power-Up Reset Timing Diagram When a RESET instruction is executed, the MC68340 drives the RESET signal for 512 clock cycles.
Freescale Semiconductor, Inc. SECTION 4 SYSTEM INTEGRATION MODULE Freescale Semiconductor, Inc... The MC68340 system integration module (SIM40) consists of several functions that control the system start-up, initialization, configuration, and the external bus with a minimum of external devices. It also provides the IEEE 1149.1 boundary scan capabilities.
Freescale Semiconductor, Inc. The external bus interface (EBI) handles the transfer of information between the internal CPU32 and memory, peripherals, or other processing elements in the external address space. See Section 3 Bus Operation for further information. Freescale Semiconductor, Inc... The MC68340 dynamically interprets the port size of an addressed device during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-bit ports.
Freescale Semiconductor, Inc. $FFFFFFFF $XXXXXFFF MC68340 RELOCATABLE MODULE BLOCK $FFF $7BF DMA $780 $721 $XXXXX000 SERIAL PORTS $700 . $67F TIMER MODULES $600 Freescale Semiconductor, Inc... $07F SIM 40 $000 MBAR ($0003FF00 FC=0111) RAM (TYPICAL) $00000000 NOTE: $XXXXX is the value contained in the MBAR bits BA31-BA12. Figure 4-1. SIM40 Module Register Block 4.2.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Internal Bus Monitor The SIM40 provides an internal bus monitor to monitor the DSACK≈ response time for all internal bus accesses. An option allows the monitoring of external bus accesses. For external bus accesses, four selectable response times are provided to allow for variations in response speed of memory and peripherals used in the system. A bus error signal is asserted internally if the DSACK≈ response limit is exceeded.
Freescale Semiconductor, Inc. MODULE CONFIGURATION RESET STATUS DOUBLE BUS FAULT MONITOR Freescale Semiconductor, Inc... BUS MONITOR HALT RESET REQUEST BERR SPURIOUS INTERRUPT MONITOR SOFTWARE WATCHDOG CLOCK 29 PRESCALER PERIODIC INTERRUPT TIMER SOFTWARE RESET REQUEST or IRQ7 IRQ7-IRQ1 Figure 4-2. System Configuration and Protection Function 4.2.2.1 SYSTEM CONFIGURATION. Aspects of the system configuration are controlled by the MCR and the autovector register (AVR).
Freescale Semiconductor, Inc. There are eight arbitration levels for access to the intermodule bus (IMB). The SIM40 is fixed at the highest level (above the programmable level 7), and the CPU32 is fixed at the lowest level (below level 0). The direct memory access (DMA) module is the only other module that can become bus master and arbitrate for the bus. It must be initialized with a level other than 0 or 7. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. interrupt (as programmed by the SWRI bit in the SYPCR). The address of the interrupt service routine for the software watchdog interrupt is stored in the software interrupt vector register (SWIV). Figure 4-3 shows a block diagram of the software watchdog as well as the clock control circuits for the periodic interrupt timer. The watchdog clock rate is determined by the SWP bit in the periodic interrupt timer register (PITR) and the SWT bits in the SYPCR.
Freescale Semiconductor, Inc. 4.2.2.6.1 Periodic Timer Period Calculation. The period of the periodic timer can be calculated using the following equation: periodic interrupt timer period = PITR count value EXTAL frequency/prescaler value 22 Freescale Semiconductor, Inc... Solving the equation using a crystal frequency of 32.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 4.2.2.6.2 Using the Periodic Timer as a Real-Time Clock. The periodic interrupt timer can be used as a real-time clock interrupt by setting it up to generate an interrupt with a one-second period.
Freescale Semiconductor, Inc. using crystal mode, the system clock frequency is programmable (using the W, X, and Y bits in the SYNCR) over the range specified in Section 11 Electrical Characteristics (see Table 4-2.). VDDSYN XFC 1 330 K 20 pF 20 pF 0.1 µF 20 M EXTAL XTAL Freescale Semiconductor, Inc... CRYSTAL OSCILLATOR 0.1 µF V DDSYN XFC PIN LOW-PASS FILTER PHASE COMPARATOR 0.
Freescale Semiconductor, Inc. To use an external clock source (see Figure 4-6), the operating clock frequency can be driven directly into the EXTAL pin (the XTAL pin must be left floating for this case). This approach results in a system clock and CLKOUT that are the same as the input signal frequency, but not tightly coupled to it. To enable this mode, MODCK must be held low during reset, and VCCSYN held at 0 V while the chip is in operation. VCCSYN XFC 1 0.
Freescale Semiconductor, Inc. this compare is low-pass filtered and used to control the VCO. The comparator also detects when the external crystal or oscillator stops running to initiate the limp mode for the system clock. Freescale Semiconductor, Inc... The PLL requires an external low-leakage filter capacitor, typically in the range from 0.01 to 0.1 µF, connected between the XFC and VCCSYN pins. The XFC capacitor should provide 50-MΩ insulation but should not be electrolytic.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 4-2. System Frequencies from 32.
Freescale Semiconductor, Inc. 4.2.4.1 PROGRAMMABLE FEATURES. The chip select function supports the following programmable features: Freescale Semiconductor, Inc... Four Programmable Chip Select Circuits All four chip select circuits are independently programmable from the same list of selectable features. Each chip select circuit has an individual base address register and address mask register that contain the programmed characteristics of that chip select.
Freescale Semiconductor, Inc. NOTE Freescale Semiconductor, Inc... If an access matches multiple chip selects, the lowest numbered chip select will have priority. For example, if CS0 and CS2 "overlap" for a certain range, CS0 will assert when accessing the "overlapped" address range, and CS2 will not.
Freescale Semiconductor, Inc. 4.2.5.2 PORT B. Port B pins can be independently programmed to function as chip selects, IRQ ≈ and MODCK pins, or discrete I/O pins. These pins are multiplexed as shown in Figure 4-7. Selection of a pin function is accomplished by a combination of the port B pin assignment register (PPARB) and the FIRQ bit of the MCR. See Table 4-5 for port B combinations.
Freescale Semiconductor, Inc. The number of wait states programmed into the internal wait state generation logic by a chip select can be used even though the pin is not used as a C S ≈ signal. The programmed number of wait states in the CS≈ signal applies to the port B pins configured as IRQ≈ or I/O pins. This is done by programming the chip select with the number of wait states to be added, as though it were to be used.
Freescale Semiconductor, Inc. the MCR disables the software watchdog and periodic interrupt timer, and setting the FRZ0 bit in the MCR disables the bus monitor. 4.3 PROGRAMMING MODEL Freescale Semiconductor, Inc... Figure 4-8 is a programming model (register map) of all registers in the SIM40. For more information about a particular register, refer to the description of the module or function indicated in the right column.
Freescale Semiconductor, Inc. ADDR FC 000 S 15 8 7 0 MODULE CONFIGURATION REGISTER (MCR) SYSTEM PROTECTION 004 S 006 S CLOCK SYNTHESIZER CONTROL REGISTER (SYNCR) AUTOVECTOR REGISTER (AVR) RESET STATUS REGISTER (RSR) CLOCK SYSTEM Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 4.3.1 Module Base Address Register (MBAR) MBAR 1 $0003FF00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 IBA18 BA17 BA16 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU Space Only Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. NOTE An access to this register does not affect external space since the cycle is not run externally. Example code for accessing the MBAR is as follows: Register D0 will contain the value of MBAR. MBAR can be read using the following code: Freescale Semiconductor, Inc... MOVE.L MOVEC.L LEA.L MOVES.
Freescale Semiconductor, Inc. FRZ0—Freeze Bus Monitor Enable 1 = When FREEZE is asserted, the bus monitor is disabled. 0 = When FREEZE is asserted, the bus monitor continues to operate as programmed. Freescale Semiconductor, Inc... FIRQ—Full Interrupt Request Mode 1 = Configures port B for seven interrupt request lines, autovector, and no external chip selects. 0 = Configures port B for four interrupt request lines and four external chip selects. See Table 4-5 for pin function selection.
Freescale Semiconductor, Inc. value of $0 prevents arbitration and causes all SIM40 interrupts, including external interrupts, to be discarded as extraneous. 4.3.2.2 AUTOVECTOR REGISTER (AVR). The AVR contains bits that correspond to external interrupt levels that require an autovector response. Setting a bit allows the SIM40 to assert an internal AVEC during the IACK cycle in response to the specified interrupt request level. This register can be read and written at any time. Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. LOC—Loss of Clock Reset 1 = The last reset was caused by a loss of frequency reference to the clock synthesizer. This reset can only occur if the RSTEN bit in the SYNCR is set and the VCO is enabled. Freescale Semiconductor, Inc... SYS—System Reset 1 = The last reset was caused by the CPU32 executing a RESET instruction.
Freescale Semiconductor, Inc. SWT1, SWT0—Software Watchdog Timing These bits, along with the SWP bit in the PITR, control the divide ratio used to establish the timeout period for the software watchdog. The software watchdog timeout period is given by the following formula: divide count EXTAL frequency The software watchdog timeout period, listed in Table 4-7, gives the formula to derive the software watchdog timeout for any clock frequency. The timeout periods are listed for a 32.
Freescale Semiconductor, Inc. Table 4-8. BMTx Encoding BMT1 BMT0 0 0 64 system clocks (CLKOUT) Bus Monitor Timeout Period 0 1 32 system clocks 1 0 16 system clocks 1 1 8 system clocks Freescale Semiconductor, Inc... 4.3.2.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the interrupt level and the vector number for the periodic interrupt request. This register can be read or written at any time.
Freescale Semiconductor, Inc. PIV7–PIV0—Periodic Interrupt Vector Bits 7–0 These bits contain the value of the vector generated during an IACK cycle in response to an interrupt from the periodic timer. When the SIM40 responds to the IACK cycle, the periodic interrupt vector from the PICR is placed on the bus. This vector number is multiplied by four to form the vector offset, which is added to the vector base register to obtain the address of the vector. 4.3.2.7 PERIODIC INTERRUPT TIMER REGISTER (PITR).
Freescale Semiconductor, Inc. 4.3.2.8 SOFTWARE SERVICE REGISTER (SWSR). The SWSR is the location to which the software watchdog servicing sequence is written. The software watchdog can be enabled or disabled by the SWE bit in the SYPCR. SWSR can be written at any time, but returns all zeros when read. SWSR 7 $027 6 5 4 3 2 1 0 SWSR7 SWSR6 SWSR5 SWSR4 SWSR3 SWSR2 SWSR1 SWSR0 RESET: 0 0 0 0 0 0 0 0 Supervisor Only Freescale Semiconductor, Inc... 4.3.
Freescale Semiconductor, Inc. SLIMP—Limp Mode 1 = A loss of input signal reference has been detected, and the VCO is running at approximately one-half the maximum speed (affected by the X-bit ), determined from an internal voltage reference. 0 = External input signal frequency is at VCO reference. Freescale Semiconductor, Inc... SLOCK—Synthesizer Lock 1 = VCO has locked onto the desired frequency (or system clock is driven externally). 0 = VCO is enabled, but has not yet locked.
Freescale Semiconductor, Inc. 4.3.4.1 BASE ADDRESS REGISTERS. There are four 32-bit base address registers in the chip select function, one for each chip select signal. Base Address 1 $044, $04C, $054, $05C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 RESET: U U U U U U U U U U U U U U U U Supervisor Only Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NCS—No CPU Space This bit specifies whether or not a chip select will assert on a CPU space access cycle (FC3–FC0 = $7 or $F). If both supervisor data and program accesses are desired, while ignoring CPU space accesses, then this bit should be set. The NCS bit is cleared at reset. 1 = Suppress the chip select on a CPU space access. 0 = Assert the chip select on a CPU space access.
Freescale Semiconductor, Inc. FCM3–FCM0—Function Code Mask Bits 3–0 This field can be used to mask certain function code bits, allowing more than one address space type to be assigned to a chip select. Any set bit masks the corresponding function code bit. DD1, DD0—DSACK Delay Bits 1 and 0 This field determines the number of wait states added before an internal DSACK≈ is returned for that entry. Table 4-10 lists the encoding for the DD bits. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 4.3.4.3 CHIP SELECT REGISTERS PROGRAMMING EXAMPLE. The following listing is an example of programming a chip select at starting address $00040000, for a block size of 256 Kbytes, accessing supervisor and user data spaces with a 16-bit port requiring two wait states. There will be no write protection, no fast termination, and no CPU space accesses. base address 1 = $0004 base address 2 = $0013 address mask 1 = $0003 address mask 2 = $FF49 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 4.3.5.2 PORT A PIN ASSIGNMENT REGISTER 2 (PPARA2). PPARA2 selects between an address and IACK≈ function for the port A pins. Any set bit defines the corresponding pin to be an IACK ≈ output pin. Any cleared bit defines the corresponding pin to be an address bit as defined in the register diagram. Any set bits in PPARA1 override the configuration set in PPARA2. Bit 0 has no function in this register because there is no level 0 interrupt.
Freescale Semiconductor, Inc. 4.3.5.5 PORT B PIN ASSIGNMENT REGISTER (PPARB). PPARB controls the function of each port B pin. Any set bit defines the corresponding pin to be an IRQ≈ input or CS≈ as defined in Table 4-5. Any cleared bit defines the corresponding pin to be a discrete I/O pin (or CS ≈ if the FIRQ bit of the MCR is zero) controlled by the port B data and data direction registers. The MODCK signal has no function after reset.
Freescale Semiconductor, Inc. 4.4 MC68340 INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the MC68340 after power-up. Freescale Semiconductor, Inc... 4.4.1 Startup RESET is asserted by the MC68340 during the time in which V CC is ramping up, the VCO is locking onto the frequency, and the MC68340 is going through the reset operation.
Freescale Semiconductor, Inc. System Protection Control Register (SYPCR) (Note that this register can only be written once after reset.) • Enable the software watchdog, if desired (SWE bit). • If the watchdog is enabled, select whether a system reset or a level 7 interrupt is desired at timeout (SWRI bit). • If the watchdog is enabled, select the timeout period (SWTx bits). • Enable the double bus fault monitor, if desired (DBFE bit). • Enable the external bus monitor, if desired (BME bit).
Freescale Semiconductor, Inc. 4.4.3 SIM40 Example Configuration Code Freescale Semiconductor, Inc... The following code is an example configuration sequence for the SIM40 module. *************************************************************************** * MC68340 basic SIM40 register initialization example code: * This code is used to initialize the MC68340's internal SIM40 registers, * providing basic functions for operation. * It includes chip select programming for external devices.
Freescale Semiconductor, Inc. *************************************************************************** * Initialization code *************************************************************************** * Start Chip Select Initialization: INIT340 MOVE.W #$2700,SR Init SR - interrupts masked Freescale Semiconductor, Inc... *************************************************************************** * Set up default module base address value MOVEQ.L #7,D0 MBAR is in CPU space MOVEC.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... *************************************************************************** * Data table for chip select initialization *************************************************************************** * CS0 - EPROM - 00060000-0007ffff, 3-wait states, 16-bit term., write protect CSAM0$ DC.L $0001FFFD CSBAR0$ DC.L $00060009 * CS1 - RAM - 00000000-0000ffff, fast termination CSAM1$ DC.L $0000FFF0 CSBAR1$ DC.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 5 CPU32 The CPU32, the first-generation instruction processing module of the M68300 family, is based on the industry-standard MC68000 core processor. It has many features of the MC68010 and MC68020 as well as unique features suited for high-performance processor applications. The CPU32 provides a significant performance increase over the MC68000 CPU, yet maintains source-code and binary-code compatibility with the M68000 family. 5.
Freescale Semiconductor, Inc. 5.1.1 Features Features of the CPU32 are as follows: • Fully Upward Object-Code Compatible with M68000 Family • Virtual Memory Implementation • Loop Mode of Instruction Execution • Fast Multiply, Divide, and Shift Instructions • Fast Bus Interface with Dynamic Bus Port Sizing • Improved Exception Handling for Embedded Control Applications Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. CPU32 uses instruction restart, which requires that only a small portion of the internal machine state be saved. After correcting the page fault, the machine state is restored, and the instruction is refetched and restarted. This process is completely transparent to the application program. SEQUENCER Freescale Semiconductor, Inc... CONTROL UNIT DATA BUS ADDRESS BUS INSTRUCTION PREFETCH AND DECODE 16 BUS CONTROL EXECUTION UNIT BUS CONTROL 32 Figure 5-1.
Freescale Semiconductor, Inc. condition and count are checked after each execution of the data operations of the looped instruction. The CPU32 automatically exits the loop mode on interrupts or other exceptions. Freescale Semiconductor, Inc... 5.1.4 Vector Base Register The vector base register (VBR) contains the base address of the 1024-byte exception vector table, which consists of 256 exception vectors.
Freescale Semiconductor, Inc. 5.1.6 Addressing Modes Addressing in the CPU32 is register oriented. Most instructions allow the results of the specified operation to be placed either in a register or directly in memory; this flexibility eliminates the need for extra instructions to store register contents in memory. The seven basic addressing modes are as follows: • Register Direct • Register Indirect • Register Indirect with Index • Program Counter Indirect with Displacement Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 5-1. Instruction Set Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.1.7.1 TABLE LOOKUP AND INTERPOLATE INSTRUCTIONS. To maximize throughput for real-time applications, reference data is often “particulated” and stored in memory for quick access. The storage of each data point would require an inordinate amount of memory. The table instruction requires only a sample of data points stored in the array, thus reducing memory requirements. Intermediate values are recovered with this instruction via linear interpolation.
Freescale Semiconductor, Inc. 5.2 ARCHITECTURE SUMMARY The CPU32 is upward source- and object-code compatible with the MC68000 and MC68010. It is downward source- and object-code compatible with the MC68020. Within the M68000 family, architectural differences are limited to the supervisory operating state. User state programs can be executed unchanged on upward-compatible devices.
Freescale Semiconductor, Inc. 31 16 15 8 7 0 D0 D1 D2 D3 DATA REGISTERS D4 D5 D6 D7 31 16 15 Freescale Semiconductor, Inc... A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 31 16 15 0 A7 (USP) 31 USER STACK POINTER 0 15 8 7 PC PROGRAM COUNTER CCR CONDITION CODE REGISTER 0 0 Figure 5-3.
Freescale Semiconductor, Inc. 5.2.2 Registers Registers D7–D0 are used as data registers for bit, byte (8-bit), word (16-bit), long-word (32-bit), and quad-word (64-bit) operations. Registers A6 to A0 and the USP and SSP are address registers that may be used as software SPs or base address registers. Register A7 (shown as A7 and A7' in Figures 5-3 and 5-4) is a register designation that applies to the USP in the user privilege level and to the SSP in the supervisor privilege level.
Freescale Semiconductor, Inc. 5.3 INSTRUCTION SET The following paragaphs describe the set of instructions provided in the CPU32 and demonstrate their use. Descriptions of the instruction format and the operands used by instructions are included. After a summary of the instructions by category, a detailed description of each instruction is listed in alphabetical order. Complete programming information is provided, as well as a description of condition code computation and an instruction format summary.
Freescale Semiconductor, Inc. 5.3.1.1.2 Table Lookup and Interpolation (TBL). To maximize throughput for real-time applications, reference data is often precalculated and stored in memory for quick access. The storage of sufficient data points can require an inordinate amount of memory. The TBL instruction uses linear interpolation to recover intermediate values from a sample of data points, and thus conserves memory. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instructions specify an operand location in one of three ways: • Register Specification A register field of the instruction contains the number of the register. • Effective Address An effective address field of the instruction contains address mode information.
Freescale Semiconductor, Inc. (...) Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.3.3 Instruction Summary The instructions form a set of tools to perform the following operations: Data movement Bit manipulation Integer arithmetic Binary-coded decimal arithmetic Logic Program control Shift and rotate System control Freescale Semiconductor, Inc... The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development. All CPU32 instructions are summarized in Table 5-2.
Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary Opcode Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary (Continued) Freescale Semiconductor, Inc... Opcode Operation Syntax CMP2 Compare Rn < lower-bound or Rn > upper-bound and Set Condition Codes CMP2 〈ea〉,Rn DBcc If condition false then (Dn – 1 ⇒ Dn; If Dn ≠ –1 then PC + d ⇒ PC) DBcc Dn,〈 label〉 DIVS DIVSL Destination/Source ⇒ Destination DIVS.W 〈ea〉,Dn DIVS.L 〈 ea〉,Dq DIVS.L 〈 ea〉,Dr:Dq DIVSL.
Freescale Semiconductor, Inc. Table 5-2.
Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary (Concluded) Opcode Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.3.3.1 CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that indicate the result of a processor operation. Table 5-3 lists the effect of each instruction on these bits. The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them. Refer to Table 5-7 as an example. Table 5-3. Condition Code Computations Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 5-3. Condition Code Computations (Continued) X N Z V C ROR Operations — ∗ ∗ 0 ? ROR (r = 0) — ∗ ∗ 0 0 Special Definition C = Dr – 1 Freescale Semiconductor, Inc... NOTE : The following notations apply to this table only.
Freescale Semiconductor, Inc. 5.3.3.3 INTEGER ARITHMETIC OPERATIONS. The arithmetic operations include the four basic operations of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as arithmetic compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction set includes ADD, CMP, and SUB instructions for both address and data operations with all operand sizes valid for data operations. Address operands consist of 16 or 32 bits.
Freescale Semiconductor, Inc. Table 5-5.
Freescale Semiconductor, Inc. 5.3.3.4 LOGIC INSTRUCTIONS. The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes of immediate data. The test (TST) instruction arithmetically compares the operand with zero, placing the result in the CCR. Table 5-6 summarizes the logical operations. Table 5-6.
Freescale Semiconductor, Inc. Table 5-7. Shift and Rotate Operations Instruction ASL ASR LSL Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.3.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five instructions support operations on BCD numbers. The arithmetic operations on packed BCD numbers are add decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with extend (NBCD). Table 5-9 is a summary of the BCD operations. Table 5-9.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... To specify conditions for change in program control, condition codes must be substituted for the letters "cc" in conditional program control opcodes. Condition test mnemonics are given below. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes.
Freescale Semiconductor, Inc. Table 5-11. System Control Operations Instruction Operand Syntax Operand Size Operation Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.3.3.10 CONDITION TESTS. Conditional program control instructions and the TRAPcc instruction execute on the basis of condition tests. A condition test is the evaluation of a logical expression related to the state of the CCR bits. If the result is 1, the condition is true. If the result is 0, the condition is false. For example, the T condition is always true, and the EQ condition is true only if the Z-bit condition code is true. Table 5-12 lists each condition test.
Freescale Semiconductor, Inc. Two additional examples show how TBLSN can reduce cumulative error when multiple table lookup and interpolation operations are used in a calculation. Example 4 demonstrates addition of the results of three table interpolations. Example 5 illustrates use of TBLSN in surface interpolation. 5.3.4.1 TABLE EXAMPLE 1: STANDARD USAGE. The table consists of 257 word entries. As shown in Figure 5-7, the function is linear within the range 32768 ≤ X ≤ 49152.
Freescale Semiconductor, Inc. The table instruction is executed with the following bit pattern in Dx: 31 16 NOT USED 15 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 Table Entry Offset ⇒ Dx [8:15] = $A3 = 163 Interpolation Fraction ⇒ Dx [0:7] = $80 = 128 Using this information, the table instruction calculates dependent variable Y: 5.3.4.2 TABLE EXAMPLE 2: COMPRESSED TABLE.
Freescale Semiconductor, Inc. Table 5-14. Compressed Table Entries Entry Number X Value Y Value 2 512 1311 3 786 1966 Since the table is reduced from 257 to 5 entries, independent variable X must be scaled appropriately. In this case the scaling factor is 64, and the scaling is done by a single instruction: LSR.W #6,Dx Thus, Dx now contains the following bit pattern: Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc... INDEPENDENT VARIABLE Freescale Semiconductor, Inc. Y 2048 1024 4096 3072 X INDEPENDENT VARIABLE Figure 5-9. Table Example 3 Table 5-15.
Freescale Semiconductor, Inc. The following value has been calculated for independent variable X: 31 16 NOT USED 15 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 1 Since X is an 8-bit value, the upper four bits are used as a table offset and the lower four bits are used as an interpolation fraction. The following results are obtained from the subroutine: Table Entry Offset ⇒ Dx [4:7] = $B = 11 Interpolation Fraction ⇒ Dx [0:3] = $D = 13 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. First, the results of each TBL are rounded with the TBLS round-to-nearest-even algorithm. The following values would be returned by TBLS: TBL # 1 TBL # 2 TBL # 3 0010 0000 . 0011 1111 . 0000 0001 . Summing, the following result is obtained: Freescale Semiconductor, Inc... 0010 0011 0000 0110 0000 . 1111 . 0001 . 0000 . Now, using the same TBL results, the sum is first calculated and then rounded according to the same algorithm: 0010 0011 0000 0110 0000 . 0111 1111 .
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 5.3.4.5 Table Example 5: Surface Interpolations. The various forms of table can be used to perform surface (3D) TBLs. However, since the calculation must be split into a series of 2D TBLs, the possibility of losing precision in the intermediate results is possible. The following code sequence, incorporating both TBLS and TBLSN, eliminates this possibility. L0: MOVE.W TBLSN.B TBLSN.B TBLS.W ASR.L BCC.B ADDQ.B L1: . . .
Freescale Semiconductor, Inc. 5.4.1 State Transitions The processor is in normal, background, or exception state unless halted. When the processor fetches instructions and operands or executes instructions, it is in the normal processing state. The stopped condition, which the processor enters when a STOP or LPSTOP instruction is executed, is a variation of the normal state in which no further bus cycles are generated. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. All exception processing is performed at the supervisor level. All bus cycles generated during exception processing are supervisor references, and all stack accesses use the SSP. Freescale Semiconductor, Inc... Instructions that have important system effects can only be executed at supervisor level. For instance, user programs are not permitted to execute STOP, LPSTOP, or RESET instructions.
Freescale Semiconductor, Inc. 5.5.1 Exception Vectors An exception vector is the address of a routine that handles an exception. The VBR contains the base address of a 1024-byte exception vector table, which consists of 256 exception vectors. Sixty-four vectors are defined by the processor, and 192 vectors are reserved for user definition as interrupt vectors. Except for the reset vector which is two long words, each vector in the table is one long word.
Freescale Semiconductor, Inc. CAUTION Because there is no protection on the 64 processor-defined vectors, external devices can access vectors reserved for internal purposes. This practice is strongly discouraged. Freescale Semiconductor, Inc... All exception vectors, except the reset vector, are located in supervisor data space. The reset vector is located in supervisor program space. Only the initial reset vector is fixed in the processor memory map.
Freescale Semiconductor, Inc. Finally, the processor prepares to resume normal execution of instructions. The exception vector offset is determined by multiplying the vector number by 4, and the offset is added to the contents of the VBR to determine displacement into the exception vector table. The exception vector is loaded into the PC. If no other exception is pending, the processor will resume normal execution at the new address in the PC.
Freescale Semiconductor, Inc. When the CPU32 completes exception processing, it is ready to begin either exception processing for a pending exception or execution of a handler routine. Priority assignment governs the order in which exception processing occurs, not the order in which exception handlers are executed. Table 5-17. Exception Priority Groups Group/ Priority 0 Characteristics Reset Aborts all processing (instruction or exception); does not save old context.
Freescale Semiconductor, Inc. 5.5.2 Processing of Specific Exceptions Freescale Semiconductor, Inc... The following paragraphs provide details concerning sources of specific exceptions, how each arises, and how each is processed. 5.5.2.1 RESET. Assertion of RESET by external hardware or assertion of the internal RESET signal by an internal module causes a reset exception. The reset exception has the highest priority of any exception.
Freescale Semiconductor, Inc. ENTRY Freescale Semiconductor, Inc... 1 0 $7 $0 ➧S ➧ T0,T1 ➧ I2:I0 ➧ VBR .✎ FETCH VECTOR # 0 OTHERWISE SP ➧ (VECTOR # 0) BUS ERROR FETCH VECTOR # 1 OTHERWISE PC BUS ERROR ➧ (VECTOR # 1) PREFETCH 3 WORDS OTHERWISE BEGIN INSTRUCTION EXECUTION BUS ERROR/ ADDRESS ERROR (DOUBLE BUS FAULT) ASSERT HALT EXIT EXIT Figure 5-11. Reset Operation Flowchart 5-44 MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 5.5.2.2 BUS ERROR. A bus error exception occurs when an assertion of the BERR signal is acknowledged. The BERR signal can be asserted by one of three sources: 1. External logic by assertion of the BERR input pin 2. Direct assertion of the internal BERR signal by an internal module 3. Direct assertion of the internal BERR signal by the on-chip hardware watchdog after detecting a no-response condition Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. case of a released operand write. Released write exceptions are delayed until the next instruction boundary or attempted operand access. An address exception on a branch to an odd address is delayed until the PC is changed. No exception occurs if the branch is not taken. In this case, the fault address and return PC value placed in the exception stack frame are the odd address, and the current instruction PC points to the instruction that caused the exception.
Freescale Semiconductor, Inc. 5.5.2.6 HARDWARE BREAKPOINTS. The CPU32 recognizes hardware breakpoint requests. Hardware breakpoint requests do not force immediate exception processing, but are left pending. An instruction breakpoint is not made pending until the instruction corresponding to the request is executed. A pending breakpoint can be acknowledged between instructions or at the end of exception processing.
Freescale Semiconductor, Inc. All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal on all M68000 family members. Those customers requiring the use of an unimplemented opcode for synthesis of "custom instructions," operating system calls, etc., should use this opcode. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.5.2.10 TRACING. To aid in program development, M68000 processors include a facility to allow tracing of instruction execution. CPU32 tracing also has the ability to trap on changes in program flow. In trace mode, a trace exception is generated after each instruction executes, allowing a debugging program to monitor the execution of a program under test. The T1 and T0 bits in the supervisor portion of the SR are used to control tracing.
Freescale Semiconductor, Inc. If an instruction is executed and an interrupt is pending on completion, the trace exception is processed before the interrupt exception. If an instruction forces an exception, the forced exception is processed before the trace exception. Freescale Semiconductor, Inc... If an instruction is executed and a breakpoint is pending upon completion of the instruction, the trace exception is processed before the breakpoint.
Freescale Semiconductor, Inc. tracing. Priority level is then set to the level of the interrupt, and the processor fetches a vector number from the interrupting device (CPU space $F). The fetch bus cycle is classified as an interrupt acknowledge, and the encoded level number of the interrupt is placed on the address bus. If an interrupting device requests automatic vectoring, the processor generates a vector number (25 to 31) determined by the interrupt level number. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. attempting to read the stack frame. The version number is located in the most significant byte (bits 15–8) of the internal register word at location SP + $14 in the stack frame. The validity check ensures that stack frame data will be properly interpreted in multiprocessor systems. Freescale Semiconductor, Inc... If a frame is invalid, a format error exception is taken. If it is inaccessible, a bus error exception is taken.
Freescale Semiconductor, Inc. The TP field defines the class of the faulted bus operation. Two bus error exception frame types are defined. One is for faults on prefetch and operand accesses, and the other is for faults during exception frame stacking: 0 = Operand or prefetch bus fault 1 = Exception processing bus fault Freescale Semiconductor, Inc... MV is set when the operand transfer portion of the MOVEM instruction is in progress at the time of a bus fault.
Freescale Semiconductor, Inc. Read and write bus cycles are distinguished by the RW bit. Read bus cycles will set this bit, and write bus cycles will clear it. RW is reloaded into the bus controller if the RR bit is set during unstacking. 0 = Faulted cycle was an operand write 1 = Faulted cycle was a prefetch or operand read Freescale Semiconductor, Inc... The LG bit indicates an original operand size of long word.
Freescale Semiconductor, Inc. The SSW for a released write fault contains the following bit pattern: 15 14 13 12 11 10 9 8 7 6 5 0 0 0 TR B1 B0 1 0 0 0 LG 4 3 2 SIZ 0 FUNC Freescale Semiconductor, Inc... TR, B1, and B0 are set if the corresponding exception is pending when the bus error exception is taken. Status regarding the faulted bus cycle is reflected in the LG, SIZ, and FUNC fields.
Freescale Semiconductor, Inc. 5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer. Bus faults that occur as a result of MOVEM operand transfer are classified as type III faults. MOVEM instruction prefetch faults are type II faults. Type III faults cause an immediate exception that aborts the current instruction. None of the registers altered during execution of the faulted instruction are restored prior to execution of the fault handler.
Freescale Semiconductor, Inc. exception is also stacked. This data is placed on the stack in the format shown in Figure 5-13. The return address from the initial exception is stacked for RTE . 5.5.3.2 CORRECTING A FAULT. There are two ways to complete a faulted released write bus cycle. The first is to use a software handler. The second is to rerun the bus cycle via RTE. Type II fault handlers must terminate with RTE, but specific requirements must also be met before an instruction is restarted.
Freescale Semiconductor, Inc. 5.5.3.2.3 Type II—Correcting Faults via RTE. Instructions aborted because of a type II fault are restarted upon return from the exception handler. A fault handler must establish safe restart conditions. If a fault is caused by a nonresident page in a demand-paged virtual memory configuration, the fault address must be read from the stack, and the appropriate page retrieved. An RTE instruction terminates the exception handler.
Freescale Semiconductor, Inc. exceptions, will be restarted upon return from the exception handler. When a fault occurs after an operand has transferred, that transfer is not "undone". However, these memory locations are accessed a second time when the instruction is restarted. If a register used in an EA calculation is overwritten before a fault occurs, an incorrect EA is calculated upon instruction restart. 5.5.3.2.6 Type III—Correcting Faults via RTE.
Freescale Semiconductor, Inc. 5.5.4 CPU32 Stack Frames The CPU32 generates three different stack frames: four-word frames, six-word frames, and twelve-word bus error frames. 5.5.4.1 FOUR-WORD STACK FRAME. This stack frame is created by interrupt, format error, TRAP #n, illegal instruction, A-line and F-line emulator trap, and privilege violation exceptions.
Freescale Semiconductor, Inc. Bus operation in progress at the time of a fault is conveyed by the SSW. 15 14 13 12 11 10 9 8 7 6 5 4 TP MV 0 TR B1 B0 RR RM IN RW LG 3 SIZ 2 1 0 FUNC The bus error stack frame is 12 words in length. There are three variations of the frame, each distinguished by different values in the SSW TP and MV fields. An internal transfer count register appears at location SP + $14 in all bus error stack frames.
Freescale Semiconductor, Inc. 15 0 SP ⇒ STATUS REGISTER +$02 RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW +$06 1 1 0 0 +$08 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C DBUF HIGH Freescale Semiconductor, Inc... DBUF LOW +$10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW +$14 +$16 INTERNAL TRANSFER COUNT REGISTER 0 0 SPECIAL STATUS WORD Figure 5-15.
Freescale Semiconductor, Inc. 15 0 SP ⇒ STATUS REGISTER +$02 NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW +$06 1 1 0 0 VECTOR OFFSET +$08 FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C PRE-EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMAT/VECTOR WORD +$10 FAULTED INSTRUCTION PROGRAM COUNTER HIGH (SIX WORD FRAME ONLY) FAULTED INSTRUCTION PROGRAM COUNTER LOW (SIX WORD FRAME ONLY) Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.6.1.1 BACKGROUND DEBUG MODE (BDM) OVERVIEW. Microprocessor systems generally provide a debugger, implemented in software, for system analysis at the lowest level. The BDM on the CPU32 is unique because the debugger is implemented in CPU microcode. BDM incorporates a full set of debug options—registers can be viewed and/or altered, memory can be read or written, and test features can be invoked. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. memory access. Off-chip address comparators will not detect breakpoints on internal accesses unless show cycles are enabled. Breakpoints on prefetched instructions, which are flushed from the pipeline before execution, are not acknowledged, but operand breakpoints are always acknowledged. Acknowledged breakpoints can initiate either exception processing or BDM. See 5.5.2.6 Hardware Breakpoints for more information. 5.6.2 Background Debug Mode Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. BDM operation is enabled when BKPT is asserted (low) at the rising edge of RESET. BDM remains enabled until the next system reset. A high BKPT on the trailing edge of RESET disables BDM. BKPT is relatched on each rising transition of RESET . BKPT is synchronized internally and must be held low for at least two clock cycles prior to negation of RESET. Freescale Semiconductor, Inc... BDM enable logic must be designed with special care.
Freescale Semiconductor, Inc. The CPU writes a unique value indicating the source of BDM transition into temporary register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP and determine the source (see Table 5-20) by issuing a read system register command (RSREG). ATEMP is used in most debugger commands for temporary storage—it is imperative that the RSREG command be the first command issued after transition into BDM. Freescale Semiconductor, Inc... Table 5-20.
Freescale Semiconductor, Inc. executing at completion of the bus cycle. PCC will contain $00000001 if BDM is entered via a double bus fault immediately out of reset. CPU32 ACTIVITY DEVELOPMENT SYSTEM ACTIVITY . ENTER (BDM) • ASSERT FREEZE SIGNAL • WAIT FOR COMMAND SEND INITIAL COMMAND • LOAD COMMAND REGISTER • ENABLE SHIFT CLOCK • SHIFT OUT 17 BITS • DISABLE SHIFT CLOCK Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. The serial interface uses a full-duplex synchronous protocol similar to the serial peripheral interface (SPI) protocol. The development system serves as the master of the serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from the CPU32 system clock, development system serial logic is unhindered by the operating frequency of the target processor.
Freescale Semiconductor, Inc. CPU DEVELOPMENT SYSTEM INSTRUCTION REGISTER BUS DATA 16 16 0 . RCV DATA LATCH SERIAL IN PARALLEL OUT COMMAND LATCH DSI PARALLEL IN SERIAL OUT Freescale Semiconductor, Inc... DSO SERIAL IN PARALLEL OUT PARALLEL IN SERIAL OUT 16 STATUS RESULT LATCH EXECUTION UNIT 16 STATUS SYNCHRONIZE MICROSEQUENCER CONTROL LOGIC DSCLK DATA CONTROL LOGIC SERIAL CLOCK Figure 5-22.
Freescale Semiconductor, Inc. CLKOUT FREEZE DSCLK DSI Freescale Semiconductor, Inc... SAMPLE WINDOW INTERNAL SYNCHRONIZED DSCLK INTERNAL SYNCHRONIZED DSI DSO . CLKOUT Figure 5-23. Serial Interface Timing Diagram A user can use the state change on DSO to signal hardware that the next serial transfer may begin. A timeout of sufficient length to trap error conditions that do not change the state of DSO should also be incorporated into the design.
Freescale Semiconductor, Inc. SHIFT_CLK FORCE_BGND BKPT_TAG BKPT . . .... .. . . . . .. . . . . FREEZE Freescale Semiconductor, Inc... Figure 5-24. BKPT Timing for Single Bus Cycle Figure 5-25 depicts the timing of the BKPT/FREEZE method. In both cases, the serial clock is left high after the final shift of each transfer. This technique eliminates the possibility of accidentally tagging the prefetch initiated at the conclusion of a BDM session.
Freescale Semiconductor, Inc. DSCLK, the gated serial clock, is normally high, but it pulses low for each bit to be transferred. At the end of the seventeenth clock period, it remains high until the start of the next transmission. Clock frequency is implementation dependent and may range from DC to the maximum specified frequency. Although performance considerations might dictate a hardware implementation, software solutions can be used provided serial bus timing is maintained. 5.6.2.8 COMMAND SET.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Register Field: In most commands, this field specifies the register number for operations performed on an address or data register. Extension Word(s) (as required): At this time, no command requires an extension word to specify fully the operation to be performed, but some commands require extension words for addresses or immediate data. Addresses require two extension words because only absolute long addressing is permitted.
Freescale Semiconductor, Inc. COMMANDS TRANSMITTED TO THE CPU32 COMMAND CODE TRANSMITTED DURING THIS CYCLE HIGH-ORDER 16 BITS OF MEMORY ADDRESS LOW-ORDER 16 BITS OF MEMORY ADDRESS NONSERIAL-RELATED ACTIVITY SEQUENCE TAKEN IF OPERATION HAS NOT COMPLETED Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 5-23. BDM Command Summary Freescale Semiconductor, Inc... Command Mnemonic Description Read A/D Register Read the selected address or data register and return the results via the serial interface. RAREG/RDREG Write A/D Register WAREG/WDREG The data operand is written to the specified address or data register. Read System Register RSREG The specified system control register is read. All registers that can be read in supervisor mode can be read in BDM.
Freescale Semiconductor, Inc. Result Data: The contents of the selected register are returned as a long-word value. The data is returned most significant word first. 5.6.2.8.5 Write A/D Register (WAREG/WDREG). The operand (long-word) data is written to the specified address or data register. All 32 bits of the register are altered by the write. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 1 0 0 0 0 0 1 0 0 0 A/D 2 0 REGISTER Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Result Data: Always returns 32 bits of data, regardless of the size of the register being read. If the register is less than 32 bits, the result is returned zero extended. Register Field: The system control register is specified by the register field (see Table 5-24). Table 5-24. Register Field for RSREG and WSREG Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Register Field: The system control register is specified by the register field (see Table 5-24). The FAR is a read-only register—any write to it is ignored. 5.6.2.8.8 Read Memory Location (READ). Read the sized data at the memory location specified by the long-word address. Only absolute addressing is supported. The SFC register determines the address space accessed. Valid data sizes include byte, word, or long word. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. space accessed. Only absolute addressing is supported. Valid data sizes include byte, word, and long word. Command Format: 15 14 13 12 11 10 9 8 7 6 0 0 0 1 1 0 0 0 OP SIZE 5 4 3 2 1 0 0 0 0 0 0 0 Command Sequence: Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. starting address of the block and to retrieve the first result. Subsequent operands are retrieved with the DUMP command. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent DUMP commands use this address, increment it by the current operand size, and store the updated address back in the temporary register. NOTE Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Operand Data: None Result Data: Requested data is returned as either a word or long word. Byte data is returned in the least significant byte of a word result. Word results return 16 bits of significant data; long-word results return 32 bits. Status of the read operation is returned as in the READ command: $0xxxx for success, $10001 for bus or address errors. 5.6.2.8.11 Fill Memory Block (FILL).
Freescale Semiconductor, Inc. Command Sequence: FILL (B/W) ??? WRITE MEMORY LOCATION LS DATA "NOT READY" MS DATA "NOT READY" XXX "ILLEGAL" XXX "NOT READY" NEXT CMD "CMD COMPLETE" NEXT CMD "NOT READY" Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Command Sequence: GO ??? NORMAL MODE XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None Freescale Semiconductor, Inc... Result Data: None 5.6.2.8.13 Call User Code (CALL). This instruction provides a convenient way to patch user code. The return PC is stacked at the location pointed to by the current SP. The stacked PC serves as a return address to be restored by the RTS command that terminates the patch routine.
Freescale Semiconductor, Inc. Command Sequence: CALL ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" STACK RETURN PC FREEZE NEGATED PREFETCH STARTED NORMAL MODE Freescale Semiconductor, Inc... XXX BERR/AERR NEXT CMD "NOT READY" Operand Data: The 32-bit operand data is the starting location of the patch routine, which is the initial PC upon exiting BDM. Result Data: None As an example, consider the following code segment.
Freescale Semiconductor, Inc. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Command Sequence: RESET ??? ASSERT RESET XXX "NOT READY" Freescale Semiconductor, Inc... NEXT CMD "CMD COMPLETE" XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None Result Data: The “command complete” response ($0FFFF) is loaded into the serial shifter after negation of RESET. 5.6.2.8.15 No Operation (NOP).
Freescale Semiconductor, Inc. 5.6.2.8.16 Future Commands. Unassigned command opcodes are reserved by Motorola for future expansion. All unused formats within any revision level will perform a NOP and return the ILLEGAL command response. 5.6.3 Deterministic Opcode Tracking Freescale Semiconductor, Inc... The CPU32 utilizes deterministic opcode tracking to trace program execution. Two signals, IPIPE and IFETCH, provide all information required to analyze instruction pipeline operation. 5.6.3.
Freescale Semiconductor, Inc. Assertion of IPIPE for a single clock cycle indicates the use of data from IRB. Regardless of the presence of valid data in IRA, the contents of IRB are invalidated when IPIPE is asserted. If IRA contains valid data, the data is copied into IRB (IRA ⇒ IRB), and the IRB stage is revalidated. Freescale Semiconductor, Inc... Assertion of IPIPE for two clock cycles indicates the start of a new instruction and subsequent replacement of data in IRC.
Freescale Semiconductor, Inc. 5.7 INSTRUCTION EXECUTION TIMING This section describes the instruction execution timing of the CPU32. External clock cycles are used to provide accurate execution and operation timing guidelines, but not exact timing for every possible circumstance. This approach is used because exact execution time for an instruction or operation depends on concurrence of independently scheduled resources, on memory speeds, and on other variables. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. The bus controller and microsequencer operate concurrently. The bus controller can perform a read or write or schedule a prefetch while the microsequencer controls EA calculation or sets condition codes. The microsequencer can also request a bus cycle that the bus controller cannot perform immediately. When this happens, the bus cycle is queued, and the bus controller runs the cycle when the current cycle is complete.
Freescale Semiconductor, Inc. priority, many instruction words would be flushed unused, and necessary operand cycles would be delayed. To maximize available bus bandwidth, the CPU32 will schedule a prefetch only when the next instruction is not a change-of-flow instruction and when there is room in the pipeline for the prefetch. Freescale Semiconductor, Inc... 5.7.1.3.2 Write Pending Buffer. The CPU32 incorporates a single-operand write pending buffer.
Freescale Semiconductor, Inc. The execution time attributed to instructions A, B, and C after considering the overlap is illustrated in Figure 5-32. The overlap time is attributed to the execution time of the completing instruction. The following equation shows the method for calculating the overlap time: Overlap = min (Tail N, HeadN+1 ) INSTRUCTION A INSTRUCTION B Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. analyzed. To derive the actual instruction execution times for an instruction sequence, the instruction times listed in the tables must be adjusted to account for overlap. The formula for this calculation is as follows: C1 − min (T1 , H2 ) + C 2 − min (T2 , H3 ) + C 3 − min (T3 , H4 ) + .. .. . where: CN is the number of cycles listed for instruction N TN is the tail time for instruction N Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Because of the stipulation that each instruction must prefetch to replace itself, the concept of negative tails has been introduced to account for these free clocks on the bus. On a two-clock bus, it is not necessary to adjust instruction timing to account for the potential extra prefetch. The cycle times of the microsequencer and bus are matched, and no additional benefit or penalty is obtained.
Freescale Semiconductor, Inc. 1 2 3 4 5 6 7 8 9 0 1 2 4 3 5 6 7 8 CLOCK 1 PREFETCH BUS CONTROLLER WRITE FOR 1 INSTRUCTION CONTROLLER MOVE A1,(AO)+ EXECUTION TIME READ FOR 2 EA FETCH ADDQ 2 PREFETCH WRITE FOR 2 ADDQ TO MOVE.W A1,(AO)+ 3 PREFETCH EA CALC CLR 3 PREFETCH WRITE FOR 3 CLR CLR.W $30(A1) ADDQ.W #1,(AO) Freescale Semiconductor, Inc... Figure 5-33. Example 1—Instruction Stream 5.7.2.2 TIMING EXAMPLE 2—BRANCH INSTRUCTIONS.
Freescale Semiconductor, Inc. 1 2 3 4 5 6 7 8 9 0 1 2 4 3 CLOCK BUS CONTROLLER 1 PREFETCH 2 PREFETCH INSTRUCTION CONTROLLER MOVEQ CMP EXECUTION TIME MOVEQ #7,D1 CMP D1,D0 OFFSET CALC 3 PREFETCH 4 PREFETCH NOT TAKEN MOVE TO (A0) BLE.B NOT TAKEN WRITE FOR 4 WRITE FOR 4 MOVE.L D1,(AO) Freescale Semiconductor, Inc... Figure 5-35. Example 2—Branch Not Taken 5.7.2.3 TIMING EXAMPLE 3—NEGATIVE TAILS.
Freescale Semiconductor, Inc. Example 3 illustrates three different aspects of instruction time calculation: 1. The branch instruction does not attempt to prefetch beyond the minimum number of words needed for itself. 2. The negative tail allows execution to begin sooner than a three-word pipeline would allow. 3. There is a one-clock delay due to late arrival of the displacement at the CPU.
Freescale Semiconductor, Inc. four. If there is no time in the head to perform a prefetch due to a previous trailing write, then additional time to perform the prefetches must be allotted in the middle of the instruction or after the tail. 8 (2 /1 /0) Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.7.3.1 FETCH EFFECTIVE ADDRESS. The fetch EA table indicates the number of clock periods needed for the processor to calculate and fetch the specified EA. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.7.3.2 CALCULATE EFFECTIVE ADDRESS. The calculate EA table indicates the number of clock periods needed for the processor to calculate a specified EA. The timing is equivalent to fetch EA except there is no read cycle. The tail and cycle time are reduced by the amount of time the read would occupy. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number.
Freescale Semiconductor, Inc. 5.7.3.3 MOVE INSTRUCTION. The MOVE instruction table indicates the number of clock periods needed for the processor to calculate the destination EA and to perform a MOVE or MOVEA instruction. For entries with CEA or FEA, refer to the appropriate table to calculate that portion of the instruction time. Destination EAs are divided by their formats (see 5.3.4.4 Effective Address Encoding Summary). The total number of clock cycles is outside the parentheses.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Instruction Head Tail Cycles EXG Rn, Rm 2 0 4(0/1/0) MOVEC Cr, Rn 10 0 14(0/2/0) MOVEC Rn, Cr 12 0 14-16(0/1/0) MOVE CCR, Dn 2 0 4(0/1/0) MOVE CCR, 〈CEA 〉 0 2 4(0/1/1) MOVE Dn, CCR 2 0 4(0/1/0) MOVE 〈FEA〉, CCR 0 0 4(0/1/0) MOVE SR, Dn 2 0 4(0/1/0) MOVE SR, 〈CEA 〉 0 2 4(0/1/1) MOVE Dn, SR 4 −2 10(0/3/0) MOVE 〈FEA〉, SR 0 −2 10(0/3/0) MOVEM.
Freescale Semiconductor, Inc. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Instruction Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Instruction Head Tail Cycles TBLUN Dn:Dm, Dp 30 0 34-40(0/2/0) TBLUN (Save)* 〈CEA〉, Dn 1 1 3(0/1/0) TBLUN (Op) 〈CEA〉, Dn 6 0 39-45(2X/1/0) X = There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles. < = Maximum time (certain data or mode combinations may execute faster). Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.7.3.6 IMMEDIATE ARITHMETIC/LOGIC INSTRUCTIONS. The immediate arithmetic/logic instruction table indicates the number of clock periods needed for the processor to fetch the source immediate data value and to perform the specified arithmetic/logic instruction using the specified addressing mode. Footnotes indicate when to account for the appropriate fetch effective or fetch immediate EA times. The total number of clock cycles is outside the parentheses.
Freescale Semiconductor, Inc. 5.7.3.7 BINARY-CODED DECIMAL AND EXTENDED INSTRUCTIONS. The BCD and extended instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number.
Freescale Semiconductor, Inc. 5.7.3.8 SINGLE OPERAND INSTRUCTIONS. The single operand instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.7.3.9 SHIFT/ROTATE INSTRUCTIONS. The shift/rotate instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. Footnotes indicate when to account for the appropriate EA times. The number of bits shifted does not affect the execution time, unless noted. The total number of clock cycles is outside the parentheses.
Freescale Semiconductor, Inc. 5.7.3.10 BIT MANIPULATION INSTRUCTIONS. The bit manipulation instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.7.3.11 CONDITIONAL BRANCH INSTRUCTIONS. The conditional branch instruction table indicates the number of clock periods needed for the processor to perform the specified branch on the given branch size, with complete execution times given. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses.
Freescale Semiconductor, Inc. 5.7.3.12 CONTROL INSTRUCTIONS. The control instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Freescale Semiconductor, Inc. 5.7.3.13 EXCEPTION-RELATED INSTRUCTIONS AND OPERATIONS. The exceptionrelated instructions and operations table indicates the number of clock periods needed for the processor to perform the specified exception-related actions. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number.
Freescale Semiconductor, Inc. 5.7.3.14 SAVE AND RESTORE OPERATIONS. The save and restore operations table indicates the number of clock periods needed for the processor to perform the specified state save or return from exception. Complete execution times and stack length are given. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 6 DMA CONTROLLER MODULE The direct memory access (DMA) controller module provides for high-speed transfer capability to/from an external peripheral or for memory-to-memory data transfer. The DMA module, shown in Figure 6-1, provides two channels that allow byte, word, or long-word operand transfers. These transfers can be either single or dual address and to either onor off-chip devices.
Freescale Semiconductor, Inc. 6.1 DMA MODULE OVERVIEW The main purpose of the DMA controller module is to transfer data at very high rates, usually much faster than the CPU32 under software control can handle. The term DMA is used to refer to the ability of a peripheral device to access memory in a system in the same manner as a microprocessor does. DMA operations can greatly increase overall system performance. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. DMA DMA PERIPHERAL PERIPHERAL MEMORY . Freescale Semiconductor, Inc... DMA PERIPHERAL MEMORY Figure 6-2. Single-Address Transfers MEMORY DMA MEMORY ... Figure 6-3. Dual-Address Transfer MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 6.2 DMA MODULE SIGNAL DEFINITIONS This section contains a brief description of the DMA module signals used to provide handshake control for either a source or destination external device. NOTE Freescale Semiconductor, Inc... The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals.
Freescale Semiconductor, Inc. 6.3.1.1 INTERNAL REQUEST, MAXIMUM RATE. Internal generation using 100% of the internal bus always has a transfer request pending for the channel until the transfer is complete. As soon as the channel is started, the DMA will arbitrate for the internal bus and begin to transfer data when it becomes bus master. If no exceptions occur, all operands in the data block will be transferred in one burst so that the DMA will use 100% of the available bus bandwidth.
Freescale Semiconductor, Inc. Therefore, if a peripheral generates it asynchronously, it must be at least two clock periods long. Freescale Semiconductor, Inc... The DMA channel responds to cycle steal requests the same as all other requests. However, if subsequent DREQ≈ pulses are generated before DACK≈ is asserted in response to each request, they are ignored.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... place in one bus cycle, where only the memory is explicitly addressed. The DMA bus cycle may be either a read or a write cycle. The DMA provides the address and control signals required for the operation. The requesting device either sends or receives data to or from the specified address. Only external requests can be used to start a transfer when the single-address mode is selected. An external device uses DREQ≈ to request a transfer.
Freescale Semiconductor, Inc. DMA READ CPU CYCLE S0 S2 S4 S0 S2 DMA READ S4 S0 S2 CPU CYCLE S4 S0 CLKOUT A31–A0 FC3–FC0 Freescale Semiconductor, Inc... SIZ1–SIZ0 AS DS R/W D15–D0 DSACKx DREQx DONEx (INPUT) ..... DACKx DONEx (OUTPUT) NOTE: 1. Timing to generate more than one DMA request. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 3.
MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 S0 S2 S4 CPU CYCLE S0 S2 S4 DMA READ S0 S2 S4 CPU CYCLE S0 S2 DMA READ Figure 6-6. Single-Address Read Timing (Cycle Steal) NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3.
Freescale Semiconductor, Inc. 6.4.1.2 SINGLE-ADDRESS WRITE. During the single-address destination (write) cycle, the DMA controls the transfer of data from a device to memory. The data is written to memory selected by the address specified in the destination address register (DAR), the destination function codes in the FCR, and the size in the CCR. The destination (write) DMA bus cycle has timing identical to a write bus cycle.
MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 S0 S2 S4 CPU CYCLE S0 S2 S4 DMA WRITE S0 S2 S4 CPU CYCLE S0 S2 Figure 6-8. Single-Address Write Timing (Cycle Steal) S4 DMA WRITE NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3.
Freescale Semiconductor, Inc. 6.4.2 Dual-Address Mode Freescale Semiconductor, Inc... The dual-address DMA bus cycle transfers data between a device or memory and the DMA internal holding register (DHR). In this mode, any operand transfer takes place in two DMA bus cycles, one where a device is addressed and one where memory is addressed. The data transferred during a dual-address operation is either read from the data bus into the DHR or written from the DHR to the data bus.
MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 CPU CYCLE Figure 6-9. Dual-Address Read Timing (External Burst–Source Requesting) NOTE: 1. Timing to generate more than one DMA transfer. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 3.
6-14 MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 CPU CYCLE S0 S2 S4 CPU CYCLE S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 S4 CPU CYCLE S0 S2 S4 DMA READ S0 Figure 6-10. Dual-Address Read Timing (Cycle Steal–Source Requesting) NOTE 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, the DREQx is asserted after DACKx is asserted and before DACKx is negated. 3.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... the FCR, and the size in the CCR. When the complete operand is written, the DAR is incremented by 0, 1, 2, or 4, according to the increment and size information specified by the DAPI and DSIZE bits of the CCR, and the byte transfer count register (BTC) is decremented by the number of bytes transferred. If the BTC is equal to zero and there were no errors, the CSR DONE bit is set, and the DONE≈ signal for the DMA handshake is asserted.
6-16 MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 CPU CYCLE Figure 6-11. Dual-Address Write Timing (External Burst–Destination Requesting) NOTE: 1. Timing to generate more than one DMA transfer. 2. DACKx and DONEx (DMA control signals) are asserted in the destination (write) DMA cycle. 3.
MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 S0 S2 S4 CPU CYCLE S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 S4 CPU CYCLE S0 S2 S4 DMA READ S0 Figure 6-12. Dual-Address Write Timing (Cycle Steal–Destination Requesting) S2 S4 DMA WRITE NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3.
Freescale Semiconductor, Inc. 6.5 BUS ARBITRATION The DMA controller module uses the M68000 bus arbitration protocol to request bus mastership for DMA transfers. Each channel arbitrates for the bus independently. The source (read) DMA bus cycle has timing identical to a read bus cycle. The destination (write) DMA bus cycle has timing identical to a write bus cycle.
Freescale Semiconductor, Inc. address. In the single-address mode with the source (read) device requesting mode of operation, this register is not used. Freescale Semiconductor, Inc... The manner in which the SAR and DAR change after each cycle depends upon the values in the CCR SSIZE and DSIZE fields and SAPI and DAPI bits, and the starting address in the SAR and DAR. If programmed to increment, the increment value is 1, 2, or 4 for byte, word, or long-word operands, respectively.
Freescale Semiconductor, Inc. Each operand transfer in dual-address mode requires from two to five bus cycles in response to each operand transfer request. If the source and destination operands are the same size, two cycles will transfer the complete operand. If the source and destination operands are different sizes, the number of cycles will vary. If the source is a long-word and the destination is a byte, there would be one bus cycle for the read and four bus cycles for the write.
Freescale Semiconductor, Inc. CPU CYCLE S0 S2 DMA READ S4 S0 S4 CPU CYCLE S0 S2 S4 DMA READ .. .. .. ...... .. .. . S0 S2 CLKOUT A31–A0 FC3–FC0 SIZ1–SIZ0 AS Freescale Semiconductor, Inc... DS R/W D15–D0 DSACKx DREQx DACKx DONEx (OUTPUT) NOTE: 1. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. Figure 6-13.
Freescale Semiconductor, Inc. CPU CYCLE S0 S2 S4 DMA READ S0 S4 DMA WRITE S0 S4 DMA READ CPU CYCLE S0 S2 ... . S4 S0 S4 DMA WRITE S0 S4 S0 CLKOUT A31–A0 FC3–FC0 SIZ1–SIZ0 AS Freescale Semiconductor, Inc... DS R/W D15–D0 DSACKx DREQx DACKx DONEx (OUTPUT) NOTE 1. To cause another DMA transfer, the DREQx is asserted after DACKx is asserted and before DACKx is negated. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. Figure 6-14.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. MCR1, MCR2 $780, $7A0 15 14 13 12 11 STP FRZ1 FRZ0 SE 0 RESET: 0 0 0 0 0 10 9 8 ISM 0 7 6 SUPV 0 0 1 5 4 3 2 MAID 0 0 1 0 0 0 IARB 0 0 0 Freescale Semiconductor, Inc... Supervisor Only STP—Stop Bit 1 = Setting the STP bit stops all clocks within the DMA module except for the clock from the IMB. The clock from the IMB remains active to allow the CPU32 access to the MCR.
Freescale Semiconductor, Inc. SE—Single-Address Enable This bit is implemented for future MC683xx family compatibility. 1 = In single-address mode, the external data bus is driven during a DMA transfer. 0 = In single-address mode, the external data bus remains in a high-impedance state during a DMA transfer (used for intermodule DMA). In dual-address mode, the SE bit has no effect. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. The reset value of the IARB field is $0, which prevents the DMA module from arbitrating during the interrupt acknowledge cycle. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). NOTE The DMA module uses only one set of IARB bits for both channels. A read or write to either MCR accesses the same IARB control bits. Freescale Semiconductor, Inc... 6.7.
Freescale Semiconductor, Inc. CCR1, CCR2 $788, $7A8 15 14 13 12 11 10 INTB INTN INTE ECO SAPI DAPI RESET: U U U U U U 9 8 7 SSIZE U 6 5 DSIZE U U 4 REQ U U 2 BB U U = Unaffected by reset Freescale Semiconductor, Inc... 3 U U 1 0 S/D STR U 0 Supervisor/User INTB—Interrupt Breakpoint Setting the interrupt breakpoint bit sets the BRKP bit in the CSR. The logic AND of INTB and BRKP generates an interrupt request.
Freescale Semiconductor, Inc. Dual-Address Mode—This bit defines which device generates requests. Freescale Semiconductor, Inc... 1 = If request generation is programmed to be external (REQ = 1x), the source device generates the request, and the control signals ( DREQ≈, DACK≈, and DONE≈) are part of the source (read) portion of the transfer.
Freescale Semiconductor, Inc. DSIZE—Destination Size Control Field This field controls the size of the destination (write) bus cycle that the DMA channel is running. Table 6-3 defines these bits. Freescale Semiconductor, Inc... Table 6-3. DSIZEx Encoding Bit 7 Bit 6 Definition 0 0 Long Word* 0 1 Byte 1 0 Word 1 1 Not Used *External logic is required to complete a longword transfer.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... S/D—Single-/Dual-Address Transfer 1 = The DMA channel runs single-address transfers from a peripheral to memory or from memory to a peripheral. The destination holding register is not used for these transfers because the data is transferred directly into the destination location. The MC68340 on-chip peripherals do not support single-address transfers. 0 = The DMA channel runs dual-address transfers.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... IRQ—Interrupt Request This bit is the logical OR of the DONE, BES, BED, CONF, and BRKP bits and is cleared when they are all cleared. IRQ is positioned to allow conditional testing as a signed binary integer. The state of this bit is not affected by the interrupt enable bits in the CCR. The STR bit in the CCR cannot be set when this bit is set; all error status bits, except the BRKP bit, must be cleared before the STR bit can be set.
Freescale Semiconductor, Inc. 6.7.5 Function Code Register (FCR) The FCR contains the source and destination function codes for the channel. This register is accessible in either supervisor or user space. The FCR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). FCR1, FCR2 7 6 $78B, $7AB 5 4 3 2 SFC RESET: U U 0 U U DFC U U U U = Unaffected by reset. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 6.7.6 Source Address Register (SAR) The SAR is a 32-bit register that contains the address of the source operand used by the DMA to access memory or peripheral registers. This register is accessible in either supervisor or user space. The SAR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. DAR1, DAR2 $790, $7B0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 RESET: U U U U U U U U U U U U U U U U 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RESET: U U U U U U U U U U U U U U U U Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... This register is decremented by 1, 2, or 4 for each successful operand transfer from source to destination locations. When the BTC decrements to zero and no error has occurred, the CSR DONE bit is set. In the external request mode, the DONE≈ handshake line is also asserted when the BTC is decremented to zero. If the operand size is byte, then the register is always decremented by 1.
Freescale Semiconductor, Inc. For normal transfers aligned with the size and address, only two bus cycles are required for each transfer: a read from the source and a write to the destination. 6.9 DMA CHANNEL INITIALIZATION SEQUENCE The following paragraphs describe DMA channel initialization and operation. If the DMA capability of the MC68340 is being used, the initialization steps should be performed during the part initialization sequence.
Freescale Semiconductor, Inc. • Select the direction of transfer if in single-address mode (ECO bit), or select which device generates requests if in dual-address mode. 6.9.1.1 DMA CHANNEL OPERATION IN SINGLE-ADDRESS MODE. The following steps are required to begin a DMA transfer in single-address mode. Channel Control Register (CCR) • Write a zero to the start bit (STR) to prevent the channel from starting the transfer prematurely. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. • If using internal request, select the amount of bus bandwidth to be used by the DMA (BB field). • Clear the S/D bit for dual-address transfer. Channel Status Register (CSR) • Clear the CSR by writing $7C into it. The DMA cannot be started until the DONE, BES, BED, CONF, and BRKP bits are cleared. Function Code Register (FCR) • Encode the source and destination function codes. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. * No interrupts are enabled, source (read) cycle. Increment source * address, source size is long word, REQ is external burst request. * Single-address mode, start the DMA transfers. MOVE.W #$1823,DMACCR1(A0) Freescale Semiconductor, Inc... *************************************************************************** END *************************************************************************** Example 2: Internal Request Generation, Memory to Memory Transfers.
Freescale Semiconductor, Inc. * Normal Operation, ignore FREEZE, dual-address mode. ISM field at 3. Make * sure CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel startup. * Supervisor/user reg. unrestricted, MAID field at 3. IARB priority at 4. MOVE.W #$0334,(A0) * Clear channel control reg. * Clear STR (start) bit to prevent the channel from starting a transfer early. CLR.W DMACCR1(A0) Freescale Semiconductor, Inc... * Initialize interrupt reg.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... * This code is used to initialize the 68340's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for internal request generation * to perform a memory block initialization for 100 bytes.
Freescale Semiconductor, Inc. MOVE.W #$0742,DMAINT1(A0) * Initialize channel status reg. * Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup. MOVE.B #$7C,DMACSR1(A0) * Initialize function code reg. * DMA space, supervisor data space for source and destination. MOVE.B #$DD,DMAFCR1(A0) Freescale Semiconductor, Inc... * Initialize source operand address * Source address is equal to $6000. MOVE.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. * Source address is equal to $6001, and odd address. MOVE.L SARADD,DMASAR1(A0) * Initialize destination operand address * Destination address is equal to $10000, and even address. MOVE.L DARADD,DMADAR1(A0) Freescale Semiconductor, Inc... * Initialize the byte transfer count register * The number of bytes to be transferred is $14 or 20 bytes MOVE.L NUMBYTE,DMABTC1(A0) * Channel control reg. init. and Start DMA transfers * No interrupts are enabled, source (read) cycle.
Freescale Semiconductor, Inc. SECTION 7 SERIAL MODULE Freescale Semiconductor, Inc... The MC68340 serial module is a dual universal asynchronous/synchronous receiver/transmitter that interfaces directly to the CPU32 processor via the intermodule bus (IMB).
Freescale Semiconductor, Inc. 7.1 MODULE OVERVIEW Features of the serial module are as follows: • Two, Independent, Full-Duplex Asynchronous/Synchronous Receiver/Transmitter Channels • Maximum Data Transfer Rate: —1× mode: 3 Mbps @ 8.39 MHz CLKOUT, 9.8 Mbps @25 MHz CLKOUT —16× mode: 188 kbps @ 8.39 MHz CLKOUT, 612 kbps @25 MHz CLKOUT • Quadruple-Buffered Receiver Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 7.1.1 Serial Communication Channels A and B Each communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter using an operating frequency independently selected from a baud rate generator or an external clock input. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. currently active interrupt conditions. The interrupt enable register (IER) is programmable to mask any events that can cause an interrupt. 7.1.5 Comparison of Serial Module to MC68681 The serial module is code compatible with the MC68681 with some modifications. The following paragraphs describe the differences. The programming model is slightly altered. The supervisor/user block in the MC68340 closely follows the MC68681.
Freescale Semiconductor, Inc. ADDRESS BUS IMB INTERFACE SIGNALS X1 CONTROL DATA DATA BUS MUX S E R I A L BAUD RATE GENERATOR LOGIC X2 SCLK CHANNEL A D7–D0 M O D U L E FOUR-CHARACTER RECEIVE BUFFER RxDA TWO-CHARACTER TRANSMIT BUFFER TxDA RTSA I N T E R N A L B U S CTSA TxRDYA EXTERNAL INTERFACE SIGNALS Freescale Semiconductor, Inc... DATA BUS D15–D0 INTERNAL CONTROL LOGIC RxRDYA ..... ..... . ..
Freescale Semiconductor, Inc. 7.2.3 External Input (SCLK) This input can be used as the clock input for channel A and/or channel B and is programmable in the clock-select registers (CSR). When used as the receiver clock, received data is sampled on the rising edge of the clock. When used as the transmitter clock, data is output on the falling edge of the clock. If this input is not used, it must be connected to VCC or GND. 7.2.4 Channel A Transmitter Serial Data Output (TxDA) Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. 7.2.9.1 RTSB . When used for this function, this signal can be programmed to be automatically negated and asserted by either the receiver or transmitter. When connected to the CTS≈ input of a transmitter, this signal can be used to control serial data flow. 7.2.9.2 OP1. When used for this function, this output is controlled by bit 1 in the OP. 7.2.10 Channel A Clear-To-Send (CTSA) This active-low input is the channel A clear-to-send. 7.2.
Freescale Semiconductor, Inc. 7.3 OPERATION The following paragraphs describe the operation of the baud rate generator, transmitter and receiver, and other functional operating modes of the serial module. 7.3.1 Baud Rate Generator Freescale Semiconductor, Inc... The baud rate generator consists of a crystal oscillator, baud rate generator, and clock selectors (see Figure 7-3). The crystal oscillator operates directly from a 3.6864-MHz crystal or from an external clock of the same frequency.
Freescale Semiconductor, Inc. CHANNEL A EXTERNAL INTERFACE COMMAND REGISTER (CRA) W MODE REGISTER A (MR1A) R/W MODE REGISTER B (MR2A) R/W STATUS REGISTER (SRA) Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 7.3.2.1 TRANSMITTER. The transmitters are enabled through their respective command registers (CR) located within the serial module. The serial module signals the CPU32 when it is ready to accept a character by setting the transmitter-ready bit (TxRDY) in the channel's status register (SR). Functional timing information for the transmitter is shown in Figure 7-5. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. transmit shift register, if any, is completely sent out. If the transmitter is reset through a software command, operation ceases immediately (refer to 7.4.1.7 Command Register (CR)). The transmitter is re-enabled through the CR to resume operation after a disable or software reset. Freescale Semiconductor, Inc... If clear-to-send operation is enabled, CTS≈ must be asserted for the character to be transmitted.
Freescale Semiconductor, Inc. RxD C2 C1 C3 C4 C5 C6 C8 C7 C6, C7, C8 ARE LOST RECEIVER ENABLED RxRDY (SR0) Freescale Semiconductor, Inc... FFULL (SR1) RxRDYA CS R R R R R R R R STATUS DATA STATUS DATA STATUS DATA STATUS DATA C1 C2 C3 C4 C5 LOST OVERRUN (SR4) 1 RTS RESET BY COMMAND OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1 2. Timing shown for OPCR(4) = 1 and MR1(6) = 0 3. R = Read 4. CN = Received Character Figure 7-6.
Freescale Semiconductor, Inc. assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO. Thus, data flowing from the receiver to the CPU32 is quadruple buffered. Freescale Semiconductor, Inc... In addition to the data byte, three status bits, PE, FE, and RB, are appended to each data character in the FIFO; OE is not appended. By programming the ERR bit in the channel's mode register (MR1), status is provided in character or block modes.
Freescale Semiconductor, Inc. 7.3.3 Looping Modes Each serial module channel can be configured to operate in various looping modes as shown in Figure 7-7. These modes are useful for local and remote system diagnostic functions. The modes are described in the following paragraphs with further information available in 7.4 Register Description and Programming. Freescale Semiconductor, Inc... The channel's transmitter and receiver should both be disabled when switching between modes.
Freescale Semiconductor, Inc. RxDx INPUT Rx CPU DISABLED Tx DISABLED TxDx OUTPUT (a) Automatic Echo Rx DISABLED RxDx INPUT DISABLED TxDx OUTPUT Freescale Semiconductor, Inc... CPU Tx (b) Local Loopback DISABLED Rx DISABLED RxDx INPUT DISABLED Tx DISABLED TxDx OUTPUT CPU (c) Remote Loopback Figure 7-7. Looping Modes Functional Diagram 7.3.4 Multidrop Mode A channel can be programmed to operate in a wakeup mode for multidrop or multiprocessor applications.
Freescale Semiconductor, Inc. RxD C2 C1 C3 C4 C5 C6 C8 C7 C6, C7, C8 ARE LOST RECEIVER ENABLED RxRDY (SR0) Freescale Semiconductor, Inc... FFULL (SR1) RxRDYA CS R R R R R R R R STATUS DATA STATUS DATA STATUS DATA STATUS DATA C1 C2 C3 C4 C5 LOST OVERRUN (SR4) 1 RTS RESET BY COMMAND OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1 2. Timing shown for OPCR(4) = 1 and MR1(6) = 0 3. R = Read 4. CN = Received Character Figure 7-8.
Freescale Semiconductor, Inc. RxRDY bit and loads the character into the receiver holding register FIFO stack provided the received A/D bit is a one (address tag). The character is discarded if the received A/D bit is a zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU32 via the receiver holding register stack during read operations. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. NOTE Freescale Semiconductor, Inc... All serial module registers are only accessible as bytes. The contents of the mode registers (MR1 and MR2), clock-select register (CSR), and the auxiliary control register (ACR) bit 7 should only be changed after the receiver/transmitter is issued a software RESET command—i.e., channel operation must be disabled.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... STP—Stop Mode Bit 1 = The serial module will be disabled. Setting the STP bit stops all clocks within the serial module (including the crystal or external clock and SCLK), except for the clock from the IMB. The clock from the IMB remains active to allow CPU32 access to the MCR. The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or a hardware reset.
Freescale Semiconductor, Inc. Bits 11–8, 6–4—Reserved Freescale Semiconductor, Inc... SUPV—Supervisor/User The value of this bit has no affect on registers permanently defined as supervisor only. 1 = The serial module registers, which are defined as supervisor or user, reside in supervisor data space and are only accessible from supervisor programs.
Freescale Semiconductor, Inc. IVR $705 7 6 5 4 3 2 1 0 IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 RESET: 0 0 0 0 1 1 1 1 Read /Write Supervisor Only Freescale Semiconductor, Inc... IVR7–IVR0—Interrupt Vector Bits Each module that generates interrupts has an interrupt vector field. This 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located.
Freescale Semiconductor, Inc. ERR—Error Mode This bit controls the meaning of the three FIFO status bits (RB, FE, and PE) in the SR for the channel. 1 = Block mode—The values in the channel SR are the accumulation (i.e., the logical OR) of the status for all characters coming to the top of the FIFO since the last reset error status command for the channel was issued. Refer to 7.4.1.7 Command Register (CR) for more information on serial module commands.
Freescale Semiconductor, Inc. Table 7-3. B/Cx Control Bits B/C1 B/C0 Bits/Character 0 0 Five Bits 0 1 Six Bits 1 0 Seven Bits 1 1 Eight Bits Freescale Semiconductor, Inc... 7.4.1.5 STATUS REGISTER (SR). The SR indicates the status of the characters in the FIFO and the status of the channel transmitter and receiver. This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared).
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... OE—Overrun Error 1 = One or more characters in the received data stream have been lost. This bit is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost.
Freescale Semiconductor, Inc. 7.4.1.6 CLOCK-SELECT REGISTER (CSR). The CSR selects the baud rate clock for the channel receiver and transmitter. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). NOTE This register should only be written after the external crystal is stable (XTAL_RDY bit of the ISR is zero). Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. TCS3–TCS0—Transmitter Clock Select These bits select the baud rate clock for the channel transmitter from a set of baud rates listed in Table 7-5. The baud rate set selected depends upon ACR bit 7. Set 1 is selected if ACR bit 7 = 0, and set 2 is selected if ACR bit 7 = 1. The transmitter clock is always 16 times the baud rate shown in this list, except when SCLK is used. Freescale Semiconductor, Inc... Table 7-5.
Freescale Semiconductor, Inc. MISC3–MISC0—Miscellaneous Commands These bits select a single command as listed in Table 7-6. Freescale Semiconductor, Inc... Table 7-6.
Freescale Semiconductor, Inc. Start Break—The start break command forces the channel's TxDx low. If the transmitter is empty, the start of the break conditions can be delayed up to one bit time. If the transmitter is active, the break begins when transmission of the character is complete. If a character is in the transmitter shift register, the start of the break is delayed until the character is transmitted. If the transmitter holding register has a character, that character is transmitted after the break.
Freescale Semiconductor, Inc. RC1–RC0—Receiver Commands These bits select a single command as listed in Table 7-8. Freescale Semiconductor, Inc... Table 7-8. RCx Control Bits RC1 RC0 Command 0 0 No Action Taken 0 1 Enable Receiver 1 0 Disable Receiver 1 1 Do Not Use No Action Taken—The no action taken command causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled.
Freescale Semiconductor, Inc. characters until the shift register is ready to accept more data. When the shift register is empty, it checks to see if the holding register has a valid character to be sent (TxRDY bit cleared). If there is a valid character, the shift register loads the character and reasserts the TxRDY bit in the channel's SR. Writes to the transmitter buffer when the channel's SR TxRDY bit is clear and when the transmitter is disabled have no effect on the transmitter buffer.
Freescale Semiconductor, Inc. 7.4.1.11 AUXILIARY CONTROL REGISTER (ACR). The ACR selects which baud rate is used and controls the handshake of the transmitter/receiver. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). ACR $714 7 6 5 4 3 2 1 0 BRG 0 0 0 0 0 IECB IECA RESET: 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... DBB—Delta Break B 1 = The channel B receiver has detected the beginning or end of a received break. 0 = The CPU32 has issued a channel B reset break-change interrupt command. Refer to 7.4.1.7 Command Register (CR) for more information on the reset break-change interrupt command. RxRDYB—Channel B Receiver Ready or FIFO Full The function of this bit is programmed by MR1B bit 6.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... RxRDYA—Channel A Receiver Ready or FIFO Full The function of this bit is programmed by MR1A bit 6. 1 = If programmed as receiver ready, a character has been received in channel A and is waiting in the receiver buffer FIFO. If programmed as FIFO full, a character has been transferred from the receiver shift register to the FIFO, and the transfer has caused the channel A FIFO to become full (all three positions are occupied).
Freescale Semiconductor, Inc. RxRDYB—Channel B Receiver Ready or FIFO full 1 = Enable interrupt 0 = Disable interrupt TxRDYB—Channel B Transmitter Ready 1 = Enable interrupt 0 = Disable interrupt Bit 3—Reserved Freescale Semiconductor, Inc... DBA—Delta Break A 1 = Enable interrupt 0 = Disable interrupt RxRDYA—Channel A Receiver Ready or FIFO full 1 = Enable interrupt 0 = Disable interrupt TxRDYA—Channel A Transmitter Ready 1 = Enable interrupt 0 = Disable interrupt 7.4.1.14 INPUT PORT (IP).
Freescale Semiconductor, Inc. 7.4.1.15 OUTPUT PORT CONTROL REGISTER (OPCR). The OPCR individually configures four bits of the 8-bit parallel OP for general-purpose use or as an auxiliary function serving the communication channels. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared).
Freescale Semiconductor, Inc. OP0—Output Port 0/ RTSA 1 = The OP0/RTSA pin functions as the ready-to-send signal for channel A. The signal is asserted and negated according to the configuration programmed by RxRTS bit 7 in the MR1A for the receiver and TxRTS bit 5 in the MR2A for the transmitter. 0 = The OP0/RTSA pin functions as a dedicated output. The signal reflects the complement of the value of bit 0 of the OP. Freescale Semiconductor, Inc... 7.4.1.16 OUTPUT PORT DATA REGISTER (OP).
Freescale Semiconductor, Inc. 7.4.1.17 MODE REGISTER 2 (MR2). MR2 controls some of the serial module configuration. This register can be read or written at any time the serial module is enabled (i.e., the STP bit in the MCR is cleared). MR2A, MR2B $720, $721 7 6 5 4 3 2 1 0 CM1 CM0 TxRTS TxCTS SB3 SB2 SB1 SB0 RESET: 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read/Write Supervisor/User CM1–CM0—Channel Mode These bits select a channel mode as listed in Table 7-9. See 7.3.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... TxCTS—Transmitter Clear-to-Send 1 = Enables clear-to-send operation. The transmitter checks the state of the CTS≈ input each time it is ready to send a character. If CTS≈ is asserted, the character is transmitted. If CTS≈ is negated, the channel TxDx remains in the high state, and the transmission is delayed until CTS≈ is asserted. Changes in CTS≈ while a character is being transmitted do not affect transmission of that character.
Freescale Semiconductor, Inc. 7.4.2 Programming The basic interface software flowchart required for operation of the serial module is shown in Figure 7-10. The routines are divided into three categories: • Serial Module Initialization • I/O Driver Freescale Semiconductor, Inc... • Interrupt Handling 7.4.2.1 SERIAL MODULE INITIALIZATION. The serial module initialization routines consist of SINIT and CHCHK. SINIT is called at system initialization time to check channel A and channel B operation.
Freescale Semiconductor, Inc. SERIAL MODULE ENABLA SINIT Freescale Semiconductor, Inc... INITIATE: CHANNEL A CHANNEL B INTERRUPTS ANY ERRORS IN CHANNEL A ? Y N CHK1 POINT TO CHANNEL A ENABLE CHANNEL A'S RECEIVER CALL CHCHK ASSERT CHANNEL A REQUEST TO SEND ENABLB SAVE CHANNEL A STATUS CHK2 POINT TO CHANNEL B ANY ERRORS IN CHANNEL B ? Y N CALL CHCHK ENABLE CHANNEL B'S TRANSMITTER SINITR SAVE CHANNEL B STATUS RETURN Figure 7-10.
Freescale Semiconductor, Inc. CHCHK CHCHK Freescale Semiconductor, Inc... PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE CHANNEL'S TRANSMITTER CLEAR CHANNEL STATUS WORD TxCHK N IS TRANSMITTER READY ? Y WAITED TOO LONG ? Y SET TRANSMITTERNEVER-READY FLAG N SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK N HAS RECEIVER RECEIVED CHARACTER ? N WAITED TOO LONG ? Y SET RECEIVERNEVER-READY FLAG Y A B Figure 7-10.
Freescale Semiconductor, Inc. A B FRCHK RSTCHN HAVE FRAMING ERROR ? N Y DISABLE CHANNEL'S TRANSMITTER RESTORE CHANNEL TO ORIGINAL MODE Freescale Semiconductor, Inc... SET FRAMING ERROR FLAG PRCHK RETURN HAVE PARITY ERROR ? N Y SET PARITY ERROR FLAG A CHRCHK GET CHARACTER FROM RECEIVER SAME AS CHARACTER TRANSMITTED ? Y N SET INCORRECT CHARACTER FLAG B Figure 7-10.
Freescale Semiconductor, Inc. SIRQ INCH ABRKI Freescale Semiconductor, Inc... WAS IRQx CAUSED BY BEGINNING OF A BREAK ? N DOES CHANNEL A RECEIVER HAVE A CHARACTER ? Y N Y CLEAR CHANGE-INBREAK STATUS BIT PLACE CHARACTER IN D0 ABRKI1 HAS END-OF-BREAK IRQx ARRIVED YET ? RETURN N Y CLEAR CHANGE-INBREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR RTE Figure 7-10.
Freescale Semiconductor, Inc. OUTCH POUCH Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 7.5 SERIAL MODULE INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the serial module. 7.5.1 Serial Module Configuration If the serial capability of the MC68340 is being used, the following steps are required to properly initialize the serial module. NOTE Freescale Semiconductor, Inc... The serial module registers can only be accessed by byte operations. Command Register (CR) • Reset the receiver and transmitter for each channel.
Freescale Semiconductor, Inc. The following steps are channel specific: Clock Select Register (CSR) • Select the receiver and transmitter clock. Mode Register 1 (MR1) • If desired, program operation of receiver ready-to-send (RxRTS bit). • Select receiver-ready or FIFO-full notification (R/F bit). • Select character or block error mode (ERR bit). • Select parity mode and type (PM and PT bits). Freescale Semiconductor, Inc... • Select number of bits per character (B/Cx bits).
Freescale Semiconductor, Inc. * Serial register offsets from serial base address MR1A EQU $10 Mode register 1 A MR2A EQU $20 Mode register 2 A SRA EQU $11 Status register A CSRA EQU $11 Clock select reg A CRA EQU $12 Command reg A Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. * MODE REGISTER 2 MOVE.B #$07,MR2A(A0) Normal, 1 stop bit Freescale Semiconductor, Inc... * SET UP BAUD RATE FOR PORT IN CLOCK SELECT REGISTER MOVE.B #$BB,CSRA(A0) Set 9600 baud for RX and TX * SET RTSA ACTIVE MOVE.B #$01,OP_BS(A0) set RTSA/OP0 output * ENABLE PORT MOVE.
Freescale Semiconductor, Inc. SECTION 8 TIMER MODULES Each MC68340 timer module contains a counter/timer (timer 1 and timer 2) as shown in Figure 8-1. Each timer interfaces directly to the CPU32 via the intermodule bus (IMB). Each timer consists of the following major areas: Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. — Pulse-Width Measurement — Period Measurement — Event Counting • Seven Maskable Interrupt Conditions Based on Programmable Events 8.1.1 Timer and Counter Functions Freescale Semiconductor, Inc... The term 'timer' is used to reference either timer 1 or timer 2, since the two are functionally equivalent. The timer can perform virtually any application traditionally assigned to timers and counters.
Freescale Semiconductor, Inc. TIMER EXTERNAL INTERFACE MODULE CONFIGURATION REGISTER INTERRUPT REGISTER CONTROL REGISTER STATUS REGISTER Freescale Semiconductor, Inc... PRELOAD 1 REGISTER I M B (SYSTEM CLOCK) CLOCK CLOCK LOGIC PRELOAD 2 REGISTER 16-BIT COUNTER MUX COUNTER CLOCK TIN TGATE SELECTED CLOCK MUX COUNTER REGISTER COMPARE REGISTER 8-BIT PRESCALER TIMEOUT TOUT 16-BIT COMPARATOR Figure 8-2. Timer Functional Diagram 8.1.1.4 CLOCK SELECTION LOGIC.
Freescale Semiconductor, Inc. 8.1.3 Interrupt Control Logic Each timer provides seven interrupt request outputs (IRQ7– IRQ1) to notify the CPU32 that an interrupt has occurred. The interrupts are described in 8.4 Register Description. Bits in the SR indicate all currently active interrupt conditions. The interrupt enable (IE) bits in the control register (CR) are programmable to mask any events that may cause an interrupt. 8.
Freescale Semiconductor, Inc. TIMER 1 TIN1 CLOCK LOGIC TGATE1 PRESCALER EXTERNAL INTERFACE SIGNALS COUNTER Freescale Semiconductor, Inc... OUTPUT CONTROL TOUT1 INTERRUPT CONTROL I M B TIMER 2 TIN2 CLOCK LOGIC TGATE2 PRESCALER EXTERNAL INTERFACE SIGNALS COUNTER OUTPUT CONTROL TOUT2 INTERRUPT CONTROL Figure 8-3. External and Internal Interface Signals 8.2.1 Timer Input (TIN1, TIN2) This input can be programmed to be the clock that causes events to occur in the counter and prescaler.
Freescale Semiconductor, Inc. for at least one system clock period plus the sum of the setup and hold times for TINx. Refer to Section 11 Electrical Characteristics, for additional information. 8.2.2 Timer Gate ( TGATE1, TGATE2) Freescale Semiconductor, Inc... This active-low input can be programmed to enable and disable the counter and prescaler. TGATE≈ may also be programmed to be a simple input. For more information on the modes of operation, refer to 8.3 OPERATING MODES.
Freescale Semiconductor, Inc. to its location in the SR. See Figure 8-4 for a depiction of this mode. If the timing gate is disabled (CR TGE bit is cleared), TGATE≈ has no effect on the operation of the timer; thus the input capture function is inoperative. At all times, the TGATE≈ level bit (TGL) in the SR reflects the level of the TGATE≈ signal.
Freescale Semiconductor, Inc. Periodic interrupt generation can be accomplished by enabling the TO, TG, and/or TC bits in the SR to generate interrupts by programming the IE bits of the CR. When enabled, the programmed IRQ≈ signal is asserted whenever the specified bits are set. TOUTx signal transitions can be controlled by writing new values into the COM. Caution must be exercised when accessing the COM.
Freescale Semiconductor, Inc. reasserted, the timer is re-enabled and begins counting from the value attained when TGATE≈ was negated. The SR ON bit is set again. If TGATE≈ is disabled (TGE = 0), TGATE≈ has no effect on the operation of the timer. In this case, the counter begins counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. The TG bit of the SR cannot be set. At all times, TGL in the SR reflects the level of TGATE≈.
Freescale Semiconductor, Inc. successive timeout causes the counter to be loaded alternately with the values from PREL1 and PREL2. TOUTx behaves as a variable duty-cycle square wave when the CR OC bits are programmed for toggle mode. The second timeout occurs after N2 + 1 periods (allowing for the zero cycle), resulting in a change of state on TOUTx. The third timeout occurs after N1 + 1 periods, resulting in a change of state on TOUTx, and so on (see Figure 8-6).
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... The timer is enabled by setting both the SWR and CPE bits in the CR and, if TGATE≈ is enabled (TGE bit in the CR is set), then asserting TGATE≈. When the timer is enabled, the ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL1 register (N1). With each successive falling edge of the counter clock, the counter decrements.
Freescale Semiconductor, Inc. immediately after the SWR and CPE bits in the CR are set. The SR TG bit cannot be set. At all times, the TGL bit in the SR reflects the level of TGATE≈. The width of the pulse generated on TOUTx (the value in PREL2) can be changed while the counter is counting down from the value in PREL1. Caution must be used because, if PREL2 is accessed simultaneously by the counting logic and a CPU32 write, the old PREL2 value may actually get loaded into the counter at timeout.
Freescale Semiconductor, Inc. causes the counter to reload with $FFFF. TOUTx transitions at timeout or is disabled as programmed by the CR OCx bits. The SR OUT bit reflects the level on TOUTx. To determine the number of cycles counted, the value in the CNTR must be read, inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count of zero). The counter counts in a true 216 fashion.
Freescale Semiconductor, Inc. COUNTER CLOCK COUNTER 0 f f f f f f f e f f f d f f f c f f f b f f f a f f f 9 f f f 9 TGATE ENABLE PERIOD MEASURED START COUNTING STOP COUNTING NO EFFECT Freescale Semiconductor, Inc... MODEx Bits in Control Register = 101 TGE Bit of Control Register = 1 Figure 8-9. Period Measurement Mode If the counter counts down to the value stored in the COM register, the COM and TC bits in the SR are set. If the counter counts down to $0000, a timeout is detected.
Freescale Semiconductor, Inc. COUNTER CLOCK COUNTER 0 f f f f f f f e f f f d f f f c f f f b 0 0 0 2 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 f f f f f f f e TGATE ENABLE TG BIT SET TIMEOUT TO BIT SET Freescale Semiconductor, Inc... MODEx Bits in Control Register = 110 TGE Bit of the Control Register = 1 Figure 8-10. Event Count Mode The timer is enabled by setting the SWR and CPE bits in the CR and, if TGATE≈ is enabled (TGE bit of the CR is set), then asserting TGATE≈.
Freescale Semiconductor, Inc. 8.3.8 Timer Bypass In this mode, the counter and prescaler cannot be enabled. However TGATE≈ and TOUTx can be used for I/O. This mode can be selected by programming the CR MODE bits to 111.
Freescale Semiconductor, Inc. Table 8-1. OCx Encoding OC1 OC0 TOUTx 0 0 Hi-Z 0 1 0 1 0 0 1 1 1 A read of the SR while in this mode always shows the TO, TC, and COM bits cleared, and the PO bits as $FF. The SR OUT bit always indicates the level on the TOUTx pin. Freescale Semiconductor, Inc... 8.3.9 Bus Operation The following paragraphs describe the operation of the IMB during read, write, and interrupt acknowledge cycles to the timer. 8.3.9.1 READ CYCLES.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... STP—Stop bit 1 = Setting the STP bit stops all clocks within the timer module except for the clock from the IMB. The clock from the IMB remains active to allow the CPU32 access to the MCR. The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to timer module registers while in stop mode produce a bus error.
Freescale Semiconductor, Inc. 8.4.2 Interrupt Register (IR) The IR contains the priority level for the timer interrupt request and the 8-bit vector number of the interrupt. The register can be read or written to at any time while in supervisor mode and while the timer module is enabled (i.e., the STP bit in the MCR is cleared).
Freescale Semiconductor, Inc. IE2–IE0—Interrupt Enable These bits determine which sources of interrupts, TO, TG, and TC, are enabled to generate an interrupt request to the CPU32. Table 8-3 lists which interrupts are enabled for all bit combinations. Freescale Semiconductor, Inc... Table 8-3.
Freescale Semiconductor, Inc. POT2–POT0—Prescaler Output Tap If PCLK is set, these bits encode which of the prescaler's output taps act as the counter clock. A division of the selected clock is applied to the counter as listed in Table 8-4. Freescale Semiconductor, Inc... Table 8-4.
Freescale Semiconductor, Inc. Disabled—TOUTx is disabled and three-stated. Freescale Semiconductor, Inc... Toggle Mode—If the timer is disabled (SWR = 0) when this encoding is programmed, TOUTx is immediately set to zero. If the timer is enabled (SWR = 1), timeout events (counter reaches $0000) toggle TOUTx. In the input capture/output compare mode, TOUTx is immediately set to zero if the timer is disabled (SWR = 0). If the timer is enabled (SWR = 1), timer compare events toggle TOUTx.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... TO—Timeout Interrupt 1 = The counter has transitioned from $0001 to $0000, and the counter has rolled over. This bit does not affect the programmed IRQ≈ signal if the IE2 bit in the CR is cleared. 0 = This bit is cleared by the timer whenever the RESET signal is asserted on the IMB, regardless of the mode of operation. This bit may also be cleared by writing a one to it. Writing a zero to this bit does not alter its contents.
Freescale Semiconductor, Inc. 1 = This bit is set when the counter output equals the value in the COM. 0 = This bit is cleared when a timeout occurs, the COM register is accessed (read or write), the timer is reset with the SWR bit, or the RESET signal is asserted on the IMB. This bit is cleared regardless of the state of the TC bit. This bit can be used to indicate when a write to the PREL1 or PREL2 registers will not cause a problem during a counter reload at timeout.
Freescale Semiconductor, Inc. PREL1 15 $60C, $64C 14 13 12 11 10 PR1-15 PR1-14 PR1-13 PR1-12 PR1-11 PR1-10 9 8 7 6 5 4 3 2 1 0 PR1-9 PR1-8 PR1-7 PR1-6 PR1-5 PR1-4 PR1-3 PR1-2 PR1-1 PR1-0 1 1 1 1 1 1 1 1 1 1 RESET: 1 1 1 1 1 1 Supervisor/User For some modes of operation, this register is also used to reload the counter one falling clock edge after a timeout occurs. Refer to 8.3 Operating Modes for more information on the individual modes.
Freescale Semiconductor, Inc. Caution must be exercised when accessing the COM. If it were to be accessed simultaneously by the compare logic and by a write, the old compare value may get compared to the counter value. 8.5 TIMER MODULE INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the timer module. Since both timers are functionally equivalent, only one timer module will be referenced. Freescale Semiconductor, Inc... 8.5.
Freescale Semiconductor, Inc. • Enable the counter prescaler (CPE bit). • Select the selected clock (CLK bit). • If the PCLK bit is set, select the POTx bits. • Select the mode of operation (MODEx bits). • Select the operation of TOUT (OCx bits). 8.5.2 Timer Module Example Configuration Code Freescale Semiconductor, Inc... The following code is an example of a configuration sequence for the timer module.
Freescale Semiconductor, Inc. * Module configuration register: * Timer1 module is set for normal operation, ignore FREEZE. * Supervisor/user timer1 registers unrestricted. * Interrupt arbitration at priority $03. MOVE.W #$0003,MCR1(A0) * Initialize timer1 interrupt level to 2 and vector to $0F MOVE.W #$020F,IR1(A0) Freescale Semiconductor, Inc... * Initialize preload 1 to 3 MOVE.W #$0003,PRLD11(A0) * Initialize the compare register to 0 CLR.
Freescale Semiconductor, Inc. * Timer1 register offsets from timer1 base address IR1 EQU $604 interrupt register timer1 CR1 EQU $606 control register timer1 SR1 EQU $608 status register timer1 CNTR1 EQU $60A counter register timer1 COM1 EQU $610 compare register timer1 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. MOVE.W #$8A10,CR1(A0) Freescale Semiconductor, Inc... * If SR TG bit=0, continue looping TGATE is asserted, * else TG=1 indicating TGATE was negated. When TG=1, counting is stopped. LOOP3 BTST.B #$5,SR1(A0) BEQ.B LOOP3 * Counting is complete. To determine the number of cycles counted, the value * in CNTR1 must be read, inverted, and incremented by 1. MOVE.W CNTR1(A0),D0 NOT.W D0 ADDQ.W #$1,DO * D0 contains the number of cycles counted.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 9 IEEE 1149.1 TEST ACCESS PORT The MC68340 includes dedicated user-accessible test logic that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG).
Freescale Semiconductor, Inc. An overview of the MC68340 implementation of IEEE 1149.1 is shown in Figure 9-1. The MC68340 implementation includes a 16-state controller, a 3-bit instruction register, and two test registers (a 1-bit bypass register and a 132-bit boundary scan register).
Freescale Semiconductor, Inc. 1 TEST LOGIC RESET 0 1 0 SELECT-DR_SCAN RUN-TEST/IDLE 1 1 SELECT-IR_SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 Freescale Semiconductor, Inc... SHIFT-DR SHIFT-IR 0 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR EXIT2-DR 0 1 1 0 0 0 EXIT2-IR 1 1 UPDATE -IR UPDATE-DR 1 1 0 0 Figure 9-2. TAP Controller State Machine 9.3 BOUNDARY SCAN REGISTER The MC68340 IEEE 1149.1 implementation has a 132-bit boundary scan register.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 9-1. Boundary Scan Control Bits Name Bit Number Name Bit Number Name Bit Number tout2.ctl 29 cs0.ctl 66 ab28.ctl 95 irq7.ctl 52 ab.ctl 83 ab29.ctl 97 irq6.ctl 54 berr.ctl 84 ab30.ctl 99 irq5.ctl 56 db.ctl 85 ab31.ctl 101 cs3.ctl 58 ab24.ctl 87 modck.ctl 122 irq3.ctl 60 ab25.ctl 89 ifetch.ctl 125 cs2.ctl 62 ab26.ctl 91 tout1.ctl 130 cs1.ctl 64 ab27.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 9-2. Boundary Scan Bit Definitions Bit Num Cell Type Pin/Cell Name Pin Type Output CTL Cell Bit Num Cell Type Pin/Cell Name Pin Type Output CTL Cell 0 IO.Cell FC3 I/O* ab.ctl 35 O.Latch R≈RDYA Output — 1 IO.Cell FC2 I/O* ab.ctl 36 O.Latch T≈RDYA Output — 2 IO.Cell FC1 I/O* ab.ctl 37 I.Pin RxDB Input — 3 IO.Cell FC0 I/O* ab.ctl 38 O.Latch TxDB Output — 4 IO.Cell A23 I/O* ab.ctl 39 O.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 9-2. Boundary Scan Bit Definitions (Continued) Bit Num Cell Type Pin/Cell Name Pin Type Output CTL Cell Bit Num Cell Type Pin/Cell Name Pin Type Output CTL Cell 70 IO.Cell D3 I/O db.ctl 101 IO.Ctl0 ab31.ctl — — 71 IO.Cell D4 I/O db.ctl 102 IO.Cell A0 I/O* ab.ctl 72 IO.Cell D5 I/O db.ctl 103 IO.Cell DSACK0 I/O** berr.ctl 73 IO.Cell D6 I/O db.ctl 104 IO.Cell DSACK1 I/O** berr.ctl 74 IO.
Freescale Semiconductor, Inc. 1 – EXTEST 0 – OTHERWISE TO NEXT CELL SHIFT DR G1 DATA FROM SYSTEM LOGIC 1 TO OUTPUT BUFFER MUX 1 G1 1 1D Freescale Semiconductor, Inc... MUX 1 1D C1 C1 FROM LAST CELL CLOCK DR UPDATE DR Figure 9-3. Output Latch Cell (O.Latch) 1 – EXTEST 0 – OTHERWISE TO NEXT CELL G1 INPUT PIN 1 MUX 1 G1 1 1D 1D C1 C1 UPDATE DR MUX 1 CLOCK DR FROM LAST CELL SHIFT DR Figure 9-4. Input Pin Cell (I.
Freescale Semiconductor, Inc. 1 – EXTEST 0 – OTHERWISE TO NEXT CELL G1 OUTPUT CONTROL FROM SYSTEM LOGIC 1 TO OUTPUT ENABLE (1 = DRIVE) MUX 1 G1 1 1D MUX 1 1D C1 Freescale Semiconductor, Inc... C1 R SHIFT DR CLOCK DR FROM LAST CELL RESET UPDATE DR Figure 9-5. Active-High Output Control Cell (IO.Ctl1) 1 – EXTEST 0 – OTHERWISE OUTPUT CONTROL FROM SYSTEM LOGIC TO NEXT CELL FIG.
Freescale Semiconductor, Inc. 1 – EXTEST 0 – OTHERWISE TO NEXT CELL SHIFT DR G1 OUTPUT FROM SYSTEM LOGIC TO OUTPUT DRIVER 1 MUX 1 G1 G1 1 1 MUX 1D MUX 1 1 1D C1 Freescale Semiconductor, Inc... C1 FROM OUTPUT ENABLE FROM PIN FROM LAST CELL CLOCK DR UPDATE DR Figure 9-7. Bidirectional Data Cell (IO.Cell) TO NEXT CELL IO.CTL0 OR IO.CTL1 OUTPUT ENABLE * EN I/O PIN OUTPUT DATA IO.CELL INPUT DATA FROM LAST CELL TO NEXT BIDIRECTIONAL PIN NOTE: More than one lO.
Freescale Semiconductor, Inc. includes a 3-bit instruction register without parity, consisting of a shift register with three parallel outputs. Data is transferred from the shift register to the parallel outputs during the update-IR controller state. The three bits are used to decode the four unique instructions listed in Table 9-3. The parallel output of the instruction register is reset to all ones in the test-logic-reset controller state.
Freescale Semiconductor, Inc. NOTE Since there is no internal synchronization between the IEEE 1149.1 clock (TCK) and the system clock (CLKOUT), the user must provide some form of external synchronization to achieve meaningful results. The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output bits prior to selection of EXTEST. This initialization ensures that known data will appear on the outputs when entering the EXTEST instruction. Freescale Semiconductor, Inc... 9.4.
Freescale Semiconductor, Inc. The MC68340 includes on-chip circuitry to detect the initial application of power to the device. Power-on reset (POR), the output of this circuitry, is used to reset both the system and IEEE 1149.1 logic. The purpose for applying POR to the IEEE 1149.1 circuitry is to avoid the possibility of bus contention during power-on. The time required to complete device power-on is power-supply dependent. However, the IEEE 1149.
Freescale Semiconductor, Inc. SECTION 10 APPLICATIONS Freescale Semiconductor, Inc... This section provides guidelines for using the MC68340. Minimum system-configuration requirements and memory interface information are discussed. 10.1 MINIMUM SYSTEM CONFIGURATION One of the powerful features of the MC68340 is the small number of external components needed to create an entire system.
Freescale Semiconductor, Inc. 330 k 4.7 pF XTAL MC68340 20 M 32.768 kHz EXTAL 10 pF Freescale Semiconductor, Inc... Figure 10-2. Sample Crystal Circuit The circuit shown in Figure 10-3 is the typical circuit recommended by Statek Corporation, for 32768 kHz crystal, part number CX-IV. It is recommended to start with these values, but parameter values may need to be adjusted to compensate for variables in layout. 470 k 10 pF XTAL MC68340 22 M 32.768 kHz EXTAL 20 pF Figure 10-3.
Freescale Semiconductor, Inc. VCCSYN VCCSYN 0.1 µF 1 MC68340 0.1 µF 0.01 µF XFC NOTE 1: Must be a low-leakage capacitor. Freescale Semiconductor, Inc... Figure 10-4. XFC and V CCSYN Capacitor Connections 10.1.2 Reset Circuitry Because it is optional, reset circuitry is not shown in Figure 10-1. The MC68340 holds itself in reset after power-up and asserts RESET to the rest of the system.
Freescale Semiconductor, Inc. load capacitance on the chip-select (CS≈) signal is not exceeded. (Address buffers may be needed, however.) 10.1.4 ROM Interface Using the programmable chip selects creates a very straightforward ROM interface. As shown in Figure 10-6, no external circuitry is needed. Care must be used, however, not to overload the address bus. Address buffers may be required to ensure that the total system input capacitance on the address signals does not exceed the CL specification.
Freescale Semiconductor, Inc. 15 pF X1 3.6864 MHz X2 RxDx R TxDx RS 232 CONNECTOR 5 pF MC68340 Rx1 Tx1 T MC145407 VCC Freescale Semiconductor, Inc... 10 µF 10 µ F C1+ C2+ C1- C1- VSS C2+ GND C2- 10 µF 10 µ F Figure 10-7. Serial Interface 10.
Freescale Semiconductor, Inc. S0 S1 S2 SW SW SW SW S3 S4 S5 S0 S1 S2 CLKOUT CS0 Q1 DSACK0 Freescale Semiconductor, Inc... Figure 10-9. 8-bit Boot ROM Timing 10.2.2 Access Time Calculations The two time paths that are critical in an MC68340 application using the CS≈ signals are shown in Figure 10-10. The first path is the time from address valid to when data must be available to the processor; the second path is the time from CS≈ asserted to when data must be available to the processor.
Freescale Semiconductor, Inc. An equation for the chip select access time, tCSDV, can be developed as follows: tCSDV = t cyc(N c – 1) – t s9 – ts27 where: tcyc = system clock period Nc = number of clocks per access ts9 = CLKOUT low to CS≈ asserted = 30 ns maximum at 16.78 MHz ts27 = data-in valid to CLKOUT low setup = 5 ns minimum at 16.78 MHz Freescale Semiconductor, Inc... Using these equations, the memory access times at 16.78 MHz are shown in Table 10-1.
Freescale Semiconductor, Inc. Additionally, the relationship between the asynchronous inputs and the clock edge, as shown in Figure 10-11, does not change as frequency changes. A second type of specification indicates the minimum amount of time a signal will be asserted. This type of specification is illustrated in Figure 10-12. T/2 N CLKOUT td OUTPUT Freescale Semiconductor, Inc... tw Figure 10-12.
Freescale Semiconductor, Inc. T/2 CLKOUT td1 OUTPUT1 t d2 OUTPUT2 ts Figure 10-13. Skew between Two Outputs Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 10.2.4 Interfacing an 8-Bit Device to 16-Bit Memory Using SingleAddress DMA Mode One of the requirements of single-address mode is that the source and destination must be the same port size. However, the MC68340 can perform direct memory accesses in single-address mode between an 8-bit device and 16-bit memory. The port size must be specified as 8 bits, and some external logic is required as shown in Figure 10-14. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 10.3.1 MC68340 Power Reduction at 5V The following figures show how different variables affect typical power consumption at 5 V. Figure 10-15 shows how system activity affects current drain. Figure 10-16 shows how voltage affects current drain at some typical operating temperatures. Figure 10-17 shows how system clock frequency affects current drain. 120 Typical values 32KHz xtal 16.78 MHz 24 ° C 93 81 I cc (mA) Freescale Semiconductor, Inc... 90 73 66 60 62 42 30 .
Freescale Semiconductor, Inc. 120 0° C 24° C 100 100° C Icc (mA) Typical values 32KHz xtal 16.78 MHz peak current Freescale Semiconductor, Inc... 80 60 4 5.5 5 VCC (V) Figure 10-16. MC68340 Current vs. Voltage/Temperature 120 Icc (mA) 90 Typical values 32KHz xtal peak current 24° C 60 30 0 0 2 4 6 8 10 12 14 16 Clock Frequency (MHz) Figure 10-17. MC68340 Current vs. Clock Frequency at 5 V 10-12 MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 10.3.2 MC68340V (3.3 V) The MC68340V can operate with a 3.3-V power supply for significant power savings. The formula for power dissipation is Pd ≈ V2 × f + dc Table 10-2 shows typical electrical characteristics for both the MC68340 and MC68340V. Table 10-2. Typical Electrical Characteristics Parameter MC68340 (5.0 V) MC68340V (3.3 V) 0–16.78 MHz 0–25 MHz 0–8.39 MHz 0–16.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 11 ELECTRICAL CHARACTERISTICS This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MC68340. Refer to Section 12 Ordering Information and Mechanical Data for specific part numbers corresponding to voltage, frequency, and temperature ratings. 11.
Freescale Semiconductor, Inc. 11.3 POWER CONSIDERATIONS The average chip-junction temperature, TJ, in °C can be obtained from: Freescale Semiconductor, Inc... TJ = T A + (PD • θJA) (1) where: TA = Ambient Temperature, °C θJA = Package Thermal Resistance, Junction-to-Ambient, °C/W PD = PINT + PI/O PINT = ICC x VCC, Watts—Chip Internal Power PI/O = Power Dissipation on Input and Output Pins—User Determined For most applications, P I/O < PINT and can be neglected.
Freescale Semiconductor, Inc. The MC68340V low voltage parts can operate up to 8.39 MHz or 16.78 MHz with a 3.3 V ±0.3 V supply. Separate part numbers are used to distinguish the operation of the parts according to the supply voltage. Refer to Section 12 Ordering Information and Mechanical Data for the part numbering schemes. MC68340 is used throughout this section to refer to the 16.78- or 25.16-MHz parts at 5.0 V ±5%. MC68340V is used throughout this section to refer to the 8.39- or 16.78-MHz parts at 3.
Freescale Semiconductor, Inc. 2.0 V 2.0 V CLKOUT 0.8 V 0.8 V A B OUTPUTS(1) VALID OUTPUT n 2.0 V 2.0 V 0.8 V 0.8 V VALID OUTPUT A n+1 B VALID OUTPUT n Freescale Semiconductor, Inc... OUTPUTS(2) C 2.0 V INPUTS(3) 0.8 V 2.0 V 2.0 V 0.8 V 0.8 V VALID OUTPUT n+1 D 2.0 V VALID INPUT 0.8 V C 2.0 V INPUTS(4) 0.8 V D VALID INPUT 2.0 V 0.8 V DRIVE TO 2.4 V DRIVE TO 0.5 V 2.0 V ALL SIGNALS(5) 0.8 V E F 2.0 V 0.8 V NOTES: 1.
Freescale Semiconductor, Inc. 11.5 DC ELECTRICAL SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70°C; see numbered notes) Characteristic Symbol Min Max Unit VIH VIL 2.0 VCC 0.8 V GND V Input High Voltage (except clock) Input Low Voltage Clock Input High Voltage Undershoot VIHC — 0.7 * (V CC ) — VCC +0.3 –0.8 I in I OZ –2.5 2.5 µA –20 20 µA IL –0.015 0.2 mA IH –0.015 0.2 mA VOH 2.
Freescale Semiconductor, Inc. 11.6 AC ELECTRICAL SPECIFICATIONS CONTROL TIMING (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70°C; see numbered notes) 3.3 V 3.3 V or 5.0 V 8.39 MHz Num. Characteristic System Frequency1 Min Max Min Max Min Max Unit f sys dc 8.39 dc 16.78 dc 25.16 MHz f XTAL 25 50 25 50 25 50 kHz On-Chip VCO System Frequency f sys 0.13 8.39 0.13 16.78 0.13 25.16 MHz On-Chip VCO Frequency Range f VCO 0.1 16.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 10. For external clock w/PLL mode operation, the minimum CLKOUT pulse width is based on a 50% duty cycle. 11. For external clock mode, there is a 10–40 ns skew between the input clock signal and the output CLKOUT signal from the MC68340. Clock skew is measured from the rising edges of the clock signals. 12. For external clock mode w/PLL, there is a 5 ns skew between the input clock signal and the output CLKOUT signal from the MC68340.
Freescale Semiconductor, Inc. 11.7 AC TIMING SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70°C; see numbered notes; see Figures 11-2–11-11) Freescale Semiconductor, Inc... Num. 3.3 V 3.3 V or 5.0 V 5.0 V 8.39 MHz 16.78 MHz 25.
Freescale Semiconductor, Inc. 11.7 AC TIMING SPECIFICATIONS (Continued) 3.3 V 5.0 V 8.39 MHz 16.78 MHz 25.
Freescale Semiconductor, Inc. 11.7 AC TIMING SPECIFICATIONS (Continued) 3.3 V Freescale Semiconductor, Inc... Num. Characteristic 3.3 V or 5.0 V 5.0 V 8.39 MHz 16.78 MHz 25.
Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 CLKOUT 6 8 SIZ1–SIZ0 FC3–FC0 A31–A0 RMC Freescale Semiconductor, Inc... 11 14 AS 12 9 13 DS 9A CS 18 21 20 R/W 46 28 47A DSACK0 DSACK1 29 31 D15–D0 29A 27 BERR 48 27A HALT 9 12 12 IFETCH 47A 47B ASYNCHRONOUS INPUTS 27A BKPT NOTE: All timing is shown with respect to 0.8V and 2.0V levels. Figure 11-2. Read Cycle Timing Diagram MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. S1 S0 S3 S2 S4 S5 CLKOUT 6 8 A31–A0 FC3–FC0 SIZ1–SIZ0 11 15 14 Freescale Semiconductor, Inc... AS 9 12 9 13 DS CS 20 14A 22 17 R/W 46 DSACK0 28 47A DSACK1 25 55 53 D15–D0 23 54 26 BERR 48 27A HALT BKPT NOTE: All timing is shown with respect to 0.8-V and 2.0-V levels. Figure 11-3. Write Cycle Timing Diagram 11-12 MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. S0 S1 S4 S5 S0 CLKOUT 8 6 Freescale Semiconductor, Inc... A31–A0 FC3–FC0 SIZ1–SIZ0 9 14B AS 12 DS CS 18 R/W 46A 27 30 D15–D0 27A 30A BKPT Figure 11-4. Fast Termination Read Cycle Timing Diagram MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. S0 S4 S1 S5 S0 CLKOUT 8 6 Freescale Semiconductor, Inc... A31–A0 FC3–FC0 SIZ1–SIZ0 12 AS 9 14B DS CS 20 46A R/W 23 24 18 D15-D0 27A 25 BKPT Figure 11-5. Fast Termination Write Cycle Timing Diagram 11-14 MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 CLKOUT A31–A0 7 Freescale Semiconductor, Inc... D15–D0 AS 16 DS R/W DSACK0 DSACK1 47A BR 35 39A BG 33 34 BGACK 37 Figure 11-6. Bus Arbitation Timing—Active Bus Case MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. CLKOUT A31–A0 D15–D0 AS 47A 47A BR 37 Freescale Semiconductor, Inc... 35 BG 33 47A 34 BGACK Figure 11-7. Bus Arbitration Timing—Idle Bus Case S41 S0 S42 S43 S1 S0 S2 CLKOUT 8 6 A31–A0 18 R/W 20 AS 12 15 9 DS 70 72 71 D15–D0 27A BKPT SHOW CYCLE START OF EXTERNAL CYCLE Figure 11-8. Show Cycle Timing Diagram 11-16 MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 0–2 CLOCKS * S0 S1 S2 S3 S4 S5 CLKOUT 6 8 SIZ1–SIZ0 Freescale Semiconductor, Inc... FC3–FC0 A31–A0, 11 14 AS 13 9 12 DS 9A IACKx 18 20 21 R/W 46 31A 28 DSACK0 47A DSACK1 31 29 D15-D0 29A 27 * Up to two wait states may be inserted by the processor between states S0 and S1. Figure 11-9. IACK Cycle Timing Diagram MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. CLKOUT FREEZE 83 82 Freescale Semiconductor, Inc... BKPT/DSCLK 85 81 80 IFETCH/DSI 84 IPIPE/DSO Figure 11-10. Background Debug Mode Serial Port Timing CLKOUT 86 FREEZE 87 IFETCH/DSI 88 89 Figure 11-11. Background Debug Mode FREEZE Timing 11-18 MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 11.8 DMA MODULE AC ELECTRICAL SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70°C; see Figure 11-12) 3.3 V 3.3 V or 5.0 V 8.39 MHz Freescale Semiconductor, Inc... Num. Characteristic 5.0 V 16.78 MHz 25.
Freescale Semiconductor, Inc. 11.9 TIMER MODULE ELECTRICAL SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70°C; see Figures 11-13 and 11-14) 3.3 V 3.3 V or 5.0 V 8.39 MHz Freescale Semiconductor, Inc... Num. Characteristic 16.78 MHz 5.0 V 25MHz Symbol Min Max Min Max Min Max Unit t cyc 119.2 — 59.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. CLKOUT 5 4 TIN 6 7 TGATE 8 TOUT Figure 11-14. Timer Module Signal Timing Diagram MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 11.10 SERIAL MODULE ELECTRICAL SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70°C; see numbered notes; see Figures 11-15–11-18) Num. Freescale Semiconductor, Inc... 1 Characteristic 3.3 V 3.3 V or 5.0 V 5.0 V 8.39 MHz 16.78 MHz 25.16 MHz Symbol Min Max Min Max Min Max Unit CLKOUT Cycle Time t cyc 119.2 — 59.
Freescale Semiconductor, Inc. 6 X1 2 2 7 7 Freescale Semiconductor, Inc... Figure 11-16. Serial Module Asynchronous Mode Timing (X1) 2 2 SCLK (16x) 8 8 Figure 11-17. Serial Module Asynchronous Mode Timing (SCLK–16X) 10 9 2 2 SCLK (1x) 11 TxD 13 12 RxD Figure 11-18. Serial Module Synchronous Mode Timing Diagram MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 11.11 IEEE 1149.1 ELECTRICAL SPECIFICATIONS ( See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70°C; see Figures 11-19–11-21) Num. Characteristic 3.3 V or 5.0 V 5.0 V 8.39 MHz 16.78 MHz 25.16 MHz Min Max TCK Frequency of Operation Freescale Semiconductor, Inc... 3.3 V Min Max Min Max Unit 0 8.39 0 16.78 0 25 MHz 119.2 — 59.6 — 40 — ns TCK Clock Pulse Width Measured at 1.
Freescale Semiconductor, Inc. TCK VIH VIL 7 6 DATA INPUTS INPUT DATA VALID 8 Freescale Semiconductor, Inc... DATA OUTPUTS OUTPUT DATA VALID 9 DATA OUTPUTS 8 DATA OUTPUTS OUTPUT DATA VALID Figure 11-20. Boundary Scan Timing Diagram VIH TCLK VIL 10 TDI TMS 11 INPUT DATA VALID 12 TDO OUTPUT DATA VALID 13 TDO 12 TDO OUTPUT DATA VALID Figure 11-21. Test Access Port Timing Diagram MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. SECTION 12 ORDERING INFORMATION AND MECHANICAL DATA Freescale Semiconductor, Inc... This section contains ordering information, pin assignments and package dimensions of the MC68340. 12.1 STANDARD MC68340 ORDERING INFORMATION Supply Voltage Package Type Frequency (MHz) Temperature Order Number 5.0 V Ceramic Quad Flat Pack FE Suffix 0 – 16.78 0 – 16.78 0 – 25 0°C to +70°C –40°C to +85°C 0°C to +70°C MC68340FE16 MC68340CFE16 MC68340FE25 5.
Freescale Semiconductor, Inc. 12.2 PIN ASSIGNMEN — CERAMIC SURFACE MOUNT RMC R/W D1 109 108 127 126 144 1 D0 D3 D2 D4 GND VCC D5 D7 D6 D9 D8 D11 D10 D12 GND VCC D13 GND D15 D14 A25 A24 A26 VCC A27 A28 GND A30 A29 DSACK0 A0 A31 VCC DSACK1 GND 12.2.
Freescale Semiconductor, Inc. The VCC and GND pins are separated into groups to help electrically isolate the output drivers for different functions of the MC68340. These groups are shown in the following table for the FE suffix package.
Freescale Semiconductor, Inc. 12.2.2 145-Lead Plastic Pin Grid Array (RP Suffix) Q FC1 FC3 TDI TCK TIN1 FREEZE IPIPE MODCK EXTAL XFC RESET BERR BR AS SIZ1 A23 FC2 TDO TMS TOUT1 BKPT DS R/W RMC A22 FC0 GND VCC A20 GND VCC VCC A0 A3O A18 A19 A21 A31 A29 A28 A16 A17 VCC GND VCC A27 A14 A15 GND A25 A24 A26 GND D14 D15 P V CC XTAL VCC CLKOUT HALT BGACK N TGATE1 IFETCH GND VCCSYN V CC . GND BG SIZ0 GND DSACK1 DSACK0 M Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. The V CC and GND pins are separated into groups to help electrically isolate the different output drivers of the MC68340. These groups are shown in the following table for the RP suffix package.
Freescale Semiconductor, Inc. 12.3 PACKAGE DIMENSIONS 12.3.1 FE Suffix X FE SUFFIX PACKAG CERAMIC QFP CASE 863A-01 PIN ONE INDEN A/B Freescale Semiconductor, Inc... TOP VIEW TRIMMED, FORMED DISCRET SHOWING DATUM FEATUR Z R K Q S Z Y S S 0.50M T X Y C M J M W ∩ 0.10144X T SEATING PLANE H D 144X G ZS 0.20M T X-Y 0.20M T Z S X-Y S S/V SIDE VIEW GULL WING LEAD CONFIGURA MILLIMETE DIM MIN MAX A 25.84 27.70 B 25.84 27.70 4.31 3.55 C 0.22 0.41 D 0.65 BS G 0.25 0.88 H 0.13 0.25 J 0.65 0.
Freescale Semiconductor, Inc. 12.3.2 RP Suffix V 145 PIN PGA CASE NO. 768E-01 C Q P N M L K J H G F E D C B A T D Freescale Semiconductor, Inc... G S A B PIN A-1 G BOTTOM VIEW 1 L V 2 3 4 5 6 7 8 9 10 11 12 13 14 15 M 145 PL K MILLIMETERS INCHES DIM MIN MAX MIN MAX A 39.37 39.88 1.570 B C D 39.37 22.75 22.75 39.88 22.97 1.550 1.550 0.895 0.905 0.905 22.97 0.895 1.570 G K 2.54 BASIC 2.92 3.43 0.100 BASIC 0.115 0.135 L M S V 1.02 1.52 0.43 0.55 4.32 4.95 35.
Freescale Semiconductor, Inc. INDEX Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. During DMA Transfers, 6-18, 6-20, 6-31, 6-33–6-35 Grant Acknowledge Signal, 3-40–3-44 Request Signal, 2-7, 3-37, 3-40–3-44, 6-25 State Diagram, 3-45 Bypass Register, 9-11 Byte Transfer Counter, 6-15, 6-19–6-20, 6-34–6-35, 6-37–6-38 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. — J — — N — JTAG, 4-2 NCS Bit, 4-31 Negate RTS Command, 7-29 Negative Tails, 5-93–5-94 No Operation Command, 5-86 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. R≈RDYA Signal, 7-7, 7-36 RxRDYB Bit, 7-33, 7-35 RxRTS Bit, 7-22, 7-47 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. — Y — Y Bits, 4-12–4-13, 4-28, 4-36 — Z — Freescale Semiconductor, Inc... Zero Mode, 8-23 MOTOROLA MC68340 USER’S MANUAL For More Information On This Product, Go to: www.freescale.