Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL 4- 17
The number of wait states programmed into the internal wait state generation logic by a
chip select can be used even though the pin is not used as a
CS≈ signal. The
programmed number of wait states in the
CS≈ signal applies to the port B pins configured
as
IRQ≈ or I/O pins. This is done by programming the chip select with the number of wait
states to be added, as though it were to be used. The DD1/DD0 and PS1/PS0 bits in the
chip select address mask register must be set to add the desired number of wait states
(the V-bit in the module base address register should be set).
4.2.6 Low-Power Stop
Executing the LPSTOP instruction provides reduced power consumption when the
MC68340 is idle; only the SIM40 remains active. Operation of the SIM40 clock and
CLKOUT during LPSTOP is controlled by the STSIM and STEXT bits in the SYNCR (see
Table 4-3). LPSTOP disables the clock to the software watchdog in the low state. The
software watchdog remains stopped until the LPSTOP mode ends; it begins to run again
on the next rising clock edge.
NOTE
When the CPU32 executes the STOP instruction (as opposed
to LPSTOP), the software watchdog continues to run. If the
software watchdog is enabled, it issues a reset or interrupt
when timeout occurs.
The periodic interrupt timer does not respond to an LPSTOP instruction; thus, it can be
used to exit LPSTOP as long as the interrupt request level is higher than the CPU32
interrupt mask level. To stop the periodic interrupt timer while in LPSTOP, the PITR must
be loaded with a zero value before LPSTOP is executed. The bus monitor, double bus
fault monitor, and spurious interrupt monitor are all inactive during LPSTOP.
The STP bit in the MCR of each on-chip module (DMA, timers, and serial modules) should
be set prior to executing the LPSTOP instruction. Setting the STP bit stops all clocks
within each of the modules, except for the clock from the IMB. The clock from the IMB
remains active to allow the CPU32 access to the MCR of each module. The system clock
stops on the low phase of the clock and remains stopped until the STP bit is cleared by
the CPU32 or until reset. For more information, see the description of the MCR STP bit for
each module.
If an external device requires additional time to prepare for entry into LPSTOP mode,
entry can be delayed by asserting
HALT (see 3.4.2 LPSTOP Broadcast Cycle).
4.2.7 Freeze
FREEZE is asserted by the CPU32 if a breakpoint is encountered with background mode
enabled. Refer to Section 5 CPU32 for more information on the background mode. When
FREEZE is asserted, the double bus fault monitor and spurious interrupt monitor continue
to operate normally. However, the software watchdog, the periodic interrupt timer and the
internal bus monitor will be affected. When FREEZE is asserted, setting the FRZ1 bit in
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