Typewriter User Manual

11/2/95 SECTION 1: OVERVIEW UM Rev.1.0
xii MC68340 USER'S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
6.3.2.2 External Cycle Steal Mode..................................................................... 6-5
6.4 Data Transfer Modes........................................................................................ 6-6
6.4.1 Single-Address Mode.................................................................................. 6-6
6.4.1.1 Single-Address Read............................................................................... 6-7
6.4.1.2 Single-Address Write............................................................................... 6-9
6.4.2 Dual-Address Mode ..................................................................................... 6-12
6.4.2.1 Dual-Address Read.................................................................................. 6-12
6.4.2.2 Dual-Address Write .................................................................................. 6-14
6.5 Bus Arbitration................................................................................................... 6-18
6.6 DMA Channel Operation................................................................................. 6-18
6.6.1 Channel Initialization and Startup............................................................. 6-18
6.6.2 Data Transfers............................................................................................... 6-19
6.6.2.1 Internal Request Transfers...................................................................... 6-19
6.6.2.2 External Request Transfers..................................................................... 6-19
6.6.3 Channel Termination ................................................................................... 6-20
6.6.3.1 Channel Termination............................................................................... 6-20
6.6.3.2 Interrupt Operation.................................................................................... 6-20
6.6.3.3 Fast Termination Option .......................................................................... 6-20
6.7 Register Description......................................................................................... 6-22
6.7.1 Module Configuration Register (MCR)...................................................... 6-23
6.7.2 Interrupt Register (INTR).............................................................................. 6-26
6.7.3 Channel Control Register (CCR) ............................................................... 6-26
6.7.4 Channel Status Register (CSR)................................................................. 6-30
6.7.5 Function Code Register (FCR) ................................................................... 6-32
6.7.6 Source Address Register (SAR) ................................................................ 6-33
6.7.7 Destination Address Register (DAR)......................................................... 6-33
6.7.8 Byte Transfer Counter Register (BTC)...................................................... 6-34
6.8 Data Packing ..................................................................................................... 6-35
6.9 DMA Channel Initialization Sequence ......................................................... 6-36
6.9.1 DMA Channel Configuration...................................................................... 6-36
6.9.1.1 DMA Channel Operation in Single-Address Mode............................ 6-37
6.9.1.2 DMA Channel Operation in Dual-Address Mode............................... 6-37
6.9.2 DMA Channel Example Configuration Code .......................................... 6-38
Section 7
Serial Module
7.1 Module Overview.............................................................................................. 7-2
7.1.1 Serial Communication Channels A and B............................................... 7-3
7.1.2 Baud Rate Generator Logic ........................................................................ 7-3
7.1.3 Internal Channel Control Logic.................................................................. 7-3
7.1.4 Interrupt Control Logic ................................................................................. 7-3
Frees
cale Semiconductor,
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Freescale Semiconductor, Inc.
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