Typewriter User Manual

5- 36 MC68340 USER’S MANUAL MOTOROLA
5.3.4.5 Table Example 5: Surface Interpolations. The various forms of table can be
used to perform surface (3D) TBLs. However, since the calculation must be split into a
series of 2D TBLs, the possibility of losing precision in the intermediate results is possible.
The following code sequence, incorporating both TBLS and TBLSN, eliminates this
possibility.
L0:
MOVE.W Dx, Dl Copy entry number and fraction number
TBLSN.B 〈ea〉, Dx
TBLSN.B 〈ea〉, Dl
TBLS.W Dx:Dl, Dm Surface interpolation, with round
ASR.L #8, Dm Read just the result
BCC.B L1 No round necessary
ADDQ.B #1, Dl Half round up
L1: . . .
Before execution of this code sequence, Dx must contain fraction and entry numbers for
the two TBL, and Dm must contain the fraction for surface interpolation. The 〈ea〉 fields in
the TBLSN instructions point to consecutive columns in a 3D table. The TBLS size
parameter must be word if the TBLSN size parameter is byte, and must be long word if
TBLSN is word. Increased size is necessary because a larger number of significant digits
is needed to accommodate the scaled fractional results of the 2D TBL.
5.3.5 Nested Subroutine Calls
The LINK instruction pushes an address onto the stack, saves the stack address at which
the address is stored, and reserves an area of the stack for use. Using this instruction in a
series of subroutine calls will generate a linked list of stack frames.
The UNLK instruction removes a stack frame from the end of the list by loading an
address into the SP and pulling the value at that address from the stack. When the
instruction operand is the address of the link address at the bottom of a stack frame, the
effect is to remove the stack frame from both the stack and the linked list.
5.3.6 Pipeline Synchronization with the NOP Instruction
Although the no operation (NOP) instruction performs no visible operation, it does force
synchronization of the instruction pipeline, since all previous instructions must complete
execution before the NOP begins.
5.4 PROCESSING STATES
This section describes the processing states of the CPU32. It includes a functional
description of the bits in the supervisor portion of the SR and an overview of actions taken
by the processor in response to exception conditions.
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