Typewriter User Manual

11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL xvii
LIST OF ILLUSTRATIONS
Figure Page
Number Title Number
1-1 Block Diagram......................................................................................................... 1-1
2-1 Functional Signal Groups ..................................................................................... 2-1
3-1 Input Sample Window............................................................................................ 3-2
3-2 MC68340 Interface to Various Port Sizes.......................................................... 3-7
3-3 Long-Word Operand Read Timing from 8-Bit Port............................................ 3-11
3-4 Long-Word Operand Write Timing to 8-Bit Port................................................. 3-12
3-5 Long-Word and Word Read and Write Timing—16-Bit Port........................... 3-13
3-6 Fast Termination Timing........................................................................................ 3-15
3-7 Word Read Cycle Flowchart ................................................................................. 3-16
3-8 Word Write Cycle Flowchart.................................................................................. 3-18
3-9 Read-Modify-Write Cycle Timing ......................................................................... 3-19
3-10 CPU Space Address Encoding............................................................................ 3-21
3-11 Breakpoint Operation Flowchart.......................................................................... 3-24
3-12 Breakpoint Acknowledge Cycle Timing (Opcode Returned).......................... 3-25
3-13 Breakpoint Acknowledge Cycle Timing (Exception Signaled) ...................... 3-26
3-14 Interrupt Acknowledge Cycle Flowchart............................................................. 3-28
3-15 Interrupt Acknowledge Cycle Timing .................................................................. 3-29
3-16 Autovector Operation Timing................................................................................ 3-31
3-17 Bus Error without
DSACK≈................................................................................... 3-35
3-18 Late Bus Error with
DSACK≈................................................................................ 3-36
3-19 Retry Sequence ...................................................................................................... 3-37
3-20 Late Retry Sequence ............................................................................................. 3-38
3-21
HALT Timing............................................................................................................ 3-39
3-22 Bus Arbitration Flowchart for Single Request.................................................... 3-41
3-23 Bus Arbitration Timing Diagram—Idle Bus Case.............................................. 3-42
3-24 Bus Arbitration Timing Diagram—Active Bus Case......................................... 3-42
3-25 Bus Arbitration State Diagram.............................................................................. 3-45
3-26 Show Cycle Timing Diagram................................................................................ 3-46
3-27 Timing for External Devices Driving
RESET...................................................... 3-47
3-28 Power-Up Reset Timing Diagram........................................................................ 3-48
4-1 SIM40 Module Register Block.............................................................................. 4-3
4-2 System Configuration and Protection Function ................................................ 4-5
4-3 Software Watchdog Block Diagram.................................................................... 4-7
4-4 Clock Block Diagram for Crystal Operation ....................................................... 4-10
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cale Semiconductor,
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