Typewriter User Manual

5- 46 MC68340 USER’S MANUAL MOTOROLA
case of a released operand write. Released write exceptions are delayed until the next
instruction boundary or attempted operand access.
An address exception on a branch to an odd address is delayed until the PC is changed.
No exception occurs if the branch is not taken. In this case, the fault address and return
PC value placed in the exception stack frame are the odd address, and the current
instruction PC points to the instruction that caused the exception.
If an address error occurs during exception processing for a bus error, another address
error, or a reset, the processor halts.
5.5.2.4 INSTRUCTION TRAPS. Traps are exceptions caused by instructions. They arise
from either processor recognition of abnormal conditions during instruction execution or
from use of specific trapping instructions. Traps are generally used to handle abnormal
conditions that arise in control routines.
The TRAP instruction, which always forces an exception, is useful for implementing
system calls for user programs. The TRAPcc, TRAPV, CHK, and CHK2 instructions force
exceptions when a program detects a run-time error. The DIVS and DIVU instructions
force an exception if a division operation is attempted with a divisor of zero.
Exception processing for traps follows the regular sequence. If tracing is enabled when an
instruction that causes a trap begins execution, a trace exception will be generated by the
instruction, but the trap handler routine will not be traced (the trap exception will be
processed first, then the trace exception).
The vector number for the TRAP instruction is internally generated—part of the number
comes from the instruction itself. The trap vector number, PC value, and a copy of the SR
are saved on the supervisor stack. The saved PC value is the address of the instruction
that follows the instruction that generated the trap. For all instruction traps other than
TRAP, a pointer to the instruction causing the trap is also saved in the fifth and sixth
words of the exception stack frame.
5.5.2.5 SOFTWARE BREAKPOINTS. To support hardware emulation, the CPU32 must
provide a means of inserting breakpoints into target code and of announcing when a
breakpoint is reached.
The MC68000 and MC68008 can detect an illegal instruction inserted at a breakpoint
when the processor fetches from the illegal instruction exception vector location. Since the
VBR on the CPU32 allows relocation of exception vectors, the exception vector address is
not a reliable indication of a breakpoint. CPU32 breakpoint support is provided by
extending the function of a set of illegal instructions ($4848–$484F).
When a breakpoint instruction is executed, the CPU32 performs a read from CPU space
$0, at a location corresponding to the breakpoint number. If this bus cycle is terminated by
BERR, the processor performs illegal instruction exception processing. If the bus cycle is
terminated by
DSACK≈, the processor uses the data returned to replace the breakpoint in
the instruction pipeline and begins execution of that instruction. See Section 3 Bus
Operation for a description of CPU space operations.
Frees
cale Semiconductor,
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Freescale Semiconductor, Inc.
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