Typewriter User Manual

11/2/95 SECTION 1: OVERVIEW UM Rev.1.0
xviii MC68340 USER'S MANUAL MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
4-5 MC68340 Crystal Oscillator.................................................................................. 4-10
4-6 Clock Block Diagram for External Oscillator Operation................................... 4-11
4-7 Full Interrupt Request Multiplexer........................................................................ 4-16
4-8 SIM40 Programming Model.................................................................................. 4-19
5-1 CPU32 Block Diagram........................................................................................... 5-3
5-2 Loop Mode Instruction Sequence ....................................................................... 5-3
5-3 User Programming Model..................................................................................... 5-9
5-4 Supervisor Programming Model Supplement.................................................. 5-9
5-5 Status Register........................................................................................................ 5-10
5-6 Instruction Word General Format......................................................................... 5-12
5-7 Table Example 1..................................................................................................... 5-30
5-8 Table Example 2..................................................................................................... 5-31
5-9 Table Example 3..................................................................................................... 5-33
5-10 Exception Stack Frame.......................................................................................... 5-42
5-11 Reset Operation Flowchart.................................................................................... 5-45
5-12 Format $0—Four-Word Stack Frame.................................................................. 5-60
5-13 Format $2—Six-Word Stack Frame.................................................................... 5-60
5-14 Internal Transfer Count Register.......................................................................... 5-61
5-15 Format $C—BERR Stack for Prefetches and Operands.................................. 5-62
5-16 Format $C—BERR Stack on MOVEM Operand................................................ 5-62
5-17 Format $C—Four- and Six-Word BERR Stack.................................................. 5-63
5-18 In-Circuit Emulator Configuration ........................................................................ 5-64
5-19 Bus State Analyzer Configuration ....................................................................... 5-64
5-20 BDM Block Diagram............................................................................................... 5-65
5-21 BDM Command Execution Flowchart................................................................. 5-68
5-22 Debug Serial I/O Block Diagram.......................................................................... 5-70
5-23 Serial Interface Timing Diagram.......................................................................... 5-71
5-24
BKPT Timing for Single Bus Cycle...................................................................... 5-72
5-25
BKPT Timing for Forcing BDM ............................................................................. 5-72
5-26
BKPT/DSCLK Logic Diagram .............................................................................. 5-72
5-27 Command-Sequence Diagram............................................................................ 5-75
5-28 Functional Model of Instruction Pipeline............................................................ 5-87
5-29 Instruction Pipeline Timing Diagram................................................................... 5-88
5-30 Block Diagram of Independent Resources ........................................................ 5-90
5-31 Simultaneous Instruction Execution.................................................................... 5-91
5-32 Attributed Instruction Times................................................................................... 5-92
5-33 Example 1—Instruction Stream ........................................................................... 5-95
5-34 Example 2—Branch Taken................................................................................... 5-95
5-35 Example 2—Branch Not Taken............................................................................ 5-96
5-36 Example 3—Branch Negative Tail...................................................................... 5-96
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