Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL 6- 9

NOTE:

1. DREQx must be active for two consecutive clocks for a DMA request to be recognized.

2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated.

3. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.

A31–A0

R/W

S4 S0

S2 S4

D15–D0

DREQx

DACKx

DMA READCPU CYCLE

CPU CYCLE CPU CYCLE

DMA READ

DONEx

(INPUT)

Figure 6-6. Single-Address Read Timing (Cycle Steal)

FC3–FC0

SIZ1–SIZ0

DSACKx

DONEx

(OUTPUT)

CLKOUT

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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