Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL 6- 11
A31–A0
FC3–FC0
SIZ1-SIZ0
R/W
AS
DS
DSACKx
S0 S2
S4 S0
S2 S4
S0
S2
S4
S0
S2
S4S0
S2
S4
D15–D0
DREQx
DACKx
DMA WRITE
CPU CYCLE
NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the destination (write) DMA cycle.
CLKOUT
CPU CYCLE
DMA WRITE
DONEx
(INPUT)
Figure 6-8. Single-Address Write Timing (Cycle Steal)
CPU CYCLE
DONEx
(OUTPUT)
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cale Semiconductor,
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