Typewriter User Manual

6- 14 MC68340 USER’S MANUAL MOTOROLA
NOTE 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, the DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 4. DONEx (input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one.
A31–A0
FC3–FC0
SIZ1–SIZ0
R/W
AS DS
DSACKx
S0
S2 S4 S0 S2
S4
S0
S2
S4
S0
S2 S4
S0
S2
S4
D15–D0
DREQx
DACKx
DONEx
(OUTPUT)
DMA READCPU CYCLE
CLKOUT
CPU CYCLE
CPU CYCLE
DMA WRITE
DMA READ
DMA WRITE
S0
S2 S4
S0
S2 S4
DONEx
(INPUT)
Figure 6-10. Dual-Address Read Timing (Cycle Steal–Source Requesting)
6.4.2.2 DUAL-ADDRESS WRITE. During the dual-address write cycle, the DMA writes
data to a device or memory from the internal DHR. The data in the DHR is written to the
device or memory selected by the address in the DAR, the destination function codes in
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