Typewriter User Manual

6- 16 MC68340 USER’S MANUAL MOTOROLA

NOTE:

1. Timing to generate more than one DMA transfer.

2. DACKx and DONEx (DMA control signals) are asserted in the destination (write) DMA cycle.

3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized.

4. DONEx (input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one.

CLKOUT

A31–A0

FC3–FC0

SIZ1–SIZ0

R/W

DSACKx

S2 S4

S0 S2 S4 S0 S2

S4 S0 S2 S4

S2 S4

S0 S2 S4

D15–D0

DREQx

DACKx

DONEx

(OUTPUT)

CPU CYCLE

DMA WRITE

DMA READ

DMA WRITE

DMA READ

CPU CYCLE

DONEx

(INPUT)

Figure 6-11. Dual-Address Write Timing (External Burst–Destination Requesting)

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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