Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL 6- 17
A31–A0
FC3–FC0
SIZ1–SIZ0
R/W
AS
DS
DSACKx
S0
S2 S4 S0 S2
S4
S0
S2
S4
S0
S2 S4
S0
S2
S4
D15–D0
DREQx
DACKx
DONEx
(OUTPUT)
DMA READCPU CYCLE
NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the destination (write) DMA cycle. 4. DONEx (Input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one.
CLKOUT
CPU CYCLE
CPU CYCLE
DMA WRITE
DMA READ
DMA WRITE
S0
S2
S4
S0
S2
S4
DONEx
(INPUT)
Figure 6-12. Dual-Address Write Timing (Cycle Steal–Destination Requesting)
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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