Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL 6- 23
ADDRESS FC
CH1 CH2 15 8 7 0
780 7A0 S MODULE CONFIGURATION REGISTER (MCR)
782 7A2 S RESERVED
784 7A4 S INTERRUPT REGISTER
786 7A6 S/U RESERVED
788 7A8 S/U CHANNEL CONTROL REGISTER
78A 7AA S/U CHANNEL STATUS REGISTER FUNCTION CODE REGISTER
78C 7AC S/U SOURCE ADDRESS REGISTER MSBs
78E 7AE S/U SOURCE ADDRESS REGISTER LSBs
790 7B0 S/U DESTINATION ADDRESS REGISTER MSBs
792 7B2 S/U DESTINATION ADDRESS REGISTER LSBs
794 7B4 S/U BYTE TRANSFER COUNTER MSBs
796 7B6 S/U BYTE TRANSFER COUNTER LSBs
798 7B8 S/U RESERVED
79A 7BA S/U RESERVED
79C 7BC S/U RESERVED
79E 7BE S/U RESERVED
Figure 6-15. DMA Module Programming Model
In the registers discussed in the following paragraphs, the numbers in the upper right-
hand corner indicate the offset of the register from the base address specified by the
module base address register (MBAR) in the SIM40. The first number is the offset for
channel 1; the second number is the offset for channel 2. The numbers above the register
represent the bit position in the register. The register contains the mnemonic for the bit.
The value of these bits after a hardware reset is shown below the register. The access
privilege is shown in the lower right-hand corner.
NOTE
A CPU32 RESET instruction will not affect the MCR but will
reset all other registers in the DMA module as though a
hardware reset occurred. The term DMA is used to reference
either channel 1 or channel 2, since the two are functionally
equivalent.
6.7.1 Module Configuration Register (MCR)
The MCR controls the DMA channel configuration. Each DMA channel has an MCR. This
register can be either read or written when the channel is enabled and is in the supervisor
state. The MCR is not affected by a CPU32 RESET instruction.
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cale Semiconductor,
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