Typewriter User Manual

6- 36 MC68340 USER’S MANUAL MOTOROLA
For normal transfers aligned with the size and address, only two bus cycles are required
for each transfer: a read from the source and a write to the destination.
6.9 DMA CHANNEL INITIALIZATION SEQUENCE
The following paragraphs describe DMA channel initialization and operation. If the DMA
capability of the MC68340 is being used, the initialization steps should be performed
during the part initialization sequence. The mode operation steps should be performed to
start a DMA transfer. The
DONE≈ pin requires an external pullup resistor even if operating
only in the internal request mode.
6.9.1 DMA Channel Configuration
The following steps can be accomplished in any order when initializing the DMA channel.
These steps need to be performed for each channel used.
Module Configuration Register (MCR)
• Clear the stop bit (STP) for normal operation. (Only one STP bit exists for both
channels.)
• Select whether to respond to or ignore FREEZE (FRZx bits). (Only one set of FRZx
bits exits for both channels.)
• If desired, enable the external data bus operation in single-address mode (SE bit).
• Program the interrupt service mask to set the level below which interrupts are ignored
during a DMA transfer (ISM bits). The channel will begin operation when the level of
the CPU32 SR I2-I0 bits is less than or equal to the level of the DMA ISM bits.
• Select the access privilege for the supervisor/user registers (SUPV bit).
• Program the master arbitration ID (MAID) to establish priority on the IMB between
both DMA channels. Note that the two DMA channels should have distinct MAIDs if
both channels are being used. (If they are programmed the same, channel 1 has
priority.)
• Select the interrupt arbitration level for the DMA channel (IARB bits). (Only one set of
IARB bits exits for both channels.)
Interrupt Register (INTR)
• Program the interrupt priority level for the channel interrupt (INTL bits).
• Program the vector number for the channel interrupt (INTV bits).
Channel Control Register (CCR)
• If desired, enable the interrupt when breakpoint is recognized and the channel is the
bus master (INTB bit).
• If desired, enable the interrupt when done without an error condition (INTN bit).
• If desired, enable the interrupt when the channel encounters an error (INTE bit).
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cale Semiconductor,
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