Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL 7- 11
transmit shift register, if any, is completely sent out. If the transmitter is reset through a
software command, operation ceases immediately (refer to 7.4.1.7 Command Register
(CR)). The transmitter is re-enabled through the CR to resume operation after a disable or
software reset.
If clear-to-send operation is enabled,
CTS≈ must be asserted for the character to be
transmitted. If
CTS≈ is negated in the middle of a transmission, the character in the shift
register is transmitted, and TxDx remains in the 'mark' state until
CTS≈ is asserted again.
If the transmitter is forced to send a continuous low condition by issuing a send break
command, the state of
CTS≈ is ignored by the transmitter.
The transmitter can be programmed to automatically negate request-to-send (
RTS≈)
outputs upon completion of a message transmission. If the transmitter is programmed to
operate in this mode,
RTS≈ must be manually asserted before a message is transmitted.
In applications in which the transmitter is disabled after transmission is complete and
RTS≈ is appropriately programmed, RTS≈ is negated one bit time after the character in
the shift register is completely transmitted. The transmitter must be manually re-enabled
by reasserting
RTS≈ before the next message is to be sent.
7.3.2.2 RECEIVER. The receivers are enabled through their respective CRs located within
the serial module. Functional timing information for the receiver is shown in Figure 7-6.
The receiver looks for a high-to-low (mark-to-space) transition of the start bit on RxDx.
When a transition is detected, the state of RxDx is sampled each 16× clock for eight
clocks, starting one-half clock after the transition (asynchronous operation) or at the next
rising edge of the bit time clock (synchronous operation). If RxDx is sampled high, the
start bit is invalid, and the search for the valid start bit begins again. If RxDx is still low, a
valid start bit is assumed, and the receiver continues to sample the input at one-bit time
intervals, at the theoretical center of the bit, until the proper number of data bits and parity,
if any, is assembled and one stop bit is detected. Data on the RxDx input is sampled on
the rising edge of the programmed clock source. The least significant bit is received first.
The data is then transferred to a receiver holding register, and the RxRDY bit in the
appropriate SR is set. If the character length is less than eight bits, the most significant
unused bits in the receiver holding register are cleared.
After the stop bit is detected, the receiver immediately looks for the next start bit.
However, if a nonzero character is received without a stop bit (framing error) and RxDx
remains low for one-half of the bit period after the stop bit is sampled, the receiver
operates as if a new start bit is detected. The parity error (PE), framing error (FE), overrun
error (OE), and received break (RB) conditions (if any) set error and break flags in the
appropriate SR at the received character boundary and are valid only when the RxRDY bit
in the SR is set.
If a break condition is detected (RxDx is low for the entire character including the stop bit),
a character of all zeros is loaded into the receiver holding register, and the RB and
RxRDY bits in the SR are set. The RxDx signal must return to a high condition for at least
one-half bit time before a search for the next start bit begins.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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