Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL 7- 13
assembled in the receiver shift register and loaded into the top empty receiver holding
register position of the FIFO. Thus, data flowing from the receiver to the CPU32 is
quadruple buffered.
In addition to the data byte, three status bits, PE, FE, and RB, are appended to each data
character in the FIFO; OE is not appended. By programming the ERR bit in the channel's
mode register (MR1), status is provided in character or block modes.
The RxRDY bit in the SR is set whenever one or more characters are available to be read
by the CPU32. A read of the receiver buffer produces an output of data from the top of the
FIFO stack. After the read cycle, the data at the top of the FIFO stack and its associated
status bits are 'popped', and new data can be added at the bottom of the stack by the
receiver shift register. The FIFO-full status bit (FFULL) is set if all three stack positions are
filled with data. Either the RxRDY or FFULL bit can be selected to cause an interrupt.
In the character mode, status provided in the SR is given on a character-by-character
basis and thus applies only to the character at the top of the FIFO. In the block mode, the
status provided in the SR is the logical OR of all characters coming to the top of the FIFO
stack since the last reset error command. A continuous logical OR function of the
corresponding status bits is produced in the SR as each character reaches the top of the
FIFO stack. The block mode is useful in applications where the software overhead of
checking each character's error cannot be tolerated. In this mode, entire messages are
received, and only one data integrity check is performed at the end of the message. This
mode allows a data-reception speed advantage, but does have a disadvantage since
each character is not individually checked for error conditions by software. If an error
occurs within the message, the error is not recognized until the final check is performed,
and no indication exists as to which character in the message is at fault.
In either mode, reading the SR does not affect the FIFO. The FIFO is 'popped' only when
the receive buffer is read. The SR should be read prior to reading the receive buffer. If all
three of the FIFO's receiver holding registers are full when a new character is received,
the new character is held in the receiver shift register until a FIFO position is available. If
an additional character is received during this state, the contents of the FIFO are not
affected. However, the character previously in the receiver shift register is lost, and the OE
bit in the SR is set when the receiver detects the start bit of the new overrunning
character.
To support control flow capability, the receiver can be programmed to automatically
negate and assert
RTS≈. When in this mode, RTS≈ is automatically negated by the
receiver when a valid start bit is detected and the FIFO stack is full. When a FIFO position
becomes available,
RTS≈ is asserted by the receiver. Using this mode of operation,
overrun errors are prevented by connecting the
RTS≈ to the CTS≈ input of the
transmitting device.
If the FIFO stack contains characters and the receiver is disabled, the characters in the
FIFO can still be read by the CPU32. If the receiver is reset, the FIFO stack and all
receiver status bits, corresponding output ports, and interrupt request are reset. No
additional characters are received until the receiver is re-enabled.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...