Typewriter User Manual

7- 24 MC68340 USER’S MANUAL MOTOROLA
Table 7-3. B/Cx Control Bits
B/C1 B/C0 Bits/Character
0 0 Five Bits
0 1 Six Bits
1 0 Seven Bits
1 1 Eight Bits
7.4.1.5 STATUS REGISTER (SR). The SR indicates the status of the characters in the
FIFO and the status of the channel transmitter and receiver. This register can only be read
when the serial module is enabled (i.e., the STP bit in the MCR is cleared).
SRA, SRB $711, $719
76543210
RB FE PE OE TxEMP TxRDY FFULL RxRDY
RESET:
00000000
Read Only Supervisor/User
RB—Received Break
1 = An all-zero character of the programmed length has been received without a stop
bit. The RB bit is only valid when the RxRDY bit is set. Only a single FIFO
position is occupied when a break is received. Further entries to the FIFO are
inhibited until the channel RxDx returns to the high state for at least one-half bit
time, which is equal to two successive edges of the internal or external 1× clock
or 16 successive edges of the external 16× clock.
The received break circuit detects breaks that originate in the middle of a
received character. However, if a break begins in the middle of a character, it
must persist until the end of the next detected character time.
0 = No break has been received.
FE—Framing Error
1 = A stop bit was not detected when the corresponding data character in the FIFO
was received. The stop-bit check is made in the middle of the first stop-bit
position. The bit is valid only when the RxRDY bit is set.
0 = No framing error has occurred.
PE—Parity Error
1 = When the with parity or force parity mode is programmed in the MR1, the
corresponding character in the FIFO was received with incorrect parity. When the
multidrop mode is programmed, this bit stores the received A/D bit. This bit is
valid only when the RxRDY bit is set.
0 = No parity error has occurred.
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cale Semiconductor,
I
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