Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL 7- 31
characters until the shift register is ready to accept more data. When the shift register is
empty, it checks to see if the holding register has a valid character to be sent (TxRDY bit
cleared). If there is a valid character, the shift register loads the character and reasserts
the TxRDY bit in the channel's SR. Writes to the transmitter buffer when the channel's SR
TxRDY bit is clear and when the transmitter is disabled have no effect on the transmitter
buffer. This register can only be written when the serial module is enabled (i.e., the STP
bit in the MCR is cleared).
TBA, TBB $713, $71B
76543210
TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0
RESET:
00000000
Write Only Supervisor/User
TB7–TB0—These bits contain the character in the transmitter buffer.
7.4.1.10 INPUT PORT CHANGE REGISTER (IPCR). The IPCR shows the current state
and the change-of-state for the
CTSA and CTSB pins. This register can only be read
when the serial module is enabled (i.e., the STP bit in the MCR is cleared).
IPCR $714
76543210
0 0 COSB COSA 0 0 CTSB CTSA
RESET:
000000UU
Read Only Supervisor/User
Bits 7, 6, 3, 2—Reserved
COSB, COSA—Change-of-State
1 = A change-of-state (high-to-low or low-to-high transition), lasting longer than 25–
50
µs when using a crystal as the sampling clock or longer than one or two
periods when using SCLK, has occurred at the corresponding
CTS≈ input (MCR
ICCS bit controls selection of the sampling clock for clear-to-send operation).
When these bits are set, the ACR can be programmed to generate an interrupt to
the CPU32.
0 = The CPU32 has read the IPCR. No change-of-state has occurred. A read of the
IPCR also clears the ISR COS bit.
CTSB, CTSA—Current State
Starting two serial clock periods after reset, the
CTS≈ bits reflect the state of the CTS≈
pins. If a CTS≈ pin is detected as asserted at that time, the associated COSx bit will be
set, which will initiate an interrupt if the corresponding IECx bit of the ACR register is
enabled.
1 = The current state of the respective
CTS≈ input is negated.
0 = The current state of the respective
CTS≈ input is asserted.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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