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7- 32 MC68340 USER’S MANUAL MOTOROLA

7.4.1.11 AUXILIARY CONTROL REGISTER (ACR). The ACR selects which baud rate is

used and controls the handshake of the transmitter/receiver. This register can only be

written when the serial module is enabled (i.e., the STP bit in the MCR is cleared).

ACR $714

76543210

BRG00000IECB IECA

RESET:

00000000

Write Only Supervisor/User

BRG—Baud Rate Generator Set Select

1 = Set 2 of the available baud rates is selected.

0 = Set 1 of the available baud rates is selected. Refer to 7.4.1.6 Clock-Select

IECB, IECA—Input Enable Control

1 = ISR bit 7 will be set and an interrupt will be generated when the corresponding bit

in the IPCR (COSB or COSA) is set by an external transition on the channel's

CTS≈ input (if bit 7 of the interrupt enable register (IER) is set to enable

interrupts).

0 = Setting the corresponding bit in the IPCR has no effect on ISR bit 7.

7.4.1.12 INTERRUPT STATUS REGISTER (ISR). The ISR provides status for all potential

interrupt sources. The contents of this register are masked by the IER. If a flag in the ISR

is set and the corresponding bit in IER is also set, the

IRQ≈ output is asserted. If the

corresponding bit in the IER is cleared, the state of the bit in the ISR has no effect on the

output. This register can only be read when the serial module is enabled (i.e., the STP bit

in the MCR is cleared).

NOTE

The IER does not mask reading of the ISR. True status is

provided regardless of the contents of IER. The contents of

ISR are cleared when the serial module is reset.

ISR $715

76543210

COS DBB RxRDYB TxRDYB XTAL_

RDY

DBA RxRDYA TxRDYA

RESET:

00001000

Read Only Supervisor/User

COS—Change-of-State

1 = A change-of-state has occurred at one of the

CTS≈ inputs and has been

selected to cause an interrupt by programming bit 1 and/or bit 0 of the ACR.

0 = The CPU32 has read the IPCR.

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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