Typewriter User Manual

7- 38 MC68340 USER’S MANUAL MOTOROLA
7.4.1.17 MODE REGISTER 2 (MR2). MR2 controls some of the serial module
configuration. This register can be read or written at any time the serial module is enabled
(i.e., the STP bit in the MCR is cleared).
MR2A, MR2B $720, $721
76543210
CM1 CM0 TxRTS TxCTS SB3 SB2 SB1 SB0
RESET:
00000000
Read/Write Supervisor/User
CM1–CM0—Channel Mode
These bits select a channel mode as listed in Table 7-9. See 7.3.3 Looping Modes for
more information on the individual modes.
Table 7-9. CMx Control Bits
CM1 CM0 Mode
0 0 Normal
0 1 Automatic Echo
1 0 Local Loopback
1 1 Remote Loopback
TxRTS—Transmitter Ready-to-Send
This bit controls the negation of the
RTSA or RTSB signals. The output is normally
asserted by setting OP0 or OP1 and negated by clearing OP0 or OP1 (see 7.4.1.15
Output Port Control Register (OPCR)).
1 = In applications where the transmitter is disabled after transmission is complete,
setting this bit causes the particular OP bit to be cleared automatically one bit
time after the characters, if any, in the channel transmit shift register and the
transmitter holding register are completely transmitted, including the programmed
number of stop bits. This feature is used to automatically terminate transmission
of a message. If both the receiver and the transmitter in the same channel are
programmed for
RTS control, RTS control is disabled for both since this is an
incorrect configuration.
0 = Clearing this bit has no effect on the transmitter
RTS≈.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
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