Typewriter User Manual

8- 4 MC68340 USER’S MANUAL MOTOROLA

8.1.3 Interrupt Control Logic

Each timer provides seven interrupt request outputs (IRQ7–IRQ1) to notify the CPU32

that an interrupt has occurred. The interrupts are described in 8.4 Register Description.

Bits in the SR indicate all currently active interrupt conditions. The interrupt enable (IE)

bits in the control register (CR) are programmable to mask any events that may cause an

interrupt.

8.2 TIMER MODULES SIGNAL DEFINITIONS

This section contains a brief description of the timer module signals (see Figure 8-3).

NOTE

The terms

assertion

and

negation

are used throughout this

section to avoid confusion when dealing with a mixture of

active-low and active-high signals. The term

assert

assertion

indicates that a signal is active or true independent of the level

represented by a high or low voltage. The term

negate

negation

indicates that a signal is inactive or false.

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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