Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL 8- 9
reasserted, the timer is re-enabled and begins counting from the value attained when
TGATE≈ was negated. The SR ON bit is set again.
If
TGATE≈ is disabled (TGE = 0), TGATE≈ has no effect on the operation of the timer. In
this case, the counter begins counting on the falling edge of the counter clock immediately
after the SWR and CPE bits in the CR are set. The TG bit of the SR cannot be set. At all
times, TGL in the SR reflects the level of
TGATE≈.
If the counter counts down to the value stored in the COM register, then the COM and TC
bits in the SR are set. The counter continues counting down to timeout. At this time, the
SR TO bit is set, and the SR COM bit is cleared. The next falling edge of the counter clock
after timeout causes the value in PREL1 to be loaded back into the counter, and the
counter begins counting down from this value.
The period of the square-wave generator can be changed dynamically by writing a new
value into the PREL1. Caution must be used because, if PREL1 is accessed
simultaneously by the counting logic and a CPU32 write, the old PREL1 value may
actually get loaded into the counter at timeout.
Periodic interrupt generation can be accomplished by enabling the TO, TG, and/or TC bits
in the SR to generate interrupts by programming the CR IE bits. When enabled, the
programmed
IRQ≈ signal is asserted whenever the specified bits are set.
8.3.3 Variable Duty-Cycle Square-Wave Generator
In this mode, both the PREL1 and PREL2 registers are used to generate a square wave
with virtually any duty cycle. The square wave is generated by counting down from the
value in the PREL1 to timeout (count value $0000), then loading that value from PREL2
and again counting down to timeout. When this second timeout occurs, the value from
PREL1 is loaded into the counter, and the cycle repeats. TOUTx can be programmed to
change state with every timeout, thus generating a variable duty-cycle square wave. This
mode can be selected by programming the MODE bits in the CR to 010.
The timer is enabled by setting both the SWR and CPE bits in the CR and, if
TGATE≈ is
enabled (CR TGE bit is set), then asserting
TGATE≈. When the timer is enabled, the ON
bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded
with the value stored in the PREL1 register (N1). With each successive falling edge of the
counter clock, the counter decrements. The time between enabling the timer and the first
timeout can range from N1 to N1+1 periods. When
TGATE≈ is used to enable the timer,
the enabling of the timer is asynchronous; however, if timing is carefully considered, the
time to the first timeout can be known. For additional details on timing, see the Section 11
Electrical Characteristics.
If the counter counts down to the value stored in the COM register, the COM and timer
compare interrupt (TC) bits in the SR are set. The counter continues counting down to
timeout. At this time, the TO bit in the SR is set, and the COM bit is cleared. The next
falling edge of the counter clock after timeout causes the value in PREL2 (N2) to be
loaded into the counter, and the counter begins counting down from this value. Each
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