Typewriter User Manual

8- 24 MC68340 USER’S MANUAL MOTOROLA
TO—Timeout Interrupt
1 = The counter has transitioned from $0001 to $0000, and the counter has rolled
over. This bit does not affect the programmed
IRQ≈ signal if the IE2 bit in the CR
is cleared.
0 = This bit is cleared by the timer whenever the
RESET signal is asserted on the
IMB, regardless of the mode of operation. This bit may also be cleared by writing
a one to it. Writing a zero to this bit does not alter its contents. This bit is not
affected by disabling the timer (SWR = 0).
TG—Timer Gate Interrupt
1 = This bit is set whenever the CR TGE bit is set and the
TGATE≈ signal
transitions in the manner to which the particular mode of operation responds.
Refer to 8.3 Operating Modes for more details. This bit does not affect the
programmed
IRQ≈ signal if the IE1 bit in the CR is cleared.
0 = This bit is cleared by the timer whenever the
RESET signal is asserted on the
IMB, regardless of the mode of operation. This bit may also be cleared by writing
a one to it. Writing a zero to this bit does not alter its contents. This bit is not
affected by disabling the timer (SWR = 0).
TC—Timer Compare Interrupt
1 = This bit is set when the counter transitions (off a clock/event falling edge) to the
value in the COM. This bit does not affect the programmed
IRQ≈ signal if the IE0
bit in the CR is cleared.
0 = This bit is cleared by the timer whenever the
RESET signal is asserted on the
IMB, regardless of the mode of operation. This bit may also be cleared by writing
a one to it. Writing a zero to this bit does not alter its contents. This bit is not
affected by disabling the timer (SWR = 0).
TGL—
TGATE≈ Level
1 = The
TGATE≈ signal is negated.
0 = The
TGATE≈ signal is asserted.
ON—Counter Enabled
1 = This bit is set whenever the SWR and CPE bits are set in the CR. If the CR TGE
bit is set,
TGATE≈ must also be asserted (except in the input capture/output
compare mode) since this signal then controls the enabling and disabling of the
counter. If all these conditions are met, the counter is enabled and begins
counting down.
0 = The counter is not enabled and does not begin counting down.
OUT—Output Level
1 = TOUTx is a logic one.
0 = TOUTx is a logic zero, or the pin is three-stated.
COM—Compare Bit
This bit is used to indicate when the counter output value is at or between the value in
the COM and $0000 (timeout).
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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