Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL Index-3
DBF Bit, 4-6, 4-23
DBFE Bit, 4-6, 4-25, 4-37
DD Bits, 4-14, 4-17, 4-32
Destination Address Register, 6-15, 6-18–6-19, 6-28,
6-33–6-34, 6-37–6-38
Deterministic Opcode Tracking, 5-64, 5-87–5-88
DFC Bits, 6-32
Differences between MC68020 Instruction Set and
MC68340 Instruction Set, 5-5
DIV Instructions,
DMA
Acknowledge Signals, 2-10, 6-4–6-7, 6-10, 6-12,
6-15
Capabilities, 6-1
Channel
Initialization, 6-18–6-19, 6-36
Operation Sequence, 6-18–6-21
Termination, 6-18, 6-20–6-21
Done Signals, 2-10, 6-4, 6-7, 6-10, 6-12, 6-15
Programming Model, 6-23
Programming Sequence, 6-18
Request Signals, 2-10, 6-4–6-7, 6-18–6-19, 6-21
Timing
Single-Address Read (External Burst), 6-8
Single-Address Read (Cycle Steal), 6-9
Single-Address Write (External Burst), 6-10
Single-Address Write (Cycle Steal), 6-11
Dual-Address Read (External Burst—Source
Requesting), 6-13
Dual-Address Read (Cycle Steal—Source
Requesting), 6-14
Dual-Address Write (External Burst—Destination
Requesting), 6-16
Dual-Address Write (Cycle Steal—Destination
Requesting), 6-17
Fast Termination (Cycle Steal), 6-21
Fast Termination (External Burst Source
Requesting), 6-22
Transfer Type, 3-5
Transfers, Control of Bus, 6-6, 6-18
Transfers, 32 Bits, 6-2, 6-7, 6-35
Documentation, 1-10
DONE Bit, 6-15, 6-20, 6-27, 6-31, 6-37–6-38, 6-30
Double Bus Fault, 3-39, 3-41, 5-43, 5-66
Monitor, 3-40, 4-1, 4-4, 4-6, 4-23, 4-37
DSACK
Encoding, 3-5
Signals, 4-2, 4-4, 4-6, 4-14, 4-32, 10-5
DSCLK Signal, 5-69–5-71
DSI Signal, 5-69, 5-71
DSIZE Bits, 6-15, 6-29, 6-37
DSO Signal, 5-69, 5-71
Dual-Address
Destination Write, 6-15
Mode, 6-12, 6-28, 6-37
Source Read, 6-12
Transfer, 6-3
Dump Memory Block Command, 5-80–5-81
Dynamic Bus Sizing, 3-5, 3-14
— E —
Early Bus Error, 3-34
EBI, 4-2, 4-22, 4-33
ECO Bit, 6-7, 6-27–6-28, 6-37
Effects of Wait States on Instruction Timing, 5-92
Electrical Characteristics, 11-1
AC Electrical Specifications
Definitions, 11-2, 11-4
Control Timing, 11-6–11-7
Timing Specifications, 11-8–11-10
Timing Diagram, 11-11–11-18
DMA Module Specifications, 11-19
DMA Timing Diagram, 11-19
Timer Module Specifications, 11-20
Timer Module Timing Diagrams, 11-20–11-21
Serial Module Specifications, 11-22
Serial Module Timing Diagrams, 11-22–11-23
IEEE 1149.1 Specifications, 11-24
IEEE 1149.1 Timing Diagrams, 11-24–11-25
Typical Characteristics, 10-11
DC Electrical Specifications, 11-5
ERR Bit, 7-13, 7-23, 7-47
Error Status, Serial, 7-13
Event Counting, 8-14–8-15
Exception
Handler, 5-42, 5-51, 5-57, 5-59, 5-56
Priorities, 5-41–5-42
Processing, 3-32, 5-4, 5-38, 5-61
Faults, 5-54–5-59
Sequence, 5-40–5-41
State, 5-7, 5-38, 5-40–5-41
Stack Frame, 5-4,
Vectors, 5-39–5-40
Exception-Related Instructions and Operands Timing
Table, 5-112
EXTAL Pin, 2-9, 4-7, 4-9–4-11, 10-21
External
Bus Interface, 4-2
Bus Master, 3-4, 3-16, 3-40–3-44, 4-6
DMA Request, 6-2, 6-5–6-6, 6-19–6-20, 6-29–6-30
Exceptions, 5-40
Reset, 10-3
— F —
F-Line Instructions, 5-47
Fast Termination Timing, 3-15
Operation, 3-4, 3-15, 4-14, 4-30, 4-33
DMA Transfers, 6-20
Fault
Address Register, 5-67
Correction, 5-57–5-59
Recovery, 5-52
Types, 5-54–5-55, 5-57–5-59, 5-83–5-86
FC Bits, 4-2
FCM Bits, 4-32
FE Bit, 7-13, 7-24, 7-28
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cale Semiconductor,
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