Typewriter User Manual

MOTOROLA MC68340 USER’S MANUAL 3- 33
EXAMPLE B: A system uses error detection and correction on RAM contents. The
designer may:
1. Delay DSACK≈ until data is verified and assert BERR and HALT simultaneously to
indicate to the MC68340 to automatically retry the error cycle (case 5), or if data is
valid, assert
DSACK≈ (case 1).
2. Delay
DSACK≈ until data is verified and assert BERR with or without DSACK≈ if
data is in error (case 3). This initiates exception processing for software handling of
the condition.
3. Return
DSACK≈ prior to data verification; if data is invalid, BERR is asserted on the
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.
4. Return
DSACK≈ prior to data verification; if data is invalid, assert BERR and HALT
on the next clock cycle (case 6). The memory controller can then correct the RAM
prior to or during the automatic retry.
Table 3-4. DSACK≈, BERR, and HALT Assertion Results
Asserted on Rising
Edge of State
Case
Num
Control
Signal N N + 2 Result
1 DSACK≈
BERR
HALT
A
NA
NA
S
NA
X
Normal cycle terminate and continue.
2 DSACK≈
BERR
HALT
A
NA
A/S
S
NA
S
Normal cycle terminate and halt; continue
when
HALT negated.
3 DSACK≈
BERR
HALT
NA/A
A
NA
X
S
X
Terminate and take bus error exception,
possibly deferred.
4 DSACK≈
BERR
HALT
A
NA
NA
X
A
NA
Terminate and take bus error exception,
possibly deferred.
5 DSACK≈
BERR
HALT
NA/A
A
A/S
X
S
S
Terminate and retry when
HALT negated.
6 DSACK≈
BERR
HALT
A
NA
NA
X
A
A
Terminate and retry when
HALT negated.
NOTES:
N — Number of the current even bus state (e.g., S2, S4, etc.)
A — Signal is asserted in this bus state
NA — Signal is not asserted in this state
X — Don't care
S — Signal was asserted in previous state and remains asserted in this state
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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