User Manual Pluto 5 Controller Document No. 80-15151 Issue 6 HEBER LTD nd September 2005 Current Issue :- Issue 6 – 2 Previous Issue :- Issue 5r1 – 14 May 2004 th ©HEBER Ltd. 2005. This document and the information contained therein is the intellectual property of HEBER Ltd and must not be disclosed to a third party without consent. Copies may be made only if they are in full and unmodified. File Name: H:\pluto5\manuals\pluto_5_controller.doc Document No.
HEBER LTD Belvedere Mill Chalford Stroud Gloucestershire GL6 8NT England Tel: +44 (0) 1453 886000 Fax: +44 (0) 1453 885013 Email: support@heber.co.uk http://www.heber.co.uk File Name: H:\pluto5\manuals\pluto_5_controller.doc Document No.
Page i CONTENTS 1 INTRODUCTION.................................................................................................................... 1 2 NEW IN THIS RELEASE ....................................................................................................... 1 3 OVERVIEW ............................................................................................................................ 1 4 CIRCUIT SCHEMATIC DESCRIPTION ........................................................
Page ii 6 MACHINE OPERATION ...................................................................................................... 20 6.1 DRIVING REELS ...................................................................................................................... 20 6.2 READING THE DIL SWITCHES .................................................................................................. 20 6.3 READING THE SWITCH INPUTS ............................................................................
Page iii LIST OF TABLES Table 1. Allocation of MC68340 Pins Controlled by SIM40 Module........................................................ 7 Table 2. Allocation of MC68340 Pins Controlled by DMA Module .......................................................... 8 Table 3. Allocation of MC68340 Pins Controlled by Serial Module......................................................... 9 Table 4. Allocation of MC68340 Pins Controlled by Timer Module.........................................................
Page 1 1 INTRODUCTION The Pluto 5 Controller board is a natural progression in the Pluto family of products. It builds on the proven reliability and technical excellence of previous Pluto boards and provides improved performance and flexibility at lower cost. This manual covers the detail of the hardware operation of Pluto 5 Controller board, other boards in the system have their own manuals. 2 NEW IN THIS RELEASE • Section 6.9 has revised audio information.
Page 2 4 CIRCUIT SCHEMATIC DESCRIPTION This section is a walk through of the Pluto 5 Controller board (56-14084) circuit schematics, Figures 1-13 of this document. A detailed description is given in Section 5 “CIRCUIT OPERATION”. 4.1 Sheet 1 This sheet shows the interconnection between the remaining sheets of this drawing. 4.2 Sheet 2 This sheet shows the following items: • • • • 4.3 Motorola MC68340 Processor. Pull-up resistors on Address Bus, Data Bus and other Control Signals.
Page 3 4.8 Sheet 8 This sheet shows various Power Supply related functions: • • • • • • 4.9 Current sensing +12V Meter supply Power fail detection. Current sensing from Lamp Multiplex. Fuse and +5V regulator. Voltage rail overvoltage and transient protection. P3 “PWR IN” power input connector Sheet 9 This sheet shows the following I/O connectors. • • • • • • P7 “REELS” carries enough I/O lines to run 6 reels, including a sub set of the lamp multiplexer and power supplies for the motors.
Page 4 5 CIRCUIT OPERATION This section describes how some elements of the circuit operate and their capabilities and limitations. A subsequent section deals with how the various capabilities of the board are used to implement specific amusement machine functions. 5.1 Power Supplies The Power Input to the board is on P3. There are 3 input voltages required, +12V, -12V and 36V or 48V for the lamp multiplex. The +12V supply is fused by F1 (3.15A) as it comes on the board.
Page 5 processor the NMI in advance of the RESET is to avoid the risk of an incomplete RAM write operation occurring if the RESET were to be asynchronously asserted while such an operation was being carried out. The time available between the assertion of NMI and the assertion of RESET will depend on the rate of fall of the +12V line, which will obviously be dependent upon the power supply and the loading on the +12V, but will typically be several milliseconds. 5.
Page 6 5.4.1 CPU32 Processor Module The CPU32 is a processing core which is basically 68000 code compatible but with a number of enhancements. For full details of operation please refer to both the Motorola MC68340 User Manual and the Motorola M68000 Family Programmers Reference Manual [see Adobe Acrobat File 68kprm.pdf]. All modern 68000 Compilers and Assemblers have various options for the target CPU. When generating code for the Pluto System, the CPU32 option should be used.
Page 7 5.4.2.4 Clock Synthesiser Control The SYNCR controls the operation of the main processor clock. The MC68340 is provided with a 32.768KHz reference to which the main clock is phase locked. After reset, the main clock defaults to 8.39MHz. The maximum clock frequency of the standard MC68340 is 16.77MHz. 5.4.2.5 System Protection The SYPCR controls the bus monitors and software watchdog. Other safeguards in the design give adequate protection against programme malfunction as a result of noise, etc.
Page 8 5.4.3 DMA Controller Module The DMA Module provides 2 DMA Channels. On the Pluto 5 these are used for sending sound data from the Programme Memory to the OKI MSM6585 Sound Chip(s). DMA Channel 1 is used to send data to Sound Channel #1, which is fitted as standard to the Pluto 5 Board. DMA Channel 2 is used for the optional add-on Sound Channel #2 if fitted (IC39).
Page 9 Pins controlled by the Serial module are allocated as follows: Table 3. Allocation of MC68340 Pins Controlled by Serial Module PIN RXDA NO. 33 I/O I TXDA 32 O RXDB TXDB OP0/RTSA- 25 24 29 I O O OP1/RTSBOP4/RXRDYAOP6/TXRDYACTSA- 23 27 26 28 O O O I CTSB- 22 I 5.4.
Page 10 5.5 FPGA The Pluto 5 Controller is fitted with an 84 lead PLCC socket, position U6, into which is plugged an FPGA. The standard FPGA type used is an Actel A40MX04-PL84. The purpose of fitting an FPGA to the system is twofold. First, to allow the Pluto 5 Controller to be uniquely configured for each user of the system to give commercial and software security (see the FPGA SECURITY MANUAL).
Page 11 Note that this scrambling of address lines is applicable ONLY to sockets U1 and U2 on the Pluto 5 Controller Board. Any EPROM sockets on Memory Expansion Cards are connected 1:1 to the address bus and do NOT require any special processing. 5.7 5.7.1 EPROM Address Line Scrambling in 16 Bit Mode 2*27C040 EPROMs In 16 bit mode, running with 2 * 27C040 EPROMs, the scrambling of the address lines cause the following effect on the memory mapping in the EPROMs.
Page 12 Thus, for example, addresses will be translated as follows so the contents of the EPROM must be rearranged to compensate: Table 9.
Page 13 5.8 Memory Expansion Various optional memory cards may be fitted to the Memory Expansion Connector P15. Seven lines from the FPGA are included along with 16 data lines and 21 address lines. The default functionality of the FPGA lines allows memory cards fitted with up to 4 EPROM or FLASH devices to be accommodated along with a pair of RAM devices with no additional mapping components. If a memory card is fitted with 5V FLASH devices, then Write facilities are available.
Page 14 5.10 AUX Outputs, AUX0-7 8 auxiliary TTL level open drain outputs are provided by U30 (see Schematic Sheet 9 - IO Connectors). U30 is a TPIC6B259 which functions exactly the same as the TPIC6259 devices used to drive OP0-63, but with a lower drive capability (see data sheet “tpic6b259.pdf”). They are memory mapped as the least significant bit of a block of 8 bytes of address space at an address determined by the FPGA fitted to the board. See the appropriate FPGA User Manual for details.
Page 15 5.12 DIL Switches The Pluto 5 board is equipped with two 8 way DIL Switches, SW1 and SW2. These are read at the same addresses as the 32 Inputs (see preceding Section). Table 12. Mapping of DIL Switch Inputs D15-D12 Base+6 Base+4 Base+2 Base 0xF 0xF 0xF 0xF D11 SW2:8 SW2:6 SW2:4 SW2:2 D10 SW2:7 SW2:5 SW2:3 SW2:1 D9 SW1:8 SW1:6 SW1:4 SW1:2 D8 SW1:7 SW1:5 SW1:3 SW1:1 D7-D0 IP31-24 IP23-16 IP15-8 IP7-0 5.
Page 16 The Pluto 5 128/16 Controller Board is intended for users who require less drive capability or who wish to run the lamps at 36V. It has ¼ of MPX1 configured as a 16*8 (128) Lamp Drive Array and the other ¼ configured as a 16*8 (16 seven-segment digits) LED Drive Array. The other 32*16 Multiplex Array (MPX2) is utilised by adding external low-cost Pluto 5 Multiplex Expansion Boards, wired to Connector P11. Each board only requires 5 signal wires from P11 plus Power Supplies.
Page 17 5.16 Multiplexed Lamp Current Sense A facility is provided to allow the processor to check the 256/128 possible lamp positions of MPX1 to determine: a. b. Is a light bulb present? Is there a short circuit in this position? This facility is intended to be run at power up and, perhaps, as a production test. The facility cannot be used during normal operation of the machine.
Page 18 5.17 Sound Generation The sound generation circuits are shown on Schematic Sheet 5 - Sound. U8 and (optionally) U39 are the source of Sound Channel 1 & 2 respectively with the audio output being pin 10, Aout. These OKI MSM6585 devices are 4 bit ADPCM D-A converters capable of running at sample rates of 4KHz, 8KHz, 16KHz or 32KHz. This rate is selected by software by setting levels on the S1 and S2 pins.
Page 19 of operation, for example, if only Sound Channel 1 is fitted, then by linking the LS1+ output to the feedback pin, the same signal can drive BOTH loudspeakers. See Section 6.9, “Making Sounds” below for a more detailed explanation of the different operational modes that are possible. 5.19 Serial I/O P1 provides connections to RS232 Channel A, Data Receive & Transmit plus RTS/CTS.
Page 20 6 MACHINE OPERATION This section discusses how various standard amusement machine functions can be implemented. 6.1 Driving Reels Up to six 12V Stepper Motor Reel Mechanisms may be connected to the “REEL” connector, P7. +12V outputs are available for the motor common connection and GND/Vcc are available for the Opto supply.
Page 21 6.4 Interfacing to Coin & Note Acceptors Most Coin or Note Acceptors have open collector (“sink to ground”) outputs. These may be connected directly to any of the Pluto 5 Inputs (IP0-31). Mechanism “Enable” or “Control” inputs may usually be driven directly from any of the Pluto 5 Open Drain Output lines (OP0-63). 6.5 Interfacing to Coin Payout Mechanisms Payout Hoppers that require relatively low drive currents, e.g.
Page 22 It is possible to run the sound in the following modes: 6.9.1 Single Channel/Single Speaker (Mono) Mode This is the lowest cost option, using the standard Pluto 5 Board with a single loudspeaker. The optional SFX Channel 2, U39, is not fitted and only SFX Channel 1, U8, is operational. A single loudspeaker is connected to LS1 pins (1 & 2) only. Pins 3,4,5 should be left open. 6.9.
Page 23 connected to a digit drive output, DIG0-15, on connector P5. Each digit drive output can drive two 7 Segment Digits, the segment anodes for one connecting to drive SEG0-7 and the other to SEG8-15. By convention, segment “a” would connect to SEG0 or SEG8. Alternatively, 14 segment starburst digits can be used, in which case each digit output would drive one digit and the 14 segment anodes should each be connected to one of the segment drive lines, SEG013.
Page 24 7 SOFTWARE DEVELOPMENT A number of options exist for the development and debug of software for use on Pluto 5. Software will normally be generated using a Cross Assembler, Cross Compiler and Linker package. A suitable package is included with the Pluto 5 Development Kit. When software has been successfully compiled, assembled and linked, it may be tested and debugged using the Background Debug Mode facility built in to the 68340 Processor.
Page 25 8 CONNECTOR TYPES AND PIN OUTS 8.1 Schedule of Connector Types There are two types of Pluto 5 Board with either Ultrex or Box Header connectors, and 3 other families of connectors: • • Pluto 5 with Ultrex connectors is referred to as Pluto 5U Pluto 5 with Box Header connectors is referred to as Pluto 5B Pluto 5U uses the following 4 different families of connectors for connection to the cableform in the machine: • • • • AMPMTA-100. 2.
Page 26 Table 18. AMP MTA-100 Connector Part Numbers Ident P1 P4 P6 P10 P11 P12 P13 Description PCB Header AMP Part No. 6W MTA-100 18W MTA-100 16W MTA-100 5W MTA-100 7W MTA-100 8W MTA-100 4W MTA-100 AMP IDC Connector Part Number 2 2 24 AWG (0.22mm ) (Colour Natural) 22 AWG Wire(0.
Page 27 8.3 P2 – Dataport (RS232 Channel B) Reference: Type: Description: 8.
Page 28 8.
Page 29 8.7 P5 Box Header – Multiplexed LEDs Reference: Type: Description: P5 Header 34W Tyco Box Header LED - Drive for 16 or 32 seven-segment LED Digits.
Page 30 8.9 P7 Ultrex – Reels Reference: Type: Description: P7 Header 50W AMP Ultrex Reels - Connector for 6 Stepper Motor Reel Mechanisms Lamp Column 0 Lamp Column 2 Lamp Column 4 Lamp Row 0 Lamp Row 2 Lamp Row 4 Open Drain Output 0 Open Drain Output 2 Open Drain Output 4 Open Drain Output 6 Open Drain Output 8 Open Drain Output 10 Open Drain Output 12 Open Drain Output 14 Open Drain Output 16 Open Drain Output 18 Open Drain Output 20 Open Drain Output 22 Input 0 Input 2 Input 4 Document No.
Page 31 8.10 P7 Box Header – Reels Reference: Type: Description: P7 Header 50W Box Header Reels - Connector for 6 Stepper Motor Reel Mechanisms Lamp Column 0 Lamp Column 2 Lamp Column 4 Lamp Row 0 Lamp Row 2 Lamp Row 4 Open Drain Output 0 Open Drain Output 2 Open Drain Output 4 Open Drain Output 6 Open Drain Output 8 Open Drain Output 10 Open Drain Output 12 Open Drain Output 14 Open Drain Output 16 Open Drain Output 18 Open Drain Output 20 Open Drain Output 22 Input 0 Input 2 Input 4 Document No.
Page 32 8.11 P8 Ultrex – General I/O #1 Reference: Type: Description: P8 Header 40W AMP Ultrex General Purpose I/O #1 Open Drain Output 24 Open Drain Output 26 Open Drain Output 28 Open Drain Output 30 Open Drain Output 32 Open Drain Output 34 Open Drain Output 36 Open Drain Output 38 Open Drain Output 40 Open Drain Output 42 Open Drain Output 44 Open Drain Output 46 Input 20 Input 22 Input 24 Input 26 Input 28 Input 30 Document No.
Page 33 8.12 P8 Box Header – General I/O #1 Reference: Type: Description: P8 Header 40W Box Header General Purpose I/O #1 Open Drain Output 24 Open Drain Output 26 Open Drain Output 28 Open Drain Output 30 Open Drain Output 32 Open Drain Output 34 Open Drain Output 36 Open Drain Output 38 Open Drain Output 40 Open Drain Output 42 Open Drain Output 44 Open Drain Output 46 Input 20 Input 22 Input 24 Input 26 Input 28 Input 30 Document No.
Page 34 8.
Page 35 8.15 P10 – Loudspeakers Reference: Type: Description: P10 Header 5W AMP MTA-100 Loudspeakers 1 2 3 4 5 LS1+ LS1MIX LS2+ LS2- Loudspeaker, Channel 1 Loudspeaker, Channel 1 Channel 2 mixer input Loudspeaker, Channel 2 Loudspeaker, Channel 2 WARNING: Loudspeaker outputs are bridge driven and must NOT be connected ground. 8.
Page 36 8.18 P13 – External I2C Bus Reference: Type: Description: P13 Header 4W AMP MTA-100 2 External I C Bus 1 2 3 4 GND AUX7/SDA AUX6/SCL +5V I2C SDA line, TTL Open Collector I/O, 1K Pull-up I2C SCL line, TTL Open Collector I/O, 1K Pull-up 8.
Page 37 8.20 P15 – Memory Expansion Card Connector Reference: Type: Description: P15 DIN41612, C/2 Socket Vertical Connector for Memory Expansion Boards a A4 VCC VCC A3 A2 A1 GND GND FPGA0 FPGA1 FPGA2 FPGA3 FPGA4 FPGA5 FPGA6 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 b A5 A7 A9 A11 A13 A15 A17 A19 A21 D14 D12 D10 D8 D6 D1 D2 c A6 A8 A10 A12 A14 A16 A18 A20* D15 D13 D11 D9 D7 D5 D3 D4 * NB.
Page 38 Figure 1 - Schematic Sheet 1 - Root Sheet SHT 6 - OPEN DRA IN OUTPUTS RESETCS_OPD[0..15] SHT 8 - +5V /CURRENT SENSE A[0..23] SHT 9 - CONNECTORS RESETCS_OPOP[0..63] D[0..15] OP[0..63] A [0..23] IP[0..31] 15084_6 METER_SENSE V REF NMIMPX_REF2 MPX_REF1 PORTA [0..7] SFX_CLK SHT 2 - MC68340 CPU R/WSIZ0 DSA CK0EXTA L 3.68MHZ CS0CS1CS2CS3CLKOUT DREQ1DREQ2- D[0..15] DSA CK1SIZ1 A [0..2 3] METER_SENSE NMI- R/WSIZ0 DSACK0 EXTA L 3.68MHZ CS0CS1CS2CS3CLKOUT DREQ1DREQ2- RESET D[0 ..
Page 39 Figure 2 - Schematic Sheet 2 - CPU N7 BACKGRO UND DEBUG CONNECT OR TCK TMS TDI TDO PP PP PP PP IEEE 11 49.
Page 40 Figure 3 - Schematic Sheet 3 - FPGA 2 R/W2,9 DSACK0 2 SIZ0 10 2 2 2 2 CS_OP- 6 CS_IP- 7 RESET RA M_WL- 4 RA M_WU- 4 RA M_OE- 4 CS0CS1CS2CS3- 2,4,6,7,9 D[0..15] ROM_OE- 4 ROM_P1 4 D[0..15] D8 D9 D10 D11 D12 FPGA [0..6] GND V CC U6 N14 FPGA 0 FPGA 1 FPGA 2 FPGA 3 FPGA 4 FPGA 5 FPGA 6 I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 D13 2 A [0..23] A [0..
Page 41 Figure 4 - Schematic Sheet 4 - Memory VBATT A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 3 3 ROM_ P1 ROM_ OE- ROM_P1 ROM_OE- GND 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 31 1 24 22 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 D0 D1 D2 D3 D4 D5 D6 D7 13 14 15 17 18 19 20 21 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 V CC C21 100n GND VCC V PP OE CE GND 32 V CC 16 GND
Page 42 Figure 5 - Schematic Sheet 5 - Sound SAMPLED SOUND CHANNEL #1 SAMPLED SOUND CHANNEL #2 V CC V CC C40 C39 GND POP4 POP6 SFX1_S1 SFX1_S2 POP4 POP6 1 2 PORTA 0 3 15 SFX_CLK SFX_CLK 16 17 S1 S2 T1 T2 T3 T4 DA O 12 13 3 8 PORTA [0..7] 2,8,9,10 PORTA [0..
Page 43 Figure 6 - Schematic Sheet 6 - Outputs OP[0..63] D0 18 SEL0 SEL1 SEL2 3 8 12 13 19 V CC 2 GND 9 U22 D S0 S1 S2 G CLR V CC GND Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PGND PGND PGND PGND OP56 OP48 OP40 OP32 OP24 OP16 OP8 OP0 4 5 6 7 14 15 16 17 1 10 11 20 D4 OP[0..63] 9 18 SEL0 SEL1 SEL2 3 8 12 13 19 GND GND GND GND V CC 2 GND 9 TPIC6259 2 A[0..23] A[0..
Page 44 Figure 7 - Schematic Sheet 7 - Inputs IP[0..31] IP[0..31] 9 D[0 ..
Page 45 Figure 8 - Schematic Sheet 8 - Power Supply +12V D1 UF4002 1 3 LC1 EMC FILTER 2 V METER+ +12V METER DETECTION R33 47R POWER FAIL DETECTION V CC GND R37 47K 2% +12V R38 47K 2% R39 47K 2% R40 revisions: 3k3 -> 10k Feb 1998 10k -> 4k7 Jul 2003 R40 4K7 2 1 NMI- + - + 2 12 - PP13 7 PP 6 V REF 10 R34 22K LM339 U16A 3 METER_SENSE 2 METER_SENSE R35 47K 2% U16B PP8 5 R36 4 PP9 GND PP LM339 47K 2% PP10 PP PP GND V CC R124 47K 2% PORTA[0..7] 2,5,9,10 PORTA [0..
Page 46 Figure 9 - Schematic Sheet 9 – IO Connectors Heber L td. 1999 I/O 1 IP20 IP22 IP24 IP26 IP28 IP30 +12V B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 OP25 OP27 OP29 OP31 OP33 OP35 OP37 OP39 OP41 OP43 OP45 OP47 V CC 1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 12 LR[0..15] LR[0..15] GND IP21 IP23 IP25 IP27 IP29 IP31 11 LC[0..15] LC[0..
Page 47 Figure 10 - Schematic Sheet 10 - Reset/Battery/RS232 BATTERY BACK-UP SM Q2 FMMT717 VBATT R42 3K3 TP14 PA D +12V PP18 BT1 2.
Page 48 Figure 11 - Schematic Sheet 11 - Lamp Column/LED Digit Drives 1 GND LC[0..
Page 49 Figure 12 - Schematic Sheet 12 - Lamp Row Drives 1 V MPX+ 2 3 4 5 6 7 8 9 N5 3K3*8 SIL GND 1 2 3 15 13 STR_12V 13 MPX1_A _12V 13 CLK_12V 13 OE_12V +12V 16 GND 8 U18 STR D CLK OE VDD GND Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 QS QS R85 4 5 6 7 14 13 12 11 3K3 R81 3K3 R84 R83 3K3 R80 3K3 R79 3K3 3K3 9 10 R82 Q11 22K R55 BC846 Q12 22K R56 Q19 TIP126 GND 3K3 GND BC846 Q13 4094 Q20 TIP126 22K R58 Q21 TIP126 BC846 Q15 22K R59 BC846 Q16 22K R60 BC846 Q17 22K R61 BC846 Q18 22K Q22
Page 50 Figure 13 - Schematic Sheet 13 - LED Segment Drives U34 3 5 7 9 11 14 3 MPX_OE 3 MPX_CLK 3 MPX_STR 3 MPX1_DA TA_A 3 MPX2_DA TA_A 3 MPX_STR_DATA_ A VCC 13 VCC 1 AI BI CI DI EI FI AO BO CO DO EO FO MODE V DD V CC GND OE_12V CLK_12V STR_12V MPX1_A _12V MPX2_A _12V STR_A _12V 2 4 6 10 12 15 16 +12V 8 GND OE_12V 11,12 CLK_12V 11,12 STR_12V 11,12 MPX1_A _12V 12 R62 +12V Q51 BC337 STR_A_12V 11 150R R63 Q52 BC337 4504 1 2 3 15 12 MPX1_B_12V +12V 16 GND 8 150R R64 Q53 BC337 U3
Page 51 Figure 14 - Pluto 5 Component Ident Document No.
Page 52 Figure 15 - Photograph of Pluto 5 with Ultrex Connectors (Pluto 5U) Document No.
