October 24, 1996 CSIC MCU Design Center Austin, Texas A G R E E M E N T General Release Specification N O N - D I S C L O S U R E MC68HC05RC8 MC68HC05RC16 R E Q U I R E D HC05RC16GRS/D REV. 3.
A G R E E M E N T R E Q U I R E D General Release Specification N O N - D I S C L O S U R E Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
General Release Specification — MC68HC05RC16 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . 15 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Section 3. Central Processor Unit . . . . . . . . . . . . . . . . . 33 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Section 6. Low-Power Modes . . . . . . . . . . . . . . . . . .
List of Sections General Release Specification 4 MC68HC05RC16 — Rev. 3.
General Release Specification — MC68HC05RC16 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.4 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.
Table of Contents Section 3. Central Processor Unit 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.4 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.5 Condition Code Register. . . . . . . . . . . . . . . . .
Table of Contents 5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.5.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.5.2 Computer Operating Properly Reset (COPR) . . . . . . . . . . .49 5.5.2.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.5.2.2 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.5.2.3 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . .
Table of Contents Section 8. Core Timer 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 8.3 Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .63 8.4 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .65 8.5 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .66 8.
Table of Contents Section 10. Instruction Set 10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 10.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 10.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 10.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents Section 12. Mechanical Specifications 12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.3 28-Pin Plastic Dual In-Line Package (Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.4 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Release Specification — MC68HC05RC16 List of Figures Figure Title 1-1 1-2 1-3 1-4 1-5 MC68HC05RC16 Block Diagram . . . . . . . . . . . . . . . . . . . . .18 28-Pin DIP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 28-Pin SOIC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 44-Pin PLCC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure Title 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 Carrier Modulator Transmitter Module Block Diagram . . . . .69 Carrier Generator Block Diagram . . . . . . . . . . . . . . . . . . . . .70 Carrier Generator Data Register CHR1 . . . . . . . . . . . . . . . .72 Carrier Generator Data Register CLR1 . . . . . . . . . . . . . . . .72 Carrier Generator Data Register CHR2 . . . . . . . . . . . . . . . .72 Carrier Generator Data Register CLR2 . . . . . . . . . . . . . . . .
General Release Specification — MC68HC05RC16 List of Tables Table Title 4-1 Vector Address for Interrupts and Reset ................................38 5-1 COP Watchdog Timer Recommendations .............................50 7-1 I/O Pin Functions ....................................................................59 8-1 RTI and COP Rates at 4.096 MHz Oscillator .........................64 10-1 10-2 10-3 10-4 10-5 10-6 10-7 Register/Memory Instructions...............................................
List of Tables General Release Specification 14 MC68HC05RC16 — Rev. 3.
General Release Specification — MC68HC05RC16 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.4 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.1 VDD and VSS . . . . .
General Description 1.2 Introduction The MC68HC05RC16 is a low-cost addition to the M68HC05 Family of microcontrollers (MCUs) and is suitable for remote control applications. This device contains the HC05 central processing unit (CPU) core, including the 14-stage core timer with real-time interrupt (RTI) and computer operating properly (COP) watchdog systems. On-chip peripherals include a carrier modulator transmitter. The 16-kbyte memory map has 15,936 bytes of user ROM and 352 bytes of RAM.
General Description Features • Low-Power Reset Pin • 20 Bidirectional I/O Lines (Four Additional I/O Lines Available for Bond Out in 44-Lead PLCC Package) • Mask Programmable Pullups and Interrupts on Eight Port Pins (PB0–PB7) • High-Current Infrared (IR) Drive Pin • High-Current Port Pin (PC0) • Power-Saving Stop and Wait Modes • Mask Selectable Options: – COP Watchdog Timer – STOP Instruction Disable – Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger – Port B Pullups for Keyscan
General Description CARRIER MODULATOR TRANSMITTER OSCILLATOR IRQEN ÷2 INTERNAL PROCESSOR CLOCK VSS CORE TIMER SYSTEM RTI SYSTEM RESET ACCUMULATOR IRQEN INDEX REGISTER IRQ 0 0 0 1 1 STACK POINTER PROGRAM COUNTER 0 0 PC4* PC5* PC6* PA0 CPU REGISTERS 0 PC3 ALU M68HC05 CPU 0 PC2 PC7* CPU CONTROL DATA DIRECTION REGISTER LPRST PC1 CONDITION CODE REGISTER 1 1 1 H I N Z PA1 PA2 PORT A COP SYSTEM IRO PC0 PORT C VDD DATA DIRECTION REGISTER OSC2 OSC1 PA3 PA4 PA5 PA6 C PA
General Description Mask Options 1.4 Mask Options There are 11 total mask options on the MC68HC05RC16 including: • Eight port B pullups • IRQ sensitivity • COP enable/disable • STOP enable/disable These are nonprogrammable options in that they are selected at the time of code submission (when masks are made). These options are as follows: PB7PU — Port B7 Pullup/Interrupt This bit enables or disables the pullup/interrupt on port B, bit 7.
General Description PB2PU — Port B2 Pullup/Interrupt This option enables or disables the pullup/interrupt on port B, bit 2. 1 = Enables pullup/interrupt 0 = Disables pullup/interrupt PB1PU — Port B1 Pullup/Interrupt This option enables or disables the pullup/interrupt on port B, bit 1. 1 = Enables pullup/interrupt 0 = Disables pullup/interrupt PB0PU — Port B0 Pullup/Interrupt This option enables or disables the pullup/interrupt on port B, bit 0.
General Description Signal Description 1.5 Signal Description The MC68HC05RC16 is available in 1. 28-pin dual-in-line package (DIP) see Figure 1-2 2. 28-pin small outline integrated circuit (SOIC) package see Figure 1-3 3. 44-pin plastic leaded chip carrier (PLCC) package see Figure 1-4 The signals are described in the following subsections.
General Description PB0 1 28 OSC1 PB1 2 27 OSC2 PB2 3 26 VDD PB3 4 25 IRQ PB4 5 24 RESET PB5 6 23 IRO PB6 7 22 VSS PB7 8 21 LPRST PA0 9 20 PC3 PA1 10 19 PC2 PA2 11 18 PC1 PA3 12 17 PC0 PA4 13 16 PA7 PA5 14 15 PA6 OSC2 VDD IRQ NC 42 41 40 PB0 2 43 PB1 3 OSC1 PB2 4 44 PB3 5 1 NC NC 6 Figure 1-3.
General Description Signal Description 1.5.1 VDD and VSS Power is supplied to the microcontroller’s digital circuits using these two pins. VDD is the positive supply and VSS is ground. 1.5.2 IRQ (Maskable Interrupt Request) In addition to suppling the EPROM with the required programming voltage, this pin has a mask option as specified by the user that provides one of two different choices of interrupt triggering sensitivity. The options are: 1. Negative edge-sensitive triggering only 2.
General Description 1.5.3 OSC1 and OSC2 These pins provide control input for an on-chip clock oscillator circuit. A crystal, a ceramic resonator, or an external signal connects to these pins to provide a system clock. The oscillator frequency is two times the internal bus rate. Figure 1-5 shows the recommended circuit when using a crystal. The crystal and components should be mounted as close as possible to the input pins to minimize output distortion and startup stabilization time.
General Description Signal Description 1.5.4 RESET This active-low pin is used to reset the MCU to a known startup state by pulling RESET low. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See Section 5. Resets. 1.5.5 LPRST The LPRST pin is an active-low pin and is used to put the MCU into low-power reset mode. In low-power reset mode the MCU is held in reset with all processor clocks halted. See Section 5. Resets. 1.5.
General Description 1.5.9 PC0–PC3 (PC4–PC7) These eight I/O lines comprise port C. PC0 is a high-current pin. PC4–PC7 are available only in the 44-lead PLCC package. The state of any pin is software programmable and all port C lines are configured as input during power-on or reset. For detailed information on I/O programming, see 2.4 Input/Output Programming. NOTE: Only four bits of port C are bonded out in 28-pin packages for the MC68HC05RC16, although port C is truly an 8-bit port.
General Release Specification — MC68HC05RC16 Section 2. Memory 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.3.1 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.3.2 ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.3.3 RAM . . . . . . . . . . . . . . . . . . . . .
Memory 0000 PORT A DATA REGISTER $00 0031 0032 PORT B DATA REGISTER $01 PORT C DATA REGISTER $02 RESERVED $03 PORT A DATA DIRECTION REGISTER $04 PORT B DATA DIRECTION REGISTER $05 PORT C DATA DIRECTION REGISTER $06 RESERVED $07 RAM 160 BYTES $00BF $00C0 $00FF $0100 $017F $0180 STACK 64 BYTES RAM 128 BYTES 0191 0192 0255 0256 CORE TIMER CONTROL & STATUS REG.
Memory Memory Map Addr. Register $0000 Port A Data Register $0001 Port B Data Register $0002 Port C Data Register $0003 Reserved $0004 Port A Data Direction Register $0005 Port B Data Direction Register $0006 Port C Data Direction Register $0007 Reserved Bit 7 6 5 4 3 2 1 Bit 0 R R R R R R R R R R R R R R R R RTIF TOFE RTIE TOFC RTFC RT1 RT0 $0008 Timer Control and Status Reg.
Memory Addr. Register Bit 7 6 5 4 3 2 1 Bit 0 $001A Reserved R R R R R R R R $001B Reserved R R R R R R R R $001C Reserved R R R R R R R R $001D Reserved R R R R R R R R $001E Reserved R R R R R R R R $001F Reserved R R R R R R R R R = Reserved Figure 2-2. I/O Registers (Continued) 2.3.1 ROM The user ROM consists of 15,920 bytes of ROM located from $0180 to $3FAF and 16 bytes of user vectors located from $3FF0 to $3FFF.
Memory Input/Output Programming 2.3.3 RAM The user RAM consists of 352 bytes of a shared stack area. The RAM starts at address $0020 and ends at address $017F. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0. NOTE: Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. 2.
Memory General Release Specification 32 MC68HC05RC16 — Rev. 3.
General Release Specification — MC68HC05RC16 Section 3. Central Processor Unit 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.4 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.5 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.6 Stack Pointer . . . . . .
Central Processor Unit 7 0 1 INCREASING MEMORY ADDRESSES 1 R E T U R N 1 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PCH PCL STACK I N T E R R U P T DECREASING MEMORY ADDRESSES UNSTACK NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. Figure 3-2. Stacking Order 3.
Central Processor Unit Condition Code Register 3.5 Condition Code Register The condition code register (CCR) is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be tested individually by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs.
Central Processor Unit 3.6 Stack Pointer The stack pointer (SP) contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the seven most significant bits are permanently set to 0000011.
General Release Specification — MC68HC05RC16 Section 4. Interrupts 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.3 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.4 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.5 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.6 Hardware Interrupts . . . . . . . . . . . . . . .
Interrupts 4.3 CPU Interrupt Processing Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I bit in the CCR is clear) and the corresponding interrupt enable bit is set, the processor will proceed with interrupt processing.
Interrupts Reset Interrupt Sequence The M68HC05 CPU does not support interruptible instructions. The maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. Latency = (Longest instruction execution time + 10) x tcyc seconds An RTI instruction is used to signify when the interrupt software service routine is completed.
Interrupts FROM RESET Y I BIT IN CCR SET? N IRQ/PORT B KEYSCAN EXTERNAL INTERRUPTS Y EIMSK CLEAR? Y CLEAR IRQ REQUEST LATCH. N N INTERNAL CMT INTERRUPT Y N INTERNAL CORE TIMER INTERRUPT Y N STACK PC, X, A, CCR. FETCH NEXT INSTRUCTION. SWI INSTRUCTION ? SET I BIT IN CC REGISTER. Y LOAD PC FROM APPROPRIATE VECTOR. N Y RTI INSTRUCTION ? N RESTORE REGISTERS FROM STACK: CCR, A, X, PC. EXECUTE INSTRUCTION. Figure 4-1.
Interrupts Hardware Interrupts 4.6 Hardware Interrupts All hardware interrupts except RESET are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. The three types of hardware interrupts are explained in the following sections. 4.7 External Interrupt (IRQ/Port B Keyscan) The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ function is shown in Figure 4-2.
Interrupts When edge sensitivity is selected for the IRQ interrupt, it is sensitive to these cases: 1. Falling edge on the IRQ pin 2. Falling edge on any port B pin with pullup enabled When edge and level sensitivity is selected for the IRQ interrupt, it is sensitive to these cases: 1. Low level on the IRQ pin 2. Falling edge on the IRQ pin 3.
Interrupts Core Timer Interrupt 4.10 Core Timer Interrupt This timer can create two types of interrupts. A timer overflow interrupt occurs whenever the 8-bit timer rolls over from $FF to $00 and the enable bit TOFE is set. A real-time interrupt occurs whenever the programmed time elapses and the enable bit RTIE is set. Either of these interrupts vectors to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF6 and $3FF7. MC68HC05RC16 — Rev. 3.
Interrupts General Release Specification 44 MC68HC05RC16 — Rev. 3.
General Release Specification — MC68HC05RC16 Section 5. Resets 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.3 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4 Low-Power External Reset (LPRST) . . . . . . . . . . . . . . . . . . . .48 5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.5.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . .
Resets 5.3 External Reset (RESET) The RESET pin is one of the two external sources of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active-low input will generate the RST signal and reset the CPU and peripherals.
MC68HC05RC16 — Rev. 3.0 MOTOROLA VDD 0V > VPOR 4 OSC12 4064 tCYC tCYC INTERNAL PROCESSOR CLOCK1 Resets INTERNAL ADDRESS BUS1 3FFE 3FFF INTERNAL DATA BUS1 NEW PCH NEW PCL NEW PC NEW PC 3FFE OP CODE 3FFE 3FFE 3FFE 3FFF PCH PCL NEW PC NEW PC OP CODE tRL RESET5 3 Figure 5-2. Reset and POR Timing Diagram Resets External Reset (RESET) 47 General Release Specification NOTES: 1. Internal timing signal and bus information are not available externally. 2.
Resets 5.4 Low-Power External Reset (LPRST) The LPRST pin is one of the two external sources of a reset. This external reset occurs whenever the LPRST pin is pulled below the lower threshold and remains in reset until the LPRST pin rises. This active low input will, in addition to generating the RST signal and resetting the CPU and peripherals, halt all internal processor clocks. The MCU will remain in this low-power reset condition as long as a logic 0 remains on LPRST.
Resets Internal Resets 5.5.2 Computer Operating Properly Reset (COPR) The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to time out, an internal reset is generated to reset the MCU. The COP reset function is enabled or disabled by a mask option and is verified during production testing. 5.5.2.1 Resetting the COP Writing a zero to the COPF bit prevents a COP reset.
Resets 5.5.2.4 COP Watchdog Timer Considerations The COP watchdog timer is active in all modes of operation if enabled by a mask option. If the COP watchdog timer is selected by a mask option, any execution of the STOP instruction (either intentionally or inadvertently due to the CPU being disturbed) causes the oscillator to halt and prevents the COP watchdog timer from timing out. If the COP watchdog timer is selected by a mask option, the COP resets the MCU when it times out.
Resets Internal Resets 5.5.2.5 COP Register The COP register is shared with the LSB of an unimplemented user interrupt vector as shown in Figure 5-3. Reading this location returns whatever user data has been programmed at this location. Writing a zero to the COPR bit in this location clears the COP watchdog timer. Address: Read: $3FF0 BIt 7 6 5 4 3 2 1 Bit 0 X X X X X X X X Write: Reset: COPR — — — — — — — 0 = Unimplemented Figure 5-3. COP Watchdog Timer Location 5.5.
Resets General Release Specification 52 MC68HC05RC16 — Rev. 3.
General Release Specification — MC68HC05RC16 Section 6. Low-Power Modes 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.4 Stop Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 6.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 6.6 Low-Power Reset . . . . .
Low-Power Modes OSC11 tRL RESET tLIH IRQ2 tILCH IRQ3 4064 tCYC INTERNAL CLOCK INTERNAL ADDRESS BUS 3FFE 3FFE 3FFE NOTES: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level and edge-sensitive mask option 3FFE 3FFF RESET OR INTERRUPT VECTOR FETCH Figure 6-1. Stop Recovery Timing Diagram 6.4 Stop Recovery The processor can be brought out of stop mode only by an external interrupt, LPRST, or RESET. Refer to Figure 6-1.
Low-Power Modes Low-Power Reset consumption. Wait current specifications assume CPU operation only and do not include current consumption by any other subsystems. During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous states. The timer may be enabled to allow a periodic exit from wait mode. 6.6 Low-Power Reset Low-power reset mode is entered when a logic 0 is detected on the LPRST pin.
Low-Power Modes STOP WAIT STOP OSCILLATOR AND ALL CLOCKS. OSCILLATOR ACTIVE. IR TIMER CLOCK ACTIVE. CORE TIMER CLOCK ACTIVE. PROCESSOR CLOCKS STOPPED. CLEAR I BIT. N RESET OR LPRST RESET OR LPRST N EXTERNAL INTERRUPT (PTB KEYSCAN PULLUPS) (IRQ) Y Y N EXTERNAL INTERRUPT N (PTB KEYSCAN PULLUPS) (IRQ) Y Y TURN ON OSCILLATOR. WAIT FOR TIME DELAY TO STABILIZE. RESTART PROCESSOR CLOCK. IR TIMER INTERNAL YINTERRUPT Y N CORE TIMER INTERNAL INTERRUPT N Y 1. FETCH RESET VECTOR OR 2.
General Release Specification — MC68HC05RC16 Section 7. Parallel Input/Output (I/O) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 7.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 7.
Parallel Input/Output (I/O) 7.4 Port B Port B is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The address of the port B data register is $0001 and the data direction register (DDR) is at address $0005. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
Parallel Input/Output (I/O) Input/Output Programming the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Port C pins PC4–PC7 are available only with the 44-lead PLCC package. NOTE: Only four bits of port C are bonded out in 28-pin packages for the MC68HC05RC16, although port C is truly an 8-bit port. Since pins PC4–PC7 are unbonded, software should include the code to set their respective data direction register locations to outputs to avoid floating inputs.
Parallel Input/Output (I/O) DATA DIRECTION REGISTER BIT INTERNAL HC05 CONNECTIONS LATCHED OUTPUT DATA BIT OUTPUT I/O PIN INPUT REG BIT INPUT I/O Figure 7-2. I/O Circuitry General Release Specification 60 MC68HC05RC16 — Rev. 3.
General Release Specification — MC68HC05RC16 Section 8. Core Timer 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 8.3 Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .63 8.4 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .65 8.5 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .66 8.6 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .
Core Timer INTERNAL BUS 8 COP CLEAR INTERNAL PERIPHERAL CLOCK (E) 8 CTCR E ÷ 22 $09 CORE TIMER COUNTER REGISTER (CTCR) E ÷ 210 ÷4 E ÷ 212 POR 5-BIT COUNTER TCBP E ÷ 215 E ÷ 214 E ÷ 213 E ÷ 212 RTI SELECT CIRCUIT OVERFLOW DETECT CIRCUIT RTIOUT CTCSR CTOF RTIF TOFE RTIE TOFC RTFC RT1 RT0 TIMER CONTROL & $08 STATUS REGISTER COP WATCHDOG TIMER (÷8) 23 INTERRUPT CIRCUIT TO INTERRUPT LOGIC TO RESET LOGIC Figure 8-1.
Core Timer Core Timer Control and Status Register 8.3 Core Timer Control and Status Register The CTCSR contains the timer interrupt flag, the timer interrupt enable bits, and the real-time interrupt rate select bits. Figure 8-2 shows the value of each bit in the CTCSR when coming out of reset. Address: Read: $08 CTOF RTIF TOFE Write: Reset: 0 0 0 0 TOFC RTFC 0 0 RTIE 0 0 RT1 RT0 1 1 = Unimplemented Figure 8-2.
Core Timer TOFC — Timer Overflow Flag Clear When a one is written to this bit, CTOF is cleared. Writing a zero has no effect on the CTOF bit. This bit always reads as zero. RTFC — Real-Time Interrupt Flag Clear When a one is written to this bit, RTIF is cleared. Writing a zero has no effect on the RTIF bit. This bit always reads as zero. RT1–RT0 — Real-Time Interrupt Rate Select These two bits select one of four taps from the real-time interrupt circuit. Refer to Table 8-1.
Core Timer Core Timer Counter Register 8.4 Core Timer Counter Register The timer counter register is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked by the CPU clock (E/4) and can be used for various functions, including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location, thereby simulating a 16-bit (or more) counter.
Core Timer 8.5 Computer Operating Properly (COP) Reset The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 8-1. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP timeout, or clearing the COP is accomplished by writing a zero to bit 0 of address $3FF0.
General Release Specification — MC68HC05RC16 Section 9. Carrier Modulator Transmitter (CMT) 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 9.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 9.4 Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 9.4.1 Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 9.4.
Carrier Modulator Transmitter (CMT) used to change the state of the infrared out pin (IRO) directly. This feature allows for the generation of future protocols not readily producible by the current architecture. 9.3 Overview The module consists of carrier generator, modulator, and transmitter output blocks. The block diagram is shown in Figure 9-1. The carrier generator has a resolution of 500 ns with a 2-MHz oscillator.
Carrier Modulator Transmitter (CMT) Overview PRIMARY/SECONDARY SELECT MODE BASE MODULATOR EOC INTERRUPT ENABLE . MODULATOR OUT EOC FLAG fOSC CARRIER GENERATOR CARRIER OUT TRANSMITTER OUTPUT IRO PIN MODULATOR/ CARRIER ENABLE CPU INTERFACE fOSC ÷ 2 DB AB EOC INTERRUPT Figure 9-1. Carrier Modulator Transmitter Module Block Diagram The modulator provides a simple method to control protocol timing. The modulator has a resolution of 4 µs with a 2-MHz oscillator.
Carrier Modulator Transmitter (CMT) 9.4 Carrier Generator The carrier signal is generated by counting a predetermined number of input clocks (500 ns for a 2-MHz oscillator) for both the carrier high time and the carrier low time. The period is determined by the total number of clocks counted. The duty cycle is determined by the ratio of high time clocks to total clocks counted. The high and low time values are user programmable and are held in two registers.
Carrier Modulator Transmitter (CMT) Carrier Generator 9.4.1 Time Counter The high/low time counter is a 6-bit up counter. After each increment, the contents of the counter are compared with the appropriate high or low count value register. When this value is reached, the counter is reset and the compare is redirected to the other count value register. Assuming that the high time count compare register is currently active, a valid compare will cause the carrier output to be driven low.
Carrier Modulator Transmitter (CMT) 9.4.2 Carrier Generator Data Registers (CHR1, CLR1, CHR2, and CLR2) The carrier generator contains two, 7-bit data registers: primary high time (CHR1), primary low time (CLR1); and two, 6-bit data registers: secondary high time (CHR2) and secondary low time (CLR2). Bit 7 of CHR1 and CHR2 is used to read and write the IRO latch.
Carrier Modulator Transmitter (CMT) Carrier Generator Address: $0013 Bit 7 6 5 4 3 2 1 Bit 0 0 0 SL5 SL4 SL3 SL2 SL1 SL0 0 0 U U U U U U Read: Write: Reset: U = Unaffected Figure 9-6. Carrier Generator Data Register CLR2 PH0–PH5 and PL0–PL5 — Primary Carrier High and Low Time Data Values When selected, these bits contain the number of input clocks required to generate the carrier high and low time periods. When operating in time mode (see 9.5.
Carrier Modulator Transmitter (CMT) of the modulator. The secondary carrier high and low time values are undefined out of reset. These bits must be written to nonzero values before the carrier generator is enabled when operating in FSK mode. IROLN and IROLP — IRO Latch Control Reading IROLN or IROLP reads the state of the IRO latch. Writing IROLN updates the IRO latch with the data being written on the negative edge of the internal processor clock (fosc/2).
Carrier Modulator Transmitter (CMT) Modulator The modulator can operate in two modes, time or FSK. In time mode the modulator counts clocks derived from the system oscillator and modulates a single-carrier frequency or no carrier (baseband). In FSK mode, the modulator counts carrier periods and instructs the carrier generator to alternate between two carrier frequencies whenever a modulation period (mark + space counts) expires. 12 BITS MBUFF 0 fOSC 8 CLOCK CONTROL .
Carrier Modulator Transmitter (CMT) 9.5.1 Time Mode When the modulator operates in time mode, the modulation mark and space periods consist of zero or an integer number of fosc ÷ 8 clocks (= 250 kHz @ 2 MHz osc). This provides a modulator resolution of 4 µs and a maximum mark and space periods of about 16 ms (each). However, to prevent carrier glitches which could affect carrier spectral purity, the modulator control gate and carrier clock are synchronized.
Carrier Modulator Transmitter (CMT) Modulator fOSC ÷ 8 CARRIER FREQUENCY MODULATOR GATE MARK SPACE MARK SPACE MARK TIME MODE OUTPUT BASEBAND OUTPUT Figure 9-8. CMT Operation in Time Mode 9.5.2 FSK Mode When the modulator operates in FSK mode, the modulation mark and space periods consist of an integer number of carrier clocks (space period can be zero).
Carrier Modulator Transmitter (CMT) The mark and space time equations for FSK mode are: MBUFF + 1 t mark = ------------------------------- sec s fcg SBUFF t space = --------------------- sec s f cg Where fcg is the frequency output from the carrier generator, setting the DIV2 bit in the MCSR will double mark and space times. 9.5.3 Extended Space Operation In either time or FSK mode, the space period can be made longer than the maximum possible value of SBUFF.
Carrier Modulator Transmitter (CMT) Modulator Where fcg is the frequency output from the carrier generator. For an example of extended space operation, see Figure 9-9. NOTE: The EXSPC feature can be used to emulate a zero mark event. SET EXSPC CLEAR EXSPC Figure 9-9. Extended Space Operation 9.5.3.1 End Of Cycle (EOC) Interrupt At the end of each cycle (when the counter is reloaded from MBUFF), the end of cycle (EOC) flag is set.
Carrier Modulator Transmitter (CMT) 9.5.3.2 Modulator Control and Status Register The modulator control and status register (MCSR) contains the modulator and carrier generator enable (MCGEN), interrupt enable (IE), mode select (MODE), baseband enable (BASE), extended space (EXSPC), and external interrupt mask (EIMSK) control bits, divide-by-two prescaler (DIV2) bit, and the end of cycle (EOC) status bit.
Carrier Modulator Transmitter (CMT) Modulator EIMSK — External Interrupt Mask The external interrupt mask bit is used to mask IRQ and keyscan interrupts. This bit is cleared by reset. 1 = IRQ and keyscan interrupts masked 0 = IRQ and keyscan interrupts enabled EXSPC — Extended Space Enable For a description of the extended space enable bit, see 9.5.3 Extended Space Operation. This bit is cleared by reset.
Carrier Modulator Transmitter (CMT) MCGEN — Modulator and Carrier Generator Enable Setting MCGEN will initialize the carrier generator and modulator and will enable all clocks. Once enabled, the carrier generator and modulator will function continuously. When MCGEN is cleared, the current modulator cycle will be allowed to expire before all carrier and modulator clocks are disabled (to save power) and the modulator output is forced low.
Carrier Modulator Transmitter (CMT) Modulator 9.5.4 Modulator Period Data Registers (MDR1, MDR2, and MDR3) The 12-bit MBUFF and SBUFF registers are accessed through three 8-bit registers: MDR1, MDR2, and MDR3. MDR2 and MDR3 contain the least significant eight bits of MBUFF and SBUFF respectively. MDR1 contains the two most significant nibbles of MBUFF and SBUFF. In many applications, periods greater than those obtained by eight bits will not be required.
Carrier Modulator Transmitter (CMT) General Release Specification 84 MC68HC05RC16 — Rev. 3.
General Release Specification — MC68HC05RC16 Section 10. Instruction Set 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 10.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 10.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 10.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 10.3.3 Direct . . . . . . . . . . .
Instruction Set 10.2 Introduction The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator. 10.
Instruction Set Addressing Modes 10.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. 10.3.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register.
Instruction Set 10.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF.
Instruction Set Instruction Types 10.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction.
Instruction Set 10.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 10-1.
Instruction Set Instruction Types 10.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. Table 10-2.
Instruction Set 10.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed.
Instruction Set Instruction Types Table 10-3.
Instruction Set 10.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 10-4. Bit Manipulation Instructions Instruction Bit Clear BCLR Branch if Bit Clear BRCLR Branch if Bit Set BRSET Bit Set General Release Specification 94 Mnemonic BSET MC68HC05RC16 — Rev. 3.
Instruction Set Instruction Types 10.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 10-5.
Instruction Set 10.
Instruction Set Instruction Set Summary Address Mode Opcode Operand Cycles Table 10-6.
Instruction Set CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X 3F 4F 5F 6F 7F dd ↕ IMM DIR EXT IX2 IX1 IX ii A1 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 1 DIR INH INH IX1 IX 33 43 53 63 73 ↕ IMM DIR EXT IX2 IX1 IX ii A3 2 B3 dd 3 C3 hh ll
Instruction Set Instruction Set Summary LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Effective Address A ← (M) X ← (M) Load Index Register with Memory Byte Logical Shift Left (Same as ASL) — — ↕ ↕ — IMM DIR EXT IX2 IX1 IX ii A6 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 ↕ — IMM DIR EXT IX2 IX1 I
Instruction Set DIR INH INH IX1 IX 36 46 56 66 76 dd — — — — — INH 9C 2 ↕ ↕ INH 80 9 — — — — — INH 81 6 — — ↕ ↕ IMM DIR EXT IX2 IX1 IX ii A2 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 Effect on CCR Description H I N Z C ROR opr RORA RORX ROR opr,X ROR ,X Rotate Byte Right through Carry Bit RSP Reset Stack Pointer SP ← $00FF RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL)
Instruction Set Instruction Set Summary Test Memory Byte for Negative or Zero TXA Transfer Index Register to Accumulator A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n dd A ← (X) — — — — — INH 9F 2 Stop CPU Clock and Enable Interrupts MC68HC05RC16 — Rev. 3.
Bit Manipulation DIR DIR MSB LSB 0 1 2 3 4 5 6 Instruction Set 7 8 9 A B C MOTOROLA MC68HC05RC16 — Rev. 3.
General Release Specification — MC68HC05RC16 Section 11. Electrical Specifications 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 11.3 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 11.4 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 11.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 11.
Electrical Specifications 11.3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD. Rating Symbol Value Unit Supply Voltage VDD –0.
Electrical Specifications Operating Range 11.4 Operating Range Characteristic Operating Temperature Range MC68HC05RC16 (Standard) Symbol Value Unit TA TL to TH 0 to +70 °C Symbol Value Unit θJA 60 60 60 °C/W 11.5 Thermal Characteristics Characteristic Thermal Resistance Plastic Dual In-Line Package Small Outline Intergrated Circuit Package Plastic Leaded Chip Carrier Package MC68HC05RC16 — Rev. 3.
Electrical Specifications 11.6 DC Electrical Characteristics (5.0 Vdc) Characteristic Output Voltage ILOAD = 10.0 µA ILOAD = –10.0 µA Symbol Min Typ Max Unit VOL VOH — VDD– 0.1 — — 0.1 — V VDD –0.8 VDD –0.8 VDD –0.8 VDD –0.2 VDD –0.2 VDD –0.2 — — — — — — 0.2 0.2 0.2 0.4 0.4 0.4 Output High Voltage (ILOAD –2.0 mA) Port A, Port B, Port C (1–7) (ILOAD –20 mA) IRO (ILOAD –4.0 mA) Port C (Bit 0) VOH Output Low Voltage (ILOAD = 3.0 mA) Port A, Port B, Port C (1–7) (ILOAD = 25.
Electrical Specifications DC Electrical Characteristics (2.2 Vdc) 11.7 DC Electrical Characteristics (2.2 Vdc) Characteristic Output Voltage ILOAD = 10.0 µA ILOAD = –10.0 µA Symbol Min Typ Max Unit VOL VOH — VDD– 0.1 — — 0.1 — V VDD– 0.3 VDD– 0.3 VDD– 0.3 VDD– 0.1 VDD– 0.1 VDD– 0.1 — — — — — — 0.1 0.1 0.1 0.3 0.3 0.3 Output High Voltage (ILOAD –0.6 mA) Port A, Port B, Port C (1–7) (ILOAD –8.0 mA) IRO (ILOAD –1.2 mA) Port C (Bit 0) VOH Output Low Voltage (ILOAD = 1.
Electrical Specifications 4.0 SUPPLY CURRENT (mA) VDD = 5.5 V TA = –0 °C to 70 °C 3.0 2.0 N I DD RU 1.0 WAIT I DD STOP IDD (20 µA) 0 0 0.5 1.0 1.5 2.0 2.1 2.5 2.0 2.1 INTERNAL CLOCK FREQUENCY (MHz) XTAL ÷ 2 2.5 INTERNAL CLOCK FREQUENCY (MHz) XTAL ÷ 2 1.0 VDD = 2.4 V TA = –0 °C to 70 °C SUPPLY CURRENT (mA) 0.8 N RU 0.6 I DD 0.4 0.3 WAIT 0.2 I DD STOP IDD (4 µA) 0 0 0.5 1.0 1.5 Figure 11-1.
Electrical Specifications Control Timing (5.0 Vdc and 2.2 Vdc) 11.8 Control Timing (5.0 Vdc and 2.2 Vdc) Characteristic Symbol Min Max Unit Frequency of Operation Crystal External Clock fosc — dc 4.2 4.2 MHz Internal Operating Frequency Crystal (fOSC /2) External Clock (fOSC /2) fop — dc 2.1 2.1 MHz Cycle Time tcyc 480 — ns Crystal Oscillator Startup Time tOXOV — 100 ms Stop Recovery Startup Time (Crystal Oscillator) tILCH — 100 ms RESET Pulse Width tRL 1.
Electrical Specifications General Release Specification 110 MC68HC05RC16 — Rev. 3.
General Release Specification — MC68HC05RC16 Section 12. Mechanical Specifications 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.3 28-Pin Plastic Dual-In-Line Package (Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.4 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.
Mechanical Specifications 12.
Mechanical Specifications 44-Pin Plastic Leaded Chip Carrier Package (Case 777-02) 12.5 44-Pin Plastic Leaded Chip Carrier Package (Case 777-02) -N- Y BRK 0.007(0.180) M T B D L-M S 0.007(0.180) M T U N S L-M S N S Z -M- -L- V 44 G1 X D W 1 0.010 (0.25) S T VIEW D-D A 0.007(0.180) M T L-M S N S R 0.007(0.180) M T L-M S N S 0.007(0.180) M T H L-M S L-M S N S N S Z J K1 E 0.004 (0.10) G C -TG1 0.010 (0.25) S T L-M S N S K SEATING PLANE F VIEW S 0.007(0.
Mechanical Specifications General Release Specification 114 MC68HC05RC16 — Rev. 3.
General Release Specification — MC68HC05RC16 Section 13. Ordering Information 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 13.3 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 13.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .116 13.5 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .117 13.6 ROM Verification Units (RVUs). . . . . . .
Ordering Information The current MCU ordering form is also available through the Motorola Freeware Bulletin Board Service (BBS). The telephone number is (512) 891-FREE. After making the connection, type bbs in lower-case letters. Then press the return key to start the BBS software. 13.4 Application Program Media Please deliver the application program to Motorola in one of the following media: • Macintosh1 3 1/2-inch diskette (double-sided 800K or double-sided high-density 1.
Ordering Information ROM Program Verification NOTE: Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all nonuser ROM locations or leave all nonuser ROM locations blank. Refer to the current MCU ordering form for additional requirements. Motorola may request pattern re-submission if nonuser areas contain any nonzero code.
Ordering Information 13.6 ROM Verification Units (RVUs) After receiving the signed listing verify form, Motorola manufactures a custom photographic mask. The mask contains the customer’s application program and is used to process silicon wafers. The application program cannot be changed after the manufacture of the mask begins. Motorola then produces 10 MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature.
General Release Specification — MC68HC05RC16 Appendix A. MC68HC05RC8 A.1 Contents A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 A.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 A.2 Introduction Appendix A introduces the MC68HC05RC8. The technical data applying to the MC68HC05RC16 applies to the MC68HC05RC8 with the exceptions given in this appendix. A.
MC68HC05RC8 $0000 $001F $0020 I/O 32 BYTES 0000 PORT A DATA REGISTER $00 0031 0032 PORT B DATA REGISTER $01 PORT C DATA REGISTER $02 RESERVED $03 PORT A DATA DIRECTION REGISTER $04 PORT B DATA DIRECTION REGISTER $05 PORT C DATA DIRECTION REGISTER $06 RESERVED $07 RAM 160 BYTES $00BF $00C0 $00FF $0100 $017F $0180 STACK 64 BYTES RAM 128 BYTES 0191 0192 0255 0256 CORE TIMER CONTROL & STATUS REG.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
