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DOCUMENT NUMBER

9S12C128DGV1/D

MC9S12C Family

Device User Guide

V01.05

Covers also

MC9S12GC Family

Original Release Date: 25 JAN 2003

Revised: 11 FEBRUARY 2004

Motorola, Inc.

Summary of content (136 pages)

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DOCUMENT NUMBER 9S12C128DGV1/D MC9S12C Family Device User Guide V01.05 Covers also MC9S12GC Family Original Release Date: 25 JAN 2003 Revised: 11 FEBRUARY 2004 Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein.
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Device User Guide — 9S12C128DGV1/D V01.05 Revision History Version Revision Effective Number Date Date 00.01 Author Description of Changes 25.JAN.03 25.JAN.03 Original Version. Based on C32 user guide version 01.12 00.02 07.FEB.03 07.FEB.03 Enhanced PortK description Part number table revision in preface 00.03 25.FEB.03 25.FEB.03 QFP112 Emulation pinout correction Enhanced part number explanation in preface Reduced pseudo STOP current spec. for C64,C96,C128 00.04 15.APR.03 15.
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Device User Guide — 9S12C128DGV1/D V01.05 Table of Contents Section 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Block Diagram . . . . .
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Device User Guide — 9S12C128DGV1/D V01.05 2.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.21 PM5 / SCK — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.22 PM4 / MOSI — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.23 PM3 / SS — Port M I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.
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Device User Guide — 9S12C128DGV1/D V01.05 5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Device User Guide — 9S12C128DGV1/D V01.05 Section 16 RAM Block Description Section 17 Pulse Width Modulator (PWM) Block Description Section 18 MSCAN Block Description Section 19 Port Integration Module (PIM) Block Description Appendix A Electrical Characteristics A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Device User Guide — 9S12C128DGV1/D V01.05 B.6 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 B.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 B.6.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 B.6.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Device User Guide — 9S12C128DGV1/D V01.05 List of Figures Figure 0-1 Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 1-6 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 3-1 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6 Figure B-1 Figure B-2 Figure B-3 Figure B-4 Figure B-5 Figure C-1 Figure C-2 Figure C-3 Figure C-4 Figure C-5 Figure D-1 Figure D-2 Order Part number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Device User Guide — 9S12C128DGV1/D V01.05 Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F) . . . . . . 130 Figure 19-1 Pin Assignments in 112-pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (case no.
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Device User Guide — 9S12C128DGV1/D V01.05 List of Tables Table 0-2 MC9S12C-Family Package Option Summary . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 0-1 List of MC9S12C and MC9S12GC Family members. . . . . . . . . . . . . . . . . . . . 15 Table 0-3 MC9S12C-Family Part Number Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 0-4 MC9S12GC-Family Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 0-5 Document References . . . . . . . . .
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Device User Guide — 9S12C128DGV1/D V01.05 $0180 - $023F Reserved 47 $0240 - $027F PIM (Port Interface Module) 47 $0280 - $03FF Reserved space 50 Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Device User Guide — 9S12C128DGV1/D V01.05 Table C-2 Table C-3 Table C-4 Table C-5 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Expanded Bus Timing Characteristics (5V Range). . . . . . . . . . . . . . . . . . . . 124 Expanded Bus Timing Characteristics (3.3V Range) . . . . . . . . . . . . . . . . . .
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Device User Guide — 9S12C128DGV1/D V01.05 Preface The Device User Guide provides information about the MC9S12C-Family as well the MC9S12GC-Family devices made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides of the implemented modules.
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Device User Guide — 9S12C128DGV1/D V01.05 Package Device 48LQFP Part Number MC9S12C64 MC9S12C64 Mask1 set Temp.
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Device User Guide — 9S12C128DGV1/D V01.05 Mask set Temp.
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Device User Guide — 9S12C128DGV1/D V01.05 Part Number Temp.
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Device User Guide — 9S12C128DGV1/D V01.05 Mask set Temp.
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Device User Guide — 9S12C128DGV1/D V01.05 Mask set Temp.
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Device User Guide — 9S12C128DGV1/D V01.05 Part Number MC9S12GC16VFU25 Mask set Temp.
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Device User Guide — 9S12C128DGV1/D V01.05 Section 1 Introduction 1.1 Overview The MC9S12C-Family and the MC9S12GC-Family is a 48/52/80 pin Flash-based Industrial/Automotive network control MCU family. Members of the MC9S12C-Family and the MC9S12GC-Family deliver the power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive, general purpose Industrial and Automotive network applications.
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Device User Guide — 9S12C128DGV1/D V01.05 – • • • • • • 24 1K, 2K or 4K Byte RAM Analog-to-Digital Converters – One 8-channel module with 10-bit resolution. – External conversion trigger capability Available on MC9S12C-Family: One 1M bit per second, CAN 2.
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Device User Guide — 9S12C128DGV1/D V01.05 • • • • – Pierce or low current Colpitts oscillator – Phase-locked loop clock frequency multiplier – Limp home mode in absence of external clock – Low power 0.
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Device User Guide — 9S12C128DGV1/D V01.05 1.4 Block Diagram Figure 1-1 MC9S12C-Family Block Diagram PLL 2.5V VDDPLL VSSPLL PTAD PTT SPI PJ6 PJ7 PTS PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Internal Logic 2.
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Device User Guide — 9S12C128DGV1/D V01.05 1.5 Device Memory Map Table 1-1 shows the device register map of the MC9S12C-Family after reset. The following figures (Figure 1-2, Figure 1-2, Figure 1-3 and Figure 1-4) illustrate the full device memory map with flash and RAM.
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Device User Guide — 9S12C128DGV1/D V01.05 $0000 1K Register Space $0000 $0400 $03FF Mappable to any 2K Boundary $3800 $3800 2K Bytes RAM $3FFF Mappable to any 2K Boundary PAGE MAP $4000 $8000 EXT PPAGE $C000 $C000 $FFFF $FF00 $FF00 $FFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP $FFFF 16K Fixed Flash EEPROM $3F BDM (If Active) The figure shows a useful map, which is not the map out of reset.
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Device User Guide — 9S12C128DGV1/D V01.05 $0280 - $03FF Reserved space Address Name Read: $0280 Reserved - $2FF Write: Read: $0300 Unimplemented $03FF Write: Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0 0 0 0 0 0 0 0 1.7 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID numbers.
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PP5/KWP5/PW5 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PS1/TXD PS0/RXD VSSA 51 50 49 48 47 46 45 44 43 42 41 40 PP4/KWP4/PW4 52 Device User Guide — 9S12C128DGV1/D V01.
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VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PS1/TXD PS0/RXD VSSA 46 45 44 43 42 41 40 39 38 37 VDDX PW1/IOC1/PT1 47 1 PP5/KWP5/PW5 PW0/IOC0/PT0 48 Device User Guide — 9S12C128DGV1/D V01.
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Device User Guide — 9S12C128DGV1/D V01.05 2.
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Device User Guide — 9S12C128DGV1/D V01.05 2.3 Detailed Signal Descriptions 2.3.1 EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 2.3.2 RESET — External Reset Pin RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state.
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Device User Guide — 9S12C128DGV1/D V01.05 2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue.
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Device User Guide — 9S12C128DGV1/D V01.05 EXTAL CDC * C1 MCU Crystal or ceramic resonator XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal .Please contact the crystal manufacturer for crystal DC Figure 2-5 Colpitts Oscillator Connections (PE7=1) EXTAL C1 MCU Crystal or ceramic resonator RB XTAL RS* C2 VSSPLL * Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturer’s data.
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Device User Guide — 9S12C128DGV1/D V01.05 2.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1}. This pin is an input with a pull-down device which is only active when RESET is low. PE[6] is not available in the 48 / 52 pin package versions. 2.3.
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Device User Guide — 9S12C128DGV1/D V01.05 2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing IRQEN bit (INTCR register).
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Device User Guide — 9S12C128DGV1/D V01.05 2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0] PP[5:0] are general purpose input or output pins, shared with the keypad interrupt function. When configured as inputs, they can generate interrupts causing the MCU to exit STOP or WAIT mode. PP[5:0] are also shared with the PWM output signals, PW[5:0]. Pins PP[2:0] are only available in the 80 pin package version. Pins PP[4:3] are not available in the 48 pin package version. 2.3.
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Device User Guide — 9S12C128DGV1/D V01.05 2.3.27 PS[3:2] — Port S I/O Pins [3:2] PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48 / 52 pin package versions. 2.3.28 PS1 / TXD — Port S I/O Pin 1 PS1 is a general purpose input or output pin and the transmit pin, TXD, of Serial Communication Interface (SCI). 2.3.29 PS0 / RXD — Port S I/O Pin 0 PS0 is a general purpose input or output pin and the receive pin, RXD, of Serial Communication Interface (SCI). 2.3.
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Device User Guide — 9S12C128DGV1/D V01.05 2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG VDDA, VSSA are the power supply and ground input pins for the voltage regulator reference and the analog to digital converter. 2.4.5 VRH, VRL — ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter. 2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop.
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Device User Guide — 9S12C128DGV1/D V01.05 The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation. S12_CORE core clock Flash RAM TIM ATD PIM EXTAL SCI CRG bus clock oscillator clock SPI MSCAN Not on 9S12GC XTAL VREG TPM Figure 3-1 Clock Connections Section 4 Modes of Operation 4.
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Device User Guide — 9S12C128DGV1/D V01.05 latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
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Device User Guide — 9S12C128DGV1/D V01.05 of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters. 4.3.1 Securing the Microcontroller Once the user has programmed the FLASH, the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array.
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Device User Guide — 9S12C128DGV1/D V01.05 4.4.1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts. 4.4.2 Pseudo Stop This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off.
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Device User Guide — 9S12C128DGV1/D V01.05 changed to known start-up states. Refer to the respective module Block User Guides for register reset states. 5.3.1 Reset Summary Table Table 5-2 Reset Summary Reset Priority Source Vector Power-on Reset 1 CRG Module $FFFE, $FFFF External Reset 1 RESET pin $FFFE, $FFFF Low Voltage Reset 1 VREG Module $FFFE, $FFFF Clock Monitor Reset 2 CRG Module $FFFC, $FFFD COP Watchdog Reset 3 CRG Module $FFFA, $FFFB 5.3.
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Device User Guide — 9S12C128DGV1/D V01.05 For all devices Flash Page 3F is visible in the $C000-$FFFF range if ROMON is set. For all devices (ecept 9S12GC16) Page 3E is also visible in the $4000-$7FFF range if ROMHM is cleared and ROMON is set. For all devices apart from MC9S12C32 Flash Page 3D is visible in the $0000-$3FFF range if ROMON is set... Table 6-1 Device Specific Flash PAGE Mapping Device PAGE PAGE visible with PPAGE contents MC9S12GC16 3F $00,$01,$02,$03,$04,$05,$06,$07,$08,$09......
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Device User Guide — 9S12C128DGV1/D V01.05 To prevent unnecessary current flow in production package options, the states of DDRK and PUPKE should not be changed by software. Section 7 Voltage Regulator (VREG) Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator. 7.1 Device-specific information The VREG is part of the IPBus domain. 7.1.1 VREGEN VREGEN is connected internally to VDDR. 7.1.
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Device User Guide — 9S12C128DGV1/D V01.05 C6 VDDX VSSA C3 VSSX VDDA VDD1 C1 VSS1 VSSR C4 C7 R1 C8 C10 C9 Note: Oscillator in Colpitts mode.
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Device User Guide — 9S12C128DGV1/D V01.05 ) NOTE: Oscillator in Colpitts mode.
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Device User Guide — 9S12C128DGV1/D V01.05 ) NOTE: Oscillator in Colpitts mode.
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Device User Guide — 9S12C128DGV1/D V01.05 C6 VDDX VSSA VSSX C3 VDDA VDD1 VSS2 C1 C2 VSS1 VDD2 VSSPLL VSSR C4 R3 C5 VDDR R2 Q1 C7 C8 C10 C9 R1 VSSPLL VDDPLL Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator Section 9 Clock Reset Generator (CRG) Block Description Consult the CRG Block User Guide for information about the Clock and Reset Generator module. 9.1 Device-specific information The CRG is part of the IPBus domain.
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Device User Guide — 9S12C128DGV1/D V01.05 The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the VREG Block User Guide for voltage level specifications. 9.1.1 XCLKS The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
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Device User Guide — 9S12C128DGV1/D V01.05 Consult the SPI Block User Guide for information about the Synchronous Serial Communications Interface module. Section 15 Flash Block Description Consult the FTS16K Block User Guide for information about the Flash module for the MC9S12GC16. Consult the FTS32K Block User Guide for information about the Flash module for the MC9S12C32 or MC9S12GC32. Consult the FTS64K Block User Guide for information about the Flash module for the MC9S12C64 or MC9S12GC64.
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Device User Guide — 9S12C128DGV1/D V01.05 Consult the PIM_9C32 Block User Guide for information about the Port Integration Module for all versions of the MC9DS12GC and MC9S12C-Family. The MODRR register within the PIM allows for mapping of PWM channels to PortT in the absence of PortP pins for the low pin count packages. For the 80QFP package option it is recommended not to use MODRR since this is intended to support PWM channel availability in low pin count packages.
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Device User Guide — 9S12C128DGV1/D V01.05 Appendix A Electrical Characteristics A.1 General NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice. NOTE: The parts are specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.
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Device User Guide — 9S12C128DGV1/D V01.05 VSS1 and VSS2 are internally connected by metal. VDD1 and VDD2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins.
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Device User Guide — 9S12C128DGV1/D V01.05 A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device.
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Device User Guide — 9S12C128DGV1/D V01.05 A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification.
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Device User Guide — 9S12C128DGV1/D V01.05 NOTE: Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions Rating Symbol Min Typ Max Unit I/O, Regulator and Analog Supply Voltage VDD5 2.97 5 5.5 V Digital Logic Supply Voltage1 VDD 2.35 2.5 2.75 V PLL Supply Voltage (1) VDDPLL 2.35 2.
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Device User Guide — 9S12C128DGV1/D V01.05 Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA 2 P IO = R DSON ⋅ I IO i i ∑ Which is the sum of all output currents on I/O ports associated with VDDX and VDDM.
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Device User Guide — 9S12C128DGV1/D V01.05 Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.
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Device User Guide — 9S12C128DGV1/D V01.05 Table A-6 5V I/O Characteristics Conditions are 4.5< VDDX <5.5V Termperature from -40˚C to +140˚C, unless otherwise noted Num C Min Typ Max Unit 1 P Input High Voltage V 0.65*VDD5 - - V T Input High Voltage VIH - - VDD5 + 0.3 V P Input Low Voltage VIL - - 0.35*VDD5 V T Input Low Voltage VIL VSS5 - 0.
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Device User Guide — 9S12C128DGV1/D V01.05 Table A-7 3.3V I/O Characteristics Conditions are VDDX=3.3V +/-10%, Termperature from -40˚C to +140˚C, unless otherwise noted Num C Min Typ Max Unit 1 P Input High Voltage V 0.65*VDD5 - - V T Input High Voltage VIH - - VDD5 + 0.3 V P Input Low Voltage VIL - - 0.35*VDD5 V T Input Low Voltage VIL VSS5 - 0.
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Device User Guide — 9S12C128DGV1/D V01.05 A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator. A.1.10.
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Device User Guide — 9S12C128DGV1/D V01.05 Table A-8 Supply Current Characteristics for MC9S12C32 Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted Num C 1 P Rating Run Supply Current Single Chip Symbol Min Typ IDD5 Max Unit 35 mA 30 8 mA Wait Supply current 2 3 4 P P C All modules enabled VDDR<4.9V, only RTI enabled(2) VDDR>4.
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Device User Guide — 9S12C128DGV1/D V01.05 Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128 Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted Num C 1 P Rating Run Supply Current Single Chip, Symbol Min Typ IDD5 Max Unit 45 mA 33 8 mA Wait Supply current 2 6 4 P P C All modules enabled VDDR<4.9V, only RTI enabled(2) VDDR>4.
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Device User Guide — 9S12C128DGV1/D V01.05 Appendix B Electrical Specifications B.1 Voltage Regulator Operating Conditions Table B-1 Voltage Regulator Electrical Parameters Nu m C 1 P Input Voltages 2 C 3 Symbol Min Typical Max Unit VVDDR, A 2.97 — 5.5 V Regulator Current Reduced Power Mode Shutdown Mode IREG — — 20 12 50 40 µA µA P Output Voltage Core Full Performance Mode VDD 2.35 2.5 2.
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Device User Guide — 9S12C128DGV1/D V01.05 B.2 Chip Power-up and LVI/LVR graphical explanation Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure B-1. Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) V VDDA VLVID VLVIA VDD VLVRD VLVRA VPORD t LVI LVI enabled LVI disabled due to LVR POR LVR B.3 Output Loads B.3.
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Device User Guide — 9S12C128DGV1/D V01.05 B.3.2 Capacitive Loads The capacitive loads are specified in Table B-2. Ceramic capacitors with X7R dielectricum are required.
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Device User Guide — 9S12C128DGV1/D V01.05 B.4 ATD Characteristics This section describes the characteristics of the analog to digital converter. VRL is not available as a separate pin in the 48 and 52 pin versions. In this case the internal VRL pad is bonded to the VSSA pin. The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test. B.4.
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Device User Guide — 9S12C128DGV1/D V01.05 beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped Table B-4 ATD Operating Characteristics Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10% Num C Rating Symbol Min VRL VRH VSSA VDDA/2 Typ Max Unit VDDA/2 VDDA V V 3.6 V Reference Potential 1 D Low High 2 C Differential Reference Voltage VRH-VRL 3.
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Device User Guide — 9S12C128DGV1/D V01.05 B.4.3.3 Current injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive conditions. 2. Current is injected into pins in the neighborhood of the channel being converted.
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Device User Guide — 9S12C128DGV1/D V01.05 B.4.4 ATD accuracy (5V Range) Table B-6 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table B-6 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.
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Device User Guide — 9S12C128DGV1/D V01.05 For the following definitions see also Figure B-2. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
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Device User Guide — 9S12C128DGV1/D V01.05 DNL LSB Vi-1 $3FF 10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary $3FE $3FD $3FC $FF $3FB $3FA $3F9 $3F8 $FE $3F7 $3F6 $3F4 8-Bit Resolution 10-Bit Resolution $3F5 $FD $3F3 9 Ideal Transfer Curve 8 2 7 10-Bit Transfer Curve 6 5 4 1 3 8-Bit Transfer Curve 2 1 0 3.25 6.5 9.75 13 16.25 19.5 22.75 26 29.
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Device User Guide — 9S12C128DGV1/D V01.05 B.5 NVM, Flash and EEPROM B.5.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum.
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Device User Guide — 9S12C128DGV1/D V01.05 B.5.1.3 Sector Erase Erasing either a 512 byte or 1024 byte Flash sector takes: 1 t era ≈ 4000 ⋅ --------------------f NVMOP The setup times can be ignored for this operation. B.5.1.4 Mass Erase Erasing a NVM block takes: 1 t mass ≈ 20000 ⋅ --------------------f NVMOP This is independent of sector size. The setup times can be ignored for this operation.
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Device User Guide — 9S12C128DGV1/D V01.05 B.5.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at <2ppm defects over lifetime at the operating conditions noted. A program/erase cycle is specified as two transitions of the cell value from erased → programmed → erased, 1 → 0 → 1.
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Device User Guide — 9S12C128DGV1/D V01.05 B.6 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). B.6.1 Startup Table B-10 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
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Device User Guide — 9S12C128DGV1/D V01.05 B.6.1.4 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. B.6.1.5 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. B.6.1.
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Device User Guide — 9S12C128DGV1/D V01.05 time tUPOSC. The device features a clock monitor. A time-out is asserted if the frequency of the incoming clock signal is below the Clock Monitor FailureAssert Frequency fCMFA. Table B-11 Oscillator Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1a C 1b Rating Symbol Min Typ Max Unit Crystal oscillator range (Colpitts) fOSC 0.5 16 MHz C Crystal oscillator range (Pierce) 1(4) fOSC 0.
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Device User Guide — 9S12C128DGV1/D V01.05 Cp VDDPLL R Phase Cs fosc 1 refdv+1 fref ∆ fcmp XFC Pin VCO KΦ KV fvco Detector Loop Divider 1 synr+1 1 2 Figure B-3 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table B-12. The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used for fOSC = 4MHz and a 25MHz bus clock.
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Device User Guide — 9S12C128DGV1/D V01.05 And finally the frequency relationship is defined as f VCO n = ------------- = 2 ⋅ ( synr + 1 ) f ref = 50 With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC=10kHz: 2 ⋅ π ⋅ n ⋅ fC R = ----------------------------- = 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ KΦ The capacitance Cs can now be calculated as: 2 0.516 2⋅ζ C s = ---------------------- ≈ --------------- ;( ζ = 0.9 ) = 5.19nF =~ 4.
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Device User Guide — 9S12C128DGV1/D V01.05 1 0 2 3 N-1 N tmin1 tnom tmax1 tminN tmaxN Figure B-4 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N).
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Device User Guide — 9S12C128DGV1/D V01.05 This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Table B-12 PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Self Clock Mode frequency fSCM 1 5.5 MHz 2 D VCO locking range fVCO 8 50 MHz 3 D |∆trk| 3 4 %1 4 D Lock Detection |∆Lock| 0 1.
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Device User Guide — 9S12C128DGV1/D V01.05 B.
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Device User Guide — 9S12C128DGV1/D V01.05 B.8 SPI Appendix C Electrical Specifications This section provides electrical parametrics and ratings for the SPI. In Table C-1 the measurement conditions are listed. Table C-1 Measurement Conditions Description Value Unit full drive mode — 50 pF (20% / 80%) VDDX V Drive mode Load capacitance CLOAD, on all outputs Thresholds for delay measurement points C.
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Device User Guide — 9S12C128DGV1/D V01.05 SS1 (OUTPUT) 1 2 12 13 12 13 3 SCK (CPOL = 0) (OUTPUT) 4 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 LSB IN 11 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure C-2 SPI Master Timing (CPHA=1) In Table C-2 the timing characteristics for master mode are listed.
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Device User Guide — 9S12C128DGV1/D V01.05 C.2 Slave Mode In Figure C-3 the timing diagram for slave mode with transmission format CPHA=0 is depicted. SS (INPUT) 1 12 13 12 13 3 SCK (CPOL = 0) (INPUT) 4 2 4 SCK (CPOL = 1) (INPUT) 10 8 7 MISO (OUTPUT) 9 see note SLAVE MSB 5 MOSI (INPUT) BIT 6 . . . 1 11 11 SLAVE LSB OUT SEE NOTE 6 MSB IN BIT 6 . . .
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Device User Guide — 9S12C128DGV1/D V01.05 SS (INPUT) 3 1 2 12 13 12 13 SCK (CPOL = 0) (INPUT) 4 4 SCK (CPOL = 1) (INPUT) see note SLAVE 7 MSB OUT 5 MOSI (INPUT) 8 11 9 MISO (OUTPUT) BIT 6 . . . 1 SLAVE LSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined! Figure C-4 SPI Slave Timing (CPHA=1) In Table C-3 the timing characteristics for slave mode are listed.
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Device User Guide — 9S12C128DGV1/D V01.05 C.3 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure C-5 with the actual timing values shown on table Table C-4. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. C.3.1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions.
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Device User Guide — 9S12C128DGV1/D V01.05 Table C-4 Expanded Bus Timing Characteristics (5V Range) Conditions are 4.75V < VDDX < 5.
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Device User Guide — 9S12C128DGV1/D V01.05 Table C-5 Expanded Bus Timing Characteristics (3.3V Range) Conditions are VDDX=3.3V+/-10%, Junction Temperature -40˚C to +140˚C, CLOAD = 50pF Num C Rating Symbol Min 1 D Frequency of operation (E-clock) 2 D Cycle time 3 D 4 Typ Max Unit fo 0 16.0 MHz tcyc 62.
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Device User Guide — 9S12C128DGV1/D V01.05 Appendix D Package Information D.1 General This section provides the physical dimensions of the MC9S12C Family and MC9S12GC Family packages 48LQFP, 52LQFP, 80QFP.
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Device User Guide — 9S12C128DGV1/D V01.05 D.2 80-pin QFP package L 60 41 61 D S M V P B C A-B D 0.20 M B B -A-,-B-,-D- 0.20 L H A-B -B- 0.05 D -A- S S S 40 DETAIL A DETAIL A 21 80 1 0.20 A H A-B M S F 20 -DD S 0.05 A-B J S 0.20 C A-B M S D S D M E DETAIL C C -H- -C- DATUM PLANE 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 ° 0.10 H SEATING PLANE N M G U T DATUM PLANE -H- R K W X DETAIL C Q NOTES: 1.
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Device User Guide — 9S12C128DGV1/D V01.05 D.3 52-pin LQFP package 4X 4X 13 TIPS 0.20 (0.008) H L-M N 0.20 (0.008) T L-M N -XX=L, M, N 52 40 1 CL 39 AB 3X G VIEW Y -L- -M- AB B B1 13 V VIEW Y BASE METAL F PLATING V1 27 14 J 26 U -N- A1 0.13 (0.005) M D T L-M S N S S1 SECTION AB-AB A S 4X C θ2 0.10 (0.004) T -H-TSEATING PLANE 4X θ3 VIEW AA 0.05 (0.002) S W 2X R θ1 R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E VIEW AA ROTATED 90 ° CLOCKWISE NOTES: 1.
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Device User Guide — 9S12C128DGV1/D V01.05 D.4 48-pin LQFP package 4X 0.200 AB T-U Z DETAIL Y A P A1 48 37 1 36 T U V B AE B1 12 25 13 AE V1 24 DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA Z S1 T, U, Z S DETAIL Y 4X 0.200 AC T-U Z 0.080 AC G AB AD AC MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 ° 7° 12 ° REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.
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Device User Guide — 9S12C128DGV1/D V01.05 Appendix E Emulation Information E.
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Device User Guide — 9S12C128DGV1/D V01.05 E.1.1 PK[2:0] / XADDR[16:14] PK2-PK0 provide the expanded address XADDR[16:14] for the external bus. Refer to the S12 Core user guide for detailed information about external address page access. Pin Name Function 1 Pin Name Function 2 Power Domain PK[2:0] XADDR[16:14] VDDX Internal Pull Resistor CTRL Reset State PUPKE Up Description Port K I/O Pins The reset state of DDRK in the S12_CORE is $00, configuring the pins as inputs.
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Device User Guide — 9S12C128DGV1/D V01.05 E.2 112-pin LQFP package 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X G X X=L, M OR N VIEW Y B L V M B1 28 57 29 F D 56 0.13 N S1 A S C2 VIEW AB θ2 0.050 0.10 T 112X SEATING PLANE θ3 T θ R R2 R 0.25 R1 GAGE PLANE (K) C1 E (Y) (Z) VIEW AB M BASE METAL T L-M N SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE A1 C AA J V1 θ1 NOTES: 1.
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