PowerDAQ User Manual PowerDAQ PD2/PDXI-MF/MFS and PDL-MF DAQ boards High-Performance Multifunction I/O boards for PCI and Compact PCI/PXI Computer January 2002 Edition © Copyright 1998-2002 Omega Engineering, Inc.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form by any means, electronic, mechanical, by photocopying, recording, or otherwise without prior written permission. Fourth Edition January 2002 Printing Information furnished in this manual is believed to be accurate and reliable. However, no responsibility is assumed for its use, or for any infringements of patents or other rights of third parties that may result from its use.
Table of Contents Table of Contents How to Use This Manual...................................................................... vi Introduction ...................................................................................... vi Who Should Read This Book?..........................................................viii Organization of This Manual...........................................................viii Conventions Used in This Manual ....................................................
Table of Contents Triggering ......................................................................................... 55 Digital Input/Output Subsystem ......................................................... 56 User Counter-Timer Subsystem...........................................................58 PD2/PDXI .........................................................................................58 PDL-MF ............................................................................................
Table of Contents Appendix E: Glossary .......................................................... 127 Glossary ..............................................................................................128 Index ...................................................................................................
Table of Contents List of Figures Figure 1: Control Panel Application ......................................................15 Figure 2: PD2- Board connector layout.............................................16 Figure 3: PDXI-MF Board connector layout ......................................16 Figure 4: PDL-MF- Board connector layout ...................................... 17 Figure 5: Single-ended Inputs and pseudo-differential inputs ........ 18 Figure 6: Differential Inputs ...............................
Table of Contents List of Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: 13: 14: 15: 16: 17: 16: 19: 20: 21: 22: 23: 24: 25: 26: 27: 28: 29: 30: PowerDAQ PD2-MF Models ...................................................4 PowerDAQ PD2-MFS Models.................................................. 5 PowerDAQ PD2-MF Models ..........
How to Use This Manual How to Use This Manual Introduction This manual describes the hardware of each of the PowerDAQ series of PCI and PXI DAQ boards.
How to Use This Manual PowerDAQ PDXI-MF Multifunction Series: PDXI-MF-16-2M/14H PDXI-MF-64-2M/14H PDXI-MF-16-400/14L PDXI-MF-16-400/14H PDXI-MF-64-400/14L PDXI-MF-64-400/14H PDXI-MF-16-1M/12L PDXI-MF-16-1M/12H PDXI-MF-64-1M/12L PDXI-MF-64-1M/12H PDXI-MF-16-150/16L PDXI-MF-16-150/16H PDXI-MF-16-333/16L PDXI-MF-16-333/16H PDXI-MF-64-333/16L PDXI-MF-64-333/16H PDXI-MF-16-500/16H PDXI-MF-16-500/16L PDXI-MF-64-500/16H PDXI-MF-64-500/16L PowerDAQ PDXI-MFS Multifunction Sample and Hold Series: PDXI-MFS-4-2M/14
How to Use This Manual Who Should Read This Book? This manual has been designed to benefit the user of PowerDAQ boards. To use PowerDAQ, it is assumed that you have basic PC skills, and that you are familiar with Microsoft Windows XP/2000/NT/ 9x, QNX or Linux/RTLinux/RTAI Linux operating environments.
How to Use This Manual The Glossary contains an alphabetical list and description of terms used in this manual. Index The Index alphabetically lists topics covered in this manual. Conventions Used in This Manual These are the main conventions used to help you get the most out of this manual: TIP Note Tips are designed to highlight quick ways to get the job done, or good ideas you might not discover on your own. Notes alert you to important information.
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1 Introduction 1
Chapter 1: Introduction About the PowerDAQ board This chapter describes the basic features of the PowerDAQ boards. Overview Thank you for purchasing a PowerDAQ board. The PowerDAQ board was designed from the ground-up to overcome the problems associated with previous ISA-based data acquisition boards. The associated PowerDAQ software has been written specifically for these products, using advanced software design.
Chapter 1: Introduction PowerDAQ Models PowerDAQ model numbers are derived from the following: [Family]-[Type Of Board]-[Channels]-[Speed]/[Resolution][Gain] Family: PD2- PowerDAQ PCI Board PDXI - PowerDAQ CompactPCI/PXI Boards The types of boards are: • • • • MF MFS AO DIO manual) Multifunction Multifunction with sample and hold Analog Output (requires PD2-AO user manual) Digital Input/Output (requires PD2-DIO user PowerDAQ PD2-MF Series: Model: Analog features: PD2-MF-16-2M/14H 2.
Chapter 1: Introduction PD2-MF-16-1M/12H 1.25 MS/s, 12-bit, 16SE/8DI A/D, Gains: 1,2,4,8; Two 12-bit D/A PD2-MF-64-1M/12L 1.25 MS/s, 12-bit, 64SE/32DI A/D, Gains: 1,10,100,1000; Two 12-bit D/A PD2-MF-64-1M/12H 1.
Chapter 1: Introduction PowerDAQ PD2-MFS Series: Model: Analog features: PD2-MFS-4-2M/14 1.65 MS/s, 14-bit, 4SE Simultaneous Sample & Hold; Two 12-bit D/As PD2-MFS-8-2M/14 1.
Chapter 1: Introduction Note The PD2-MFS series have onboard sample and hold amplifiers for each channel. These are part of the boards hardware design and do not require any software programming to be enabled. PowerDAQ PDXI-MF Series: Model: Analog features: PDXI-MF-16-2M/14H 2.2 MS/s, 14-bit, 16SE/8DI A/D, Gains: 1,2,4,8; Two 12-bit D/A PDXI-MF-64-2M/14H 2.
Chapter 1: Introduction PDXI-MF-16-333/16L 333 kS/s, 16-bit, 16SE/8DI A/D, Gains: 1,10,100,1000; Two 12-bit D/A PDXI-MF-16-333/16H 333 kS/s, 16-bit, 16SE/8DI A/D, Gains: 1,2,4,8; Two 12-bit D/A PDXI-MF-64-333/16L 333 kS/s, 16-bit, 64SE/32DI A/D, Gains: 1,10,100,1000; Two 12-bit D/A PDXI-MF-64-333/16H 333 kS/s, 16-bit, 64SE/32DI A/D, Gains: 1,2,4,8; Two 12-bit D/A PDXI-MF-16-500/16L 500 kS/s, 16-bit, 16SE/8DI A/D, Gains: 1,10,100,1000; Two 12-bit D/A PDXI-MF-16-500/16H 500 kS/s, 16-bit, 16SE/8DI
Chapter 1: Introduction Two 12-bit D/As PDXI-MFS-4-500/14 500 kS/s, 14-bit, 4SE Simultaneous Sample & Hold Two 12-bit D/As PDXI-MFS-8-500/14 500 kS/s, 14-bit, 8SE Simultaneous Sample & Hold Two 12-bit D/As PDXI-MFS-4-1M/12 1 MS/s, 12-bit, 4SE Simultaneous Sample & Hold; Two 12-bit D/As PDXI-MFS-8-1M/12 1 MS/s, 12-bit, 8SE Simultaneous Sample & Hold; Two 12-bit D/As PDXI-MFS-4-300/16 300 kS/s, 16-bit, 4SE Simultaneous Sample & Hold Two 12-bit D/As PDXI-MFS-8-300/16 300 kS/s, 16-bit, 8SE Simultane
Chapter 1: Introduction Upgrade Part Number: Additional features added: PD2-MFS-4-DG4 Upgrade any PD2-MFS board from 4SE to 4DI with Gains (1,2,5,10) PD2-MFS-8-DG8 Upgrade any PD2-MFS board from 8SE to 8DI with Gains (1,2,5,10) PDXI-MFS-4-DG4 Upgrade any PDXI-MFS board from 4SE to 4DI with Gains (1,2,5,10) PDXI-MFS-8-DG8 Upgrade any PDXI-MFS board from 8SE to 8DI with Gains (1,2,5,10) Table 5: PowerDAQ features: MFS Differential Upgrade Options D/A, DIO and Counter Timer All PowerDAQ PD2/
PowerDAQ PDL-MF Lab Board: This low cost Lab series board features: 150 kS/s, 16-bit, 16SE/16PDI, 8DI ; Two 12-bit D/As, 48 DIO and 3 CTM PDL-MF Table 7: PDL-MF board specifications The PDL-MF board have the following additional features: • • • • Analog Output Digital Input Digital Output Counter Timers Two 12-bit 200 kHz DAC’s 24 lines 24 lines Three 24-bit 16.
2 Installation and Configuration 11
Chapter 2: Installation and Configuration Before You Begin Before you install your PowerDAQ board, you should read and understand the following information. System Requirements: To install and run your PowerDAQ board, you must have the following: • • • A PC with PCI slots, a Pentium-class processor, and a BIOS that is compliant with PCI Local Bus Specification Revision 2.1 or greater Windows 95, 98, NT 4.
Chapter 2: Installation and Configuration Installing PowerDAQ Installing the Board: To install your PowerDAQ board: 1. Turn off your PC and remove the cover from your PC. 2. Locate an empty PCI slot and remove the slot cover on the back panel of your PC. Save the screw. 3. Insert the board into the PCI slot. 4. Fasten the board’s mounting bracket to your PC’s back panel with the screw that held the slot cover. 5. Inspect the board and ensure that it has been properly inserted in the slot. 6.
Chapter 2: Installation and Configuration Installing the Software To install the PowerDAQ SDK: 1. Start your PC and, if you are running Windows NT, login as an administrator. 2. Insert the PowerDAQ CD into your CD-ROM drive. Windows should automatically start the PowerDAQ Setup program. If you see the OMEGA logo and then the PowerDAQ welcome screen, go to step 6. 3. If the Setup program does not start automatically, select Run from the Start menu. 4. Enter D:\Setup.exe in the Open: textbox.
Chapter 2: Installation and Configuration 7. If the Setup program asks for information about third-party software packages that you do not have installed on your PC, leave the textbox blank and click the Next button. 8. When the installation is complete, you should restart your PC when prompted. Confirming the Installation Once you have installed the PowerDAQ board and software on your PC, you should confirm the installation: • Select Programs ! PowerDAQ ! Control Panel: from the Start menu.
Chapter 2: Installation and Configuration Configuring the PowerDAQ Board PowerDAQ 1 1 J2 Connector Logic Control Logic 1 J4 Connector Boot ROM DSP Low Noise DC-DC Onboard FIFO Onboard FIFO PowerDAQ II MF board Input Multiplexors J1 Connector 1 J 6 Conne ctor PCI Bus Figure 2: PD2- Board connector layout Low N oise DC- DC PXI PDXI-MF board DSP PowerDAQ Figure 3: PDXI-MF Board connector layout 16 CompactPCI Bu s Input M ultiple xors J2 Conn ecto r J1 C onnector 1
Chapter 2: Installation and Configuration PowerDAQ PDL-MF board 1 J1 Connector Boot ROM DSP PowerDAQ PCI Bus Figure 4: PDL-MF- Board connector layout Input Modes: The analog input section multiplexes the active input channels (64/16 single-ended or 32/8)differential) to a single 12- or 16-bit successive approximation analog-to-digital converter (ADC). Single-Ended: PowerDAQ boards can be configured to operate with either a singleended or differential input.
Chapter 2: Installation and Configuration Ain V1 Aout Agnd Figure 5: Single-ended Inputs and pseudo-differential inputs Note Unused channels should be shorted to ground using 0to 1-KΩ resistor. In pseudo-differential mode ground reference level is taken from remote system. Differential Inputs: Differential inputs allow up to 32 channels. Each differential channel uses two analog channels — one analog channel connects to the positive input of the programmable gain amplifier, and the other to the negative.
Chapter 2: Installation and Configuration Note Positive and negative differential inputs should not be driven by voltages more then AGND ±14V. When wiring applications to your PowerDAQ board, consider the following: • When working in an environment with electrical noise or when using gains, use differential input. • When working in an environment with electrical noise, use individually shielded twisted-pair wiring. • Physically separate wiring paths or conduits carrying power lines and signal lines.
Chapter 2: Installation and Configuration Note PXI boards are synchronized via PXI interface using the PXI Configurator program. Figure 7: PDXI Configurator PDL-MF board is synchronized via connections on a screwterminal panel. Note When using more than 4 PCI slots (standard PC), you will need a PCI bridge chip to support additional PCI slots. These bridge chips reduce the PCI bus throughput and will reduce your maximum sampling speed.
Chapter 2: Installation and Configuration Test Program: After you have wired an application to your PowerDAQ board, you should run the Simple Test program: 1. Select Programs " PowerDAQ " Simple Test : from the Start menu. The Simple Test dialog box is displayed. Figure 8: Simple Test Application 2. Use the Analog In, Analog Out, Digital In, Digital Out, and Counters tabs to observe your application running on the board.
Chapter 2: Installation and Configuration • 36-pin internal digital connector (J2) Manufactured by: Thomas and Betts PN# 609-3627 (Male) http://www.thomasandbetts.com/ • 36-pin internal digital connector (J4) Manufactured by: Thomas and Betts PN# 609-3627 (Male) http://www.thomasandbetts.com/ • 8-pin internal digital clock-signal connector (J6) Manufactured by: Adam Tech PN# PH2-08-TA-SMT http://www.adam-tech.
Chapter 2: Installation and Configuration J1 Connector (Single-Ended Mode) AGND AGND AGND AGND DGND AGND AIN55 AIN53 AIN51 AIN49 AGND AIN38 AIN36 AIN34 AIN33 AIN23 AIN21 AGND AIN18 AIN16 AIN6 AIN5 AIN3 AIN1 AGND DSP Trigger Input/AO External Clock *ADC Conversion Start Out/ Pacer clock out N/C AGND ADC Channel List Start Input / Burst Clock AIN62 AIN60 AIN59 AIN57 AIN47 AGND AIN44 AIN42 AIN40 AGND AIN29 AIN27 AIN25 AIN24 AIN14 AIN12 AGND AIN9 Table 8: 1 2 3 4 5 6 7 8 10 11 12 13 15 16 17 18 19 20 21 22 2
Chapter 2: Installation and Configuration J1 Connector (Differential Input Mode) AGND AGND AGND AGND DGND AGND AIN55 AIN53 AIN51 AIN49 AGND AIN38 AIN36 AIN34 AIN33 AIN23 AIN21 AGND AIN18 AIN16 AIN6 AIN5 AIN3 AIN1 AGND DSP Trigger Input/AO External Clock ADC Conversion Start Out/ Pacer clock out N/C AGND ADC Channel List Start Input / Burst Clock AIN54 Return AIN52 Return AIN51 Return AIN49 Return AIN39 Return AGND AIN36 Return AIN34 Return AIN32 Return AGND AIN21 Return AIN19 Return AIN17 Return AIN16 Retu
Chapter 2: Installation and Configuration Connector Pin Assignments for J2 The J2 digital internal connector contains eight digital input and eight digital output lines.
Chapter 2: Installation and Configuration Connector Pin Assignments for J4 The J4 Connector contains eight digital input and eight digital output lines.
Chapter 2: Installation and Configuration Connector Pin Assignments for J6 The J6 Interboard Synchronization Connector contains two pairs of clock signal lines: • • The ADC Clock (also known as the conversion clock. The Channel List Clock (also known as the scan clock or burst clock).
Chapter 2: Installation and Configuration Connector Pin Assignments for PDL-MF J1 TMR0 DGND TMR 1 DGND TMR2 DGND DOUT22 DOUT 20 1 2 3 4 51 52 53 54 5 55 6 56 7 57 8 DOUT18 9 DOUT16 10 DOUT14 1 1 DOUT12 DOUT10 DOUT 8 +5VPJ2 DOUT6 DOUT4 DOUT2 DOUT0 DIN22 DIN20 DIN18 DIN16 DGND DIN14 DIN12 DIN10 DIN8 DIN6 DIN4 DI N2 58 59 60 61 12 62 13 63 14 64 15 16 17 18 19 20 65 66 67 68 69 70 21 71 22 72 23 73 24 25 26 27 28 29 30 31 32 33 34 74 75 76 77 78 79 80 81 DIN0 82 AGND 83 AOUT 1 84 E XT_GND 35 85 AIN
Chapter 2: Installation and Configuration Connector Pin Assignments for PDXI J2 DOUT11 DIN13 DOUT12 DIN14 DOUT13 DIN15 DOUT14 DOUT15 DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND UCT0_CLK_IN UCT2_CLK_IN UCT0_OUT UCT2_OUT UCT0_GATE UCT2_GATE UCT1_CLK_IN 1 3 5 7 9 11 13 15 19 21 23 25 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
Chapter 2: Installation and Configuration PXI lines support Following PXI lines may be used for the synchronization: PXI_TR16 0..
3 Architecture 31
Chapter 3: Architecture Functional Overview PowerDAQ PD2-MF/MFS series have very extensive input modes, clocking and triggering capabilities as well as simultaneous subsystems operations. + Custom PGIA Gain Amp. Aln Power Conditioner Clock 12,14, 16-bit Sampling A/D Converter - User Counter Timer (82C54) Upgradable 1k Sample ADC FIFO 3 Gate 3 Out 3 Ext. Aln Conv Clock Aln Control Ext. Aln Scan Clock Channel List FIFO UCT Control Aln Clock Out Digital Input Buffer Latch DIn Control Ext.
Chapter 3: Architecture 16 or 64 Ch annel An alog Multiplexer (64) Aln Power Cond itioner Aln C alibration DACs + C ustom P GIA Gain A mp. 12,14 , 16-bit Sampling A/D Converter - Use r Counter Timer (82C5 4) U pgradable 1k Sample ADC FIFO C lock 3 Gate 3 Out 3 Ext. Aln Co nv Clock Aln Con trol Ext. Al n Scan Cl ock Channel Li st FIF O U CT C ontro l PowerDAQ II Data Acquisition Control and Timing Logic Ext. Aln Conv Clock Ext.
Chapter 3: Architecture + P GIA G ain A mp. Aln Power Cond itioner 16-bit Sampling A/D Converter - D SP Cou nter Ti mer (24) 16 Channel Analog Mu ltiplexer (3) Aln Calibration DACs Volt age R efe rence U pgradable 1k Sample ADC FIFO (24) A ln Clo ck Out Ext. Trigger Ext.
Chapter 3: Architecture • • • • • input channels simultaneously and then hold the acquired voltages while the ADC converts channel by channel. The Programmable Gain Amplifier (PGA) amplifies an input signal in order to provide adequate voltage to the analog-to-digital converter (ADC). The PGA amplification depends on the board model and can be software selected {1,2,4,8} or {1,10,100,1000} for MF series boards and {1,2,5,10} for MFS/PDL-MF boards when the differential gain (DG) option is installed.
Chapter 3: Architecture Digital Input/Output subsystem includes • • • • 16-bit input register to read logical levels on digital input lines (24-bit on PDL-MF) 8-bit Schmidt trigger to catch logic level changes on digital input lines (not present on PDL-MF) 16-bit output register to hold logical levels on digital output lines, once data has been written (24-bit on PDLMF) Interrupt mechanism to notify DSP about interrupt conditions User Counter-Timer subsystem includes • • • • 36 Three 16-bit Intel 82C54
Chapter 3: Architecture Analog Input Subsystem The analog input front-end multiplexes multiplex the first stage of the input channels (64/16 single-ended or 32/8 differential) into a single, 12, 14 or 16-bit successive approximation ADC. The A/D subsystem also includes input modes, polarity, gain settings, channel gains, channel queue, trigger and clocking control.
Chapter 3: Architecture channel and gain control MUX A ~ Analog input 0 … INA … PGA … to range control, calibration circuitry and ADC MUX B … ~ SE/DI/PD (PDL-MF only) switch control signal Analog input N Figure 13: PowerDAQ Multifunction Board front-end MFS boards have sample and hold amplifiers (SHA) located at the signal inputs. PD2-MFS-DGx options include a INA and PGA in the one device located on the back side of the board (Fig. 9).
Chapter 3: Architecture Analog input 0 ~ INA PGA MUX SHA … … to range control, calibration circuitry and ADC … Analog input N ~ INA SE/DF switch control signal PGA Gain contro l signal SHA S/H signal channel select signal Figure 14: PowerDAQ Sample and Hold Board front-end The major difference between MF and MFS boards are the SHAs. ‘Sample and Hold’ signal switches SHAs between ‘sampled’ and ‘hold’ states. When the SHA is in a sample state its output repeats its input.
Chapter 3: Architecture Channels Ch 0 Ch 1 Ch 2 t0 t1 Time t2 Moment of digitizing Signal level at the moment of Figure 15: PD2/PDXI Series Acquisition Process Channels Ch 0 Ch 1 Ch 2 Hold t0 t1 t2 Sampl Time Moment of digitizing Signal level Figure 16: PD2/PDXI Acquisition Process 40
Chapter 3: Architecture Figures 10 and 11 show the differences in data acquired using MF and MFS boards. When a sine wave is applied to the channels 0, 1 and 2. t0, t1 and t2 is the time when the channel reading has happened. Minimum delay between them is limited by the rated speed of the board and can be calculated as 1/rate in kS (seconds). Note PowerDAQ boards acquire channels sequentially at the rated speed that is referenced as the aggregate rate.
Chapter 3: Architecture Note Complete timing tables for all PowerDAQ boards are located Appendix A. Input Modes Single Ended The PowerDAQ boards operate with either a single-ended or a differential input configuration. Single-ended inputs allow up to 64 channels and share a common low side, which is the analog ground. Single ended inputs are shown diagrammatically in figure 12. See Table 5 for complete wiring instructions. Note Unused channels should be shorted to ground using a 0 to 1KOhm resistor.
Chapter 3: Architecture Differential Inputs Differential inputs allow up to 32 channels. (Differential inputs use two analog input channels. One channel connects to the positive input of the programmable gain amplifier and the other to the negative of the instrumentation amplifier). Note Both inputs must remain in AGND ±14V rails; otherwise input multiplexors lookup may occur.
Chapter 3: Architecture Input Ranges The PowerDAQ boards have four possible input ranges. These are global settings. UNIPOLAR BIPOLAR 0V to +10V - 10V to + 10V 0V to +5V* -5V to +5V * Not Available on PDL-MF board. Table 15: Input Range Table Gain Settings You can set a gain for each channel prior to acquisition. Depending on your board, there are three gain ranges.
Chapter 3: Architecture Channel List The Channel List contains sequences of channels to be acquired and their per channel gains. This sequence is known as the SCAN. The ADC Channel List can contain 1 to 256 channel entries (64 entries on PDLMF). Configuration data for each channel will include the channel selection, gain, and slow bit setting. Each Channel List block written clears and overwrites the previous settings.
Chapter 3: Architecture Clocking The PowerDAQ board has two selectable base frequencies (11 MHz and 33 MHz) to clock acquisition. Lower frequencies are obtained by dividing the base frequency by a 24-bit number (from 1 to 16M). To calculate the result frequency use following formula: Timebase = Base Frequency / (divisor + 1) Acquisition is clocked by two signals: conversion start (CV Start) and channel list start (CL Start).
Chapter 3: Architecture Clock combination CL Clock CV Clock source source SW Continuous Internal Continuous External Continuous Continuous Continuous Continuous or SW Internal Continuous External Internal Internal External External SW SW Typical use Acquire one set of data points (one scan). SW clock causes channel list to be executed once. The board will wait until next CL clock comes before restarting. Continuous acquisition with accurate timebase.
Chapter 3: Architecture Triggering The Analog input subsystem needs a trigger signal to start and stop acquisition. The Trigger signal is selectable. It can be either software command or an external pulse. External trigger is edge-sensitive. You can select rising or falling edge to be active. If the board is set up to start on an external trigger, all clocks will be ignored until the pulse comes. Acquisition continues until the stop trigger comes.
Chapter 3: Architecture Start trigger edge Stop trigger edge Rising Rising Rising Falling Falling Falling Falling Rising External TTL signal Acquisition started Acquisition stopped Table 20: External Trigger Modes ADC FIFO The PowerDAQ boards have an on-board FIFO. The FIFO could contain from 1kS (default) up to 64 kS depending on the FIFO option purchased. When the PowerDAQ board acquires data in continuous mode, data is written into the ADC FIFO.
Chapter 3: Architecture Data format Data in the data stream has the following format. Each two consecutive bytes contain a single sample from the A/D converter. Data is stored repeatedly sample by sample for all channels in the channel list. (Table 19 shows a PowerDAQ 16-bit board data format. For PowerDAQ 12-bit boards, only 12 LSBs (Least Significant Bits) are valid. PowerDAQ II boards automatically place zeroes in any unused bit locations.
Chapter 3: Architecture The following calculations should be performed to convert the raw, stored hexadecimal data to scaled (Voltage) data: 1. Determine the value of a single bit (“bit weight”) in Volts depending on the input range. PowerDAQ II (span)/65535 0 - 5V unipolar (5V span) 0.000076295 Volts/bit 0 - 10V unipolar (10V span) 0.000152590 Volts/bit +/-5V bipolar (10V span) 0.000152590 Volts/bit +/-10V bipolar (20V span) 0.000305180 Volts/bit Table 25: Bit Weight vs. Input Range 2.
Chapter 3: Architecture 7.
Chapter 3: Architecture Analog Output Subsystem Analog output subsystem contains two DACs (Digital to Analog Converters) and supports the following operating modes: Single Update The PowerDAQ PD2-MF(S) boards operate with either a single-update or streaming (waveform) output configuration. Single-update mode allows direct write access to the pair of 12-bit DACs. The update frequency is at least 1 kHz for the single update mode. This single update speed is dependent on your PC system speed.
Chapter 3: Architecture Auto-regeneration Waveform (circular waveform) Auto-regeneration waveform mode can be used to create fixed length waveforms (2048 samples maximum) without any host PC intervention after initialization of the subsystem. An application writes data to the buffer of the board and each time the end of buffer is reached, it starts to resend the same buffer again. Note Revision 3.x of PowerDAQ SDK allows to create waveforms up to the size of memory available in PC.
Chapter 3: Architecture The two Hex values for Aout channel 0 and 1 respectively can be combined to write to the analog output as follows: Value_To_Write = (HexValue1 << 12) OR (HexValue0) Clocking The analog output subsystem can be clocked using software command, internal 11 MHz base frequency or external trigger input line.
Chapter 3: Architecture Digital Input/Output Subsystem Digital Output subsystem contains one 16-bit (PD2/PDXI-MF/MFS) and 24-bit (PDL-MF) output register. The Digital outputs do not support clocked output, it can only be used in software-polled mode. The digital Input subsystem contains one 16-bit (PD2/PDXI-MF/MFS) and 24-bit (PDL-MF) input register. Digital inputs do not support clocked input, it can only be used in software-polled mode.
Chapter 3: Architecture Latch configuration is a 16-bit word, two bits for each one of eight sense inputs. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 F R F R F R F R F R F R F R F: 1 in this position, the inputs are sensitive to falling edge F Bit 0 R R: 1 in this position, the inputs are sensitive to rising edge Table 28: Digital Input Configuration Word (PD2/PDXI only) The Edge Detector and Latch Logic detect configured edges on the digital input lines. A 8-bit latch register has 1 bit per input line.
Chapter 3: Architecture User Counter-Timer Subsystem PD2/PDXI User counter-timer is based on the Intel 82C54 16-bit counter-timer chip. It contains three fully independent counter-timers. It’s fully dedicated for user applications and it is not used by any of the PowerDAQ systems. The logic allows you to select the clock and gate source for each of the three independent counter-timers. The countertimer outputs can generate interrupts to the host PC on change of their state.
Chapter 3: Architecture Special frequency measurement mode is implemented on PD2/PDXI boards. Using this mode external frequency may be measured in 0..65535 interval with absolute accuracy. The UCT is extremely useful in combination with the external clock and trigger lines. Using the UCT you can create very sophisticated acquisition setups. PDL-MF There are three DSP-based 24-bit counter/timers are available on the PDL-MF board. They are independent from each other and capable to generate interrupts.
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4 PowerDAQ Software Development Kit (PD-SDK) 61
Chapter 4: PowerDAQ Software (SDK) PowerDAQ Software PowerDAQ SDK Structure The installation will create the following directory structure in Program Files. This assumes you selected the SDK installation (default). PowerDAQ PowerDAQ root directory Applications Applications – ready to run Documentation Documents and manuals SDK Software developers Kit (SDK) Examples Examples (including applications with source code) C Builder Examples Borland C++ Builder 3.
Chapter 4: PowerDAQ Software (SDK) Location: \winnt\system32\drivers Files: pwrdaq.sys device driver PowerDAQ DLLs The PowerDAQ software includes various DLLs (dynamic linked libraries) for Windows operating systems. The location of these DLLs is as follows: Windows 9x operating System Location: \windows\system directory Files: PwrDAQ32.dll 32-bit DLL PwrDAQ16.dll 16-bit DLL Windows NT/2000/XP operating system Location: \winNT\system32 Files: PwrDAQ32.dll 32-bit DLL PwrDAQ16.
Chapter 4: PowerDAQ Software (SDK) /lib pwrdaq32.lib pd32bb.lib pd16bb.lib pd16bc45.lib pwrdaq16.lib - MSVC/MSVS v.5.x, 6.x Borland C Builder v.3.0, 4.0 16-bit Borland compilers 16-bit Borland C++ 4.5x 16-bit MSVC 1.5x PowerDAQ Include Files /include pdfw_def.h - firmware constant definition file for C/C++ pdfw_def.pas - firmware constant definition file for Borland Delphi pdfw_def.bas - firmware constant definition file for Visual Basic pwrdaq.h pwrdaq.pas pwrdaq.
Chapter 4: PowerDAQ Software (SDK) /include/vb3 pwrdaq16.bas Basic v.3.0 pdfw_def.bas pd_hcaps.bas daqdefs.bas - API function prototypes and structures file for Visual - firmware constant definition file for Visual Basic v.3.0 - boards capabilities definition file for Visual Basic v.3.0 - event word definition for Visual Basic v.3.0 /include/16-bit pwrdaq16.h C/C++ pwrdaq.h pdd_vb3.h pd_hcaps.
Chapter 4: PowerDAQ Software (SDK) Communication between user application and PowerDAQ PD2/PDXI/PDLboard PowerDAQ board (using the PD2 as an example) DSP PCI Bus Interface PowerDAQ driver PowerDAQ DLL samples Data Buffer events User Application Figure 21: Communication between user application and PowerDAQ board DSP – Digital Signal Processor controls all on board devices. User application communicates with the board via the PowerDAQ API encompassed into the PowerDAQ dynamic-link library (DLL).
Chapter 4: PowerDAQ Software (SDK) Programming subsystems All PowerDAQ subsystems have two modes of operation: • • Polled Event-based Polled mode is preferred when the application does not need to be notified about hardware events. Event-based mode allows you to write truly asynchronous applications. Opening the subsystems You have to open the driver, adapter and acquired subsystem before starting any operation and after completion, release the subsystem , close adapter and driver.
Chapter 4: PowerDAQ Software (SDK) Analog Input Subsystem There are many ways of working with the analog input subsystem. Before you start programming your application, consider how you would like to use the board. To select the input mode you need to OR your analog input configuration word with the input mode selection constants. Input Mode Single-Ended, 0..5V* Single-Ended, 0..10V Single-Ended, -5..+5V Single-Ended, -10..+10V Differential, 0..5V* Differential, 0..10V Differential, -5..
Chapter 4: PowerDAQ Software (SDK) Method A. Single scan operation See SDK Examples SimpleAin.c, simplescan.pas, simplescan.bas, vm64.pas, voltmeter.vbp, Vl16.cpp, PDGABoards.cpp This method is useful when you need to get one set of data points (one scan). This method allows you to acquire up to 100 scans per second, depending on the channel list size and maximal board speed. For example, applications such as a multi-channel voltmeter or sensor/thermocouple monitor are best suited for this method.
Chapter 4: PowerDAQ Software (SDK) Acquisition - call the acquisition sequence using the timer or in a program loop. Allow all points in the scan to be acquired, then calculate how much time it takes to digitize the entire channel list. One channel takes (1 / maximum_board_rate) (s) to be digitized. Do not forget the “Slow bit” adds additional time and some PowerDAQ MFS models have small additional “hold delay” time.
Chapter 4: PowerDAQ Software (SDK) Note The PowerDAQ boards have a special “slow bit” in the channel list. You might want to increase settling time for a particular channel with the high gain selected or a channel connected to a high output impedance signal. See your board specifications to calculate how much “slow bit” affects time needed to acquire that channel.
Chapter 4: PowerDAQ Software (SDK) Method B. Burst Buffered Acquisition – One Shot See SDK Examples Stream2.c, SimpleExample.vbp This method is useful when you need to get one-shot data acquisition with significant delay between acquisition runs. For example if you need an application like an oscilloscope or FFT , run acquisition one time, then stop it, analyze data and run it again Method B is for you. The size of the acquired data will required buffered A/D FIFO reads.
Chapter 4: PowerDAQ Software (SDK) dwCfg = (AIB_CVSTART0 | AIB_CVSTART1 | AIB_CLSTART1) for external clock Add AIB_INTCLSBASE constant to select 33 MHz base frequency instead of 11 MHz. Analog input event bits are defined in the file pwrdaq.h. Recommended event notification method: dwEvents = eFrameDone + eBufferDone + eBufferError + eStopped Your application will be notified when at least one frame is done. The buffer will be filled with data or buffer error, if an error occurs.
Chapter 4: PowerDAQ Software (SDK) • • your buffer with samples. When it returns event from the board you have to check what caused it Check events # _PdGetUserEvents(…) This function returns events for the subsystem specified (AnalogIn). Your code should analyze them and make a decision based on the result. An Event word could contain following flags: eFrameDone – get a frame of data eBufferDone + eStopped – acquisition is completed. All data is stored in the buffer. Data is available for analysis.
Chapter 4: PowerDAQ Software (SDK) # # _PdUnregisterBuffer(…) _PdFreeBuffer(…) Note External trigger. If you want your acquisition process to be started (or stopped) by an external pulse, connect your trigger source to the external trigger line and setup your analog input configuration word (dwAInCfg) with trigger settings as stated below.
Chapter 4: PowerDAQ Software (SDK) Trigger type Start trigger rising edge Start trigger falling edge Stop trigger rising edge Stop trigger falling edge Configuration AIB_STARTTRIG0 AIB_STARTTRIG0 + AIB_STARTTRIG1 AIB_STOPTRIG0 AIB_ STOPTRIG0+ AIB_STOPTRIG1 Table 29: Setting up External Trigger TIP 76 When the board is clocked from the low frequency internal timebase or external clock you might not get an immediate response because the board transfers data into the host memory only when the A/D FIFO bec
Chapter 4: PowerDAQ Software (SDK) Method C. Continuous Acquisition using ACB See SDK Examples Stream2.c Method C uses the PowerDAQ Advanced Circular Buffer mechanism. Acquisition runs continuously and each time an event occurs, the application takes control. You can create separate threads in your application to run the acquisition process.
Chapter 4: PowerDAQ Software (SDK) • • # WaitForSingleObject(hEventObject, Timeout) This function puts your program into a sleep mode and gives processor time to other processes. It is activated when the board signals an event or the timeout period has expired. The timeout period should be long enough to fill your buffer with samples.
Chapter 4: PowerDAQ Software (SDK) data in a one piece. This eliminates need of the user application to take care about data wrap around situations. _PdAInGetScans(…) has a side effect. When it’s called it marks frames it returns as “read”. This means that these frames can be reused for new data. • • Reset events # _PdSetUserEvents(…) Call this function to tell the driver that events are processed. Perform your application specific tasks. At this point you can do whatever you want with the data.
Chapter 4: PowerDAQ Software (SDK) TIP How to find optimal frame size for data acquisition? The following should be taken into account when selecting the frame size. Events consume host CPU and on-board DSP time and a small frame decreases overall system performance, on the other hand, larger frames decrease event rates and you might need faster response especially in control-loop applications. Performance-wise we recommend selecting frame sizes to receive 4 to 10 events/second.
Chapter 4: PowerDAQ Software (SDK) Method D. Retrieving ‘always-fresh’ data using ACB recycled mode See SDK Examples Stream2.c Another very useful feature introduced by the PowerDAQ API’s ACB is recycled buffering mode. It allows frames to be overwritten with new data without reading it. For example, you can run acquisition in continuous mode as it was explained in Method C.
Chapter 4: PowerDAQ Software (SDK) Method F. Multi-board operations. disk applications Stream to See SDK Examples stream4.c, SingleBoardStreamBasic.vbp A special cable to synchronize data acquisition from several boards is required ( PD-CBL-SYNC4 See Appendix) . This cable has one master connector and three slaves. (Custom versions of this cable are available for more than 4 boards in one system). It connects the CL and CV clock outputs from master board to CL and CV clock inputs of the slave boards.
Chapter 4: PowerDAQ Software (SDK) Method G. Combining Analog and Digital subsystems See SDK Examples SimpleTest.dpr The tricky part of combining digital and analog operations is the event handling. The PowerDAQ API has two sets of function to solve this. The first way is to set up all subsystem operations in a one thread and create an event using _PdSetPrivateEvent(…). This function creates a single event that is set when any subsystem needs attention.
Chapter 4: PowerDAQ Software (SDK) Method H. operation Synchronous stimulus/response This is subset of Method A. Some applications require a analog stimulus to be applied to a system and a response read. You can do this by setting the analog input to start the scan from an external clock (CL Clock line) and the analog output to output the next data point on the external trigger line pulse.
Chapter 4: PowerDAQ Software (SDK) When starting out, first recognize that a driver for a data acquisition card differs from one for a printer, CD-ROM or other peripheral in one fundamental way: real-time operation. A printer can wait before it gets the next data to print; a CD-ROM can pause for a short while to let some other activity go on. A data-acq board, though, typically is collecting data continuously and can pause only as long as its onboard FIFO can store intermediate results.
Chapter 4: PowerDAQ Software (SDK) Analog Output Subsystem There are four update modes for the analog output subsystem: • • • • Polled I/O update mode Buffered event-based waveform mode using PCI interrupts Buffered polled-I/O waveform mode Auto-retriggerable waveform mode Method A. Polled I/O update mode See SDK Examples SimpleAOut.cpp, SimpleTest.vbp This method allows you to update analog output values immediately (see Functional Overview for data format).
Chapter 4: PowerDAQ Software (SDK) Method B. Buffered event-based waveform mode using PCI interrupts See SDK Examples AOEvents.c, AEOutBlk.vbp Buffered event-based waveform mode allows you to generate any continuous waveforms. When the on-board output FIFO is less than half full, the board sends an interrupt to the host to request additional data. You can process analog output events in a separate event handler or in the common event handler for all subsystems.
Chapter 4: PowerDAQ Software (SDK) • Enable and start analog output waveform generation # _PdAOutEnableConv(…) use 1 as dwEnable # _PdAOutSwStartTrig(…) Note Use _PdAOutSwStartTrig() to start waveform generation by software. If you wish to synchronize analog output signal with external trigger, set appropriate flags in _PdAOutSetCfg() (flags AOB_STARTTRIG0, AOB_STARTTRIG1, AOB_STOPTRIG0, AOB_STOPTRIG1 has the same functionality as for the analog input subsystem).
Chapter 4: PowerDAQ Software (SDK) Stop acquisition • Issue a stop trigger if external trigger was not configured # _PdAOutSwStopTrig() • Disable D/A conversions # _PdAOutEnableConv(…) use 0 (false) as dwEnable De-Initialize • Disable interrupt (if no other subsystem uses interrupt at that time) # _PdAdapterEnableInterrupt(…) use dwEnable = 0 • Release event object # _PdAOutClearPrivateEvent(…) • Clear subsystem and set both outputs to zero volt # _PdAOutReset(…) 89
Chapter 4: PowerDAQ Software (SDK) Method C. Buffered polled-I/O waveform mode See SDK Example AoutBlock.vbp Buffered polled-I/O waveform mode does not require an event handler. Instead, the analog output subsystem is initialized and the initial data is written to the output buffer (2048 samples maximum). After the subsystem and buffer have been initialized, the application continues to write samples to the buffer.
Chapter 4: PowerDAQ Software (SDK) • Continue waveform generation # _PdAOutEnableConv(…) use 1 as dwEnable # _PdAOutSwStartTrig(…) • Sleep for a while using Sleep(…) Win32 API call to give up processor time to other processes # Sleep(n) – time for process to sleep depends on output rate.
Chapter 4: PowerDAQ Software (SDK) Method D. Auto-retriggerable waveform mode (no CPU usage) See SDK Example SimpleTest.dpr Auto-regeneration waveform mode is used to create fixed-length waveforms (2048 samples/scans maximum) without using any CPU cycles in the host PC. After an application writes datum to the buffer, the board starts to output the waveform, which will be restarted automatically when the buffer pointer reaches the end of the buffer.
Chapter 4: PowerDAQ Software (SDK) # # _PdAOutEnableConv(…) use 1 as dwEnable _PdAOutSwStartTrig(…) Stop acquisition • Reset analog output subsystem _PDAOutReset(…) Note Board will stop waveform generation when it reaches the end of the buffer.
Chapter 4: PowerDAQ Software (SDK) Digital Input/Output Subsystems The digital input/output subsystem can be used in two ways. Method A: 16-bit digital input and digital output polled configuration. Note: The digital subsystem has no clocked operations available. Method B: Set up an input configuration and the digital input fires an event when it detects a specified edge on the selected input line. The eight lower lines are edge-sensitive. Method A. Polled I/O See SDK Example SimpleTest.
Chapter 4: PowerDAQ Software (SDK) • • Configuration word is explained in Digital I/O Architecture section of this manual. Read status of digital input latch # _PdDInGetStatus(…)function returns current state of the digital input lines in a single byte and digital input latch register in the other byte. If the specified edge was detected, the latch contains “1” in the appropriate bit.
Chapter 4: PowerDAQ Software (SDK) Method B. Generate event when specified edge is detected See SDK Example DIEvents.c This method is very similar in setup parameters with Method A. The difference is that you should additionally enable and set up event notification. Like the analog output subsystem, the digital input can share the same event handler with other subsystems or have its own event handler.
Chapter 4: PowerDAQ Software (SDK) # • • • _PdGetUserEvent(…) should return eDInEvent flag in the status word. Read status of digital input latch # _PdDInGetStatus(…) function returns current state of the digital input lines in a one byte and digital input latch register in the other byte. If specified edge was detected, the latch contains “1” in the appropriate bit.
Chapter 4: PowerDAQ Software (SDK) User Counter-Timer Subsystem PD2/PDXI The User Counter-Timer subsystem can be used in many different ways. Counter-timers are fully dedicated to the user tasks. Three on-board counter-timers can be set up to any configurable Intel 82C54 chip mode. Using counter-timers output to control analog input and analog output subsystems allows you to create setups to solve very sophisticated data acquisition tasks.
Chapter 4: PowerDAQ Software (SDK) Initialization • Reset UCT subsystem # _PdUctReset(…)clears register latch and configuration Set up UCT configuration • Set up edge-sensivity configuration # _PdUctSetCfg(…)use this function to set up UCT configuration. Refer to uct_progr.c for bit definition # _PdAdapterEnableInterrupt(…) with dwEnable = 1 # _PdUctSetPrivateEvent(…)set up event object # _PdSetUserEvent(…) use CounterTimer as a subsystem name.
Chapter 4: PowerDAQ Software (SDK) # _PdUctReset(…) Note To write to the counter-timer, an input clock must be applied to appropriate UCT. You can control the gate using the API call _PdUctSwSetGate(…).
Chapter 4: PowerDAQ Software (SDK) PowerDAQ Example Programs A complete range of sample programs with source code is included with your PowerDAQ board. For complete details on programming the PowerDAQ board, refer to the PowerDAQ Software Manual Note Listed below are summary of a few examples. Please review the installation directories for new examples or online at www.PowerDAQ.com Visual C++ examples Versions supported: VC 1.5 (16 bit), VC 5 and 6 (32-bit) Examples supplied: VM16.
Chapter 4: PowerDAQ Software (SDK) SimpleTest application which allows Analog Input, Analog Output, Digital Input, Digital Output and Counter Timer operation. This program also allows simultaneous subsystem operation. Borland C++ Builder examples Versions supported: Inprise/Borland 3.5 Examples supplied: Stream4.exe – continuous acquisition and stream to disk application. Note The include files for the above languages may have the same file name. This means they can be used with either language.
Chapter 4: PowerDAQ Software (SDK) Third Party Software Support The PowerDAQ CD contains drivers for most of the popular third party software packages. The installation procedure automatically detects if you have installed any of the third party packages and will install the drivers and examples automatically If you install a third party software package after installing the PowerDAQ software, you must re-install the PowerDAQ software to include support for this new third party package.
5 Calibration 105
Chapter 5: Calibration Calibration Overview This chapter contains information on the calibration procedures for the A/D and D/A subsystems on the PowerDAQ series of boards. When to calibrate These procedures should be performed at six-month intervals. It is highly recommended to send board back to OMEGA, Inc. calibration facility for recalibration. Note Allow the host PC and the board to warm up for at least one hour before calibration.
A Appendix A: Specifications 107
Appendix A: Specifications PowerDAQ II Board Acquisition Timing The table below shows continuous acquisition and timing delays controlled by the PowerDAQ II onboard logic. These timings guarantee accuracy.
Appendix A: Specifications PDXI-MF Series Timing: ID OMEGA Model Res / Speed / Gain 1 2 3 4 5 6 7 8 9 A B C D E F PDXI-MF-1M/12L PDXI-MF-1M/12H PDXI-MF-400/14L PDXI-MF-400/14H PDXI-MF-800/14L PDXI-MF-800/14H PDXI-MF-2M/14H PDXI-MF-150/16L PDXI-MF-150/16H PDXI-MF-100/16L PDXI-MF-100/16H PDXI-MF-333/16L PDXI-MF-333/16H PDXI-MF-500/16L PDXI-MF-500/16H 12, 12, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 1.25 MHz, 1.25 MHz, 400 kHz, 400 kHz, 800 kHz, 800 kHz, 1.
Appendix A: Specifications
B Appendix B: Accessories 111
Appendix B: Accessories Accessories The following accessories are available for the PowerDAQ PD2/PXI boards. Screw Terminal Panels (PDL-MF only) PDL-STP The PDL-STP is a 16-channel screw-terminal pane with 50-way header for direct connection to 50way cables. The PDL-STP includes metal standoffs for use on a desktop or for mounting on a custom panel.
Appendix B: Accessories BNC Connection Panels (PD2/PDXI) PD-BNC-16 16-channel BNC panel for 16-channel boards PD-BNC-16-KIT Complete Kit: Includes PD-BNC-16, PD-CBL-96, PD-CBL-37 (for 16-channel boards) PD-BNC-64 64-channel BNC panel for 64-channel boards PD-BNC-64-KIT Complete Kit: Includes PD-BNC-64, PD-CBL96,PD-CBL-37 (for 64-channel boards) Note See appendix C, Application Notes for additional PDBNC wiring options.
Appendix B: Accessories Thermocouple Input Racks (All) PD-TCR-16-J 16-channel Isolated Thermocouple Input Rack— Type J PD-TCR-16-K 16-channel Isolated Thermocouple Input Rack— Type K 5B/7B/OEM (PD2/PDXI) Distribution Panels PD-5BCONN Connects 16- or 64-channel PowerDAQ II board to 1 to 4, 5B-xx racks PD-7BCONN Connects 16- or 64-channel PowerDAQ II board to 1 to 4, 7B-xx racks PD-100HDR Connects 16- or 64-channel PowerDAQ II board to two 50-way IDC headers Mating cables, connectors, connection
Appendix B: Accessories Cables (PD2/PDXI) PD-CBL-96 96-way pinless, 1m round, shielded cable with metal cover plates PD-CBL-96-6FT 96-way pinless, 6 ft round, shielded cable with metal cover plates PD-CBL-96-9FT 96-way pinless, 9 ft round, shielded cable with metal cover plates PD-CBL-37 DIO cable set: 37-way, 1m D-sub cable, Internal cable with mounting bracket PD-CBL-37BRKT DIO cable: 37-way, 1m internal cable with mounting bracket PD-CBL-37TP DIO Twisted-pair cable set: 37-way, 1m D-sub cable
Appendix B: Accessories Signal (All) Conditioning Expansion Units PD-SCXU-F8 8 Anti-aliasing filters PD-SCXU-F16 16 Anti-aliasing filters PD-SCXU-G8 8 Programmable gain amplifiers PD-SCXU-G16 16 Programmable gain amplifiers PD-SCXU-FP8 8 Anti-aliasing filters combined with 8 programmable gain amplifiers PD-SCXU-F8-P8 8 Anti-aliasing filters and 8 programmable gain amplifies (not combined) PD-SCXU-FG16 16 Anti-aliasing filters combined with 16 programmable gain amplifiers PD-SCXU-TJ8 8 J-
C Appendix C: Application Notes 117
Appendix C: Application Notes Application Note: 1 PowerDAQ Advanced Circular Buffer (ACB) The Advanced Circular Buffer solves many of the problems associated with high throughput data acquisition on a multi-threaded /multitasking OS. For simplicity, data acquisition as an input process is discussed, however, the same concepts can be applied to output signal generation.
Appendix C: Application Notes To receive notification on a sample or scan count boundary, the buffer is segmented into frames. Whenever the data transferred to the buffer crosses a frame boundary, the driver sends an event to the application. This event "wakes up" the application thread that is responsible for processing data in the buffer. To keep the frame boundaries at fixed buffer locations, the buffer size should be a multiple of the frame size.
Appendix C: Application Notes Circular Buffer In the Circular Buffer mode the buffer head and tail wrap to the beginning of the buffer when the end is reached. Data is written at the location pointed to by head and the head pointer is incremented and likewise data is read from the location pointed to by the tail and the tail pointer is incremented. When the head pointer wraps around and reaches the tail pointer, then the buffer is considered full and acquisition stops with a buffer overflow condition.
Appendix C: Application Notes Driver Asserts Frame Done Events When Data Written Passes Frame Boundry Advanced Circular Buffer Board/Driver Write New Data At Buffer Head Buffer Head Application Reads Data From Buffer Tail Buffer Tail Frame Markers Figure 22: Advanced Circular Buffer While the Advanced Circular Buffer may appear as a much different buffering mechanism as compared to the much simpler single and double buffer mechanisms, in essence, it is actually a superset of the simpler buffers.
Appendix C: Application Notes Application Note: 2 PD-BNC-xx wiring options: Voltage dividers In order to build a voltage divider, resistors should be installed into the R0A, R8A and R0C positions, for the channel 0 and channel 8 pair, and similarly for the other pairs. Note that as supplied by the factory, the RxA resistors have zero Ohm jumpers installed.
D Appendix D: Warranty 123
Appendix D: Warranty Overview IBM, IBM PC/XT/AT and IBM PS/2 are trademarks of International Business Machine Corporation. BASIC is a trademark of Dartmouth College. Microsoft is a trademark of Microsoft Corporation.
Appendix D: Warranty Omega Engineering warrants that the products furnished under this agreement will be free from material defects for a period of one year from the date of shipment. The customer shall provide notice to Omega Engineering of such defect within one week after the Customer’s discovery of such defect.
E Appendix E: Glossary 127
Appendix E: Glossary Glossary A A/D Analog-to-digital. ADC Analog-to-Digital Converter. An integrated circuit that converts an analog voltage to a digital number. ADC Conversion The process of converting a single analog input to a digital value. ADC Conversion Start Signal used to start the conversion process of an analog input to a digital value. The source of this signal can be either an internal ADC synchronous clock or an external asynchronous signal.
Appendix E: Glossary (2) Software - A property of a function that begins an operation and returns prior to the completion or termination of the operation. B Background Acquisition Data is acquired by a DAQ system while another program or processing routine is running without apparent interruption. Base Address A memory address that serves as the starting address for programmable registers. All other addresses are located by adding to the base address.
Appendix E: Glossary amount of memory required to store one byte of data. C Cache High-speed processor memory that buffers commonly used instructions or data to increase processing throughput. Channel List A variable length list of 1 to 256 channels and their associated gains and “slow bits” specifying which analog input channels to convert to digital values. In continuous A/D acquisition mode the list wraps around to the first channel after it reaches the end.
Appendix E: Glossary Component Software An application that contains one or more component objects that can freely interact with other component software. Examples include OLEenabled applications such as Microsoft Visual Basic and OLE Controls for virtual instrumentation in Component Works. Conversion Time The time required, in an analog input or output system, from the moment a channel is interrogated (such as with a read instruction) to the moment that accurate data is available.
Appendix E: Glossary DAC Conversion Start signal used to start the conversion process of digital value to an analog output. The source of this signal can be either an internal DAC synchronous clock or an external asynchronous signal. This is a common signal fed to both DACs.
Appendix E: Glossary DNL Differential Non-linearity: A measure in LSB of the worst-case deviation of code widths from their ideal value of 1 LSB. DMA Direct Memory Access: A method by which data can be transferred to/from computer memory from/to a device or memory on the bus while the processor does something else. DMA is the fastest method of transferring data to/from computer memory. Drivers Software that controls a specific hardware device, such as DAQ boards. DSP Digital signal processing.
Appendix E: Glossary opaque areas, a light source, and a photo detector. EPROM Erasable Programmable Read-Only Memory: ROM that can be erased (usually by ultraviolet light exposure) and reprogrammed. Events Signals or interrupts generated by a device to notify another device of an asynchronous event. The contents of events are device-dependent. External Trigger A voltage pulse from an external source that triggers an event such as A/D conversion.
Appendix E: Glossary program by means of graphical screen displays. GUIs can resemble the front panels of instruments or other objects associated with a computer program. H Handler A device driver that is installed as part of the operating system of the computer. Hardware The physical components of a computer system, such as the circuit boards, plug-in boards, chassis, enclosures, peripherals, cables, and so on.
Appendix E: Glossary Integral Control A control action that eliminates the offset inherent in proportional control. Integrating ADC An ADC whose output code represents the average value of the input voltage over a given time interval. Interpreter A software utility that executes source code from a high-level language such as Basic, C or Pascal, by reading one line at a time and executing the specified operation. See also Compiler.
Appendix E: Glossary K Kilo, the prefix for 1,024, or 210, used with B in quantifying data or computer memory. kbytes/s A unit for data transfer that means 1,000 or 103 bytes/s. L Linearity The adherence of device response to the equation R = KS, where R =response, S = stimulus, and K = a constant. LSB Least significant bit.
Appendix E: Glossary N Noise An undesirable electrical signal. Noise comes from external sources such as the AC power line, motors, generators, transformers, fluorescent lights, soldering irons, CRT dis-plays, computers, electrical storms, welders, radio transmitters, and internal sources such as semiconductors, resistors, and capacitors. O OLE Object Linking and Embedding: A set of system services that provides a means for applications to interact and interoperate.
Appendix E: Glossary Output Settling Time The amount of time required for the analog output voltage to reach its final value within specified limits. Output Slew Rate The maximum rate of change of analog output voltage from one level to another. Overhead The amount of computer processing resources, such as time and/or memory, required to accomplish a task.
Appendix E: Glossary networking protocols, and specialpurpose digital and analog I/O ports. Plug and Play ISA A specification prepared by Microsoft, Intel, and other PC-related companies that will result in PCs with plug-in boards that can be fully configured in software, without jumpers or switches on the boards. Port A communications connection on a computer or a remote controller.
Appendix E: Glossary through a communications such as the GPIB. channel, Q Quantization Error The inherent uncertainty in digitizing an analog value due to the finite resolution of the conversion process. R Real Time A property of an event or system in which data is processed as it is acquired in-stead of being accumulated and processed at a later time. Relative Accuracy A measure in LSB of the accuracy of an ADC. It includes all non-linearity and quantization errors.
Appendix E: Glossary SE Single-Ended: A term used to describe an analog input that is measured with respect to a common ground. Scan Set of the channels, or data point, to be acquired at the same time. Self-Calibrating DAQ board that calibrates its own A/D and D/A circuits with and external reference source. Sensor A device that responds to a physical stimulus (heat, light, sound, pressure, motion, flow, and so on), and produces a corresponding electrical signal.
Appendix E: Glossary Subroutine A set of software instructions executed by a single line of code that may have input and/or output parameters. Successive-Approximation ADC An ADC that sequentially compares a series of binary-weighted values with an analog input to produce an output digital word in n steps, where n is the bit resolution of the ADC. Synchronous A property of a function that begins an operation and returns only when the operation is complete.
Appendix E: Glossary Thermocouple A temperature sensor created by joining two dissimilar metals. The junction produces a small voltage as a function of the temperature. Throughput Rate The data, measured in bytes/s, for a given continuous operation. Transducer A device that responds to a physical stimulus (heat, light, sound, pressure, motion, flow, and so on), and produces a corresponding electrical signal.
Index Index _ _PdAdapterEnableInterrupt ... 77 _PdAInAsyncInit.....................65 _PdAInAsyncStart ........... 64, 65 _PdAInAsyncStop...................65 _PdAInClearPrivateEvent........65 _PdAInEnableConv.................59 _PdAInEnableTimer................ 70 _PdAInGet Samples ...............60 _PdAInSetCfg ........................59 _PdAInSetChList.....................59 _PdAinSetPrivateEvent ...........63 _PdAInSetPrivateEvent........... 73 _PdAInStartTrig......................59 _PdAInSwClStart ..
Index C F Calibration ..............................95 Calibration DACs ....................26 CE Mark CE Mark Certification ........ 117 Channel list.......................26, 37 Channel list D/A ....................45 Circular waveform..................45 CL start clock .........................38 Clock source ........................... 27 Clocking........................... 26, 38 Clocking D/A..........................46 Combining analog and digital subsystems .........................
Index M Maximum per channel rate.... 32 Multi-board operation ........... 72 Multiplexors............................28 Multithreaded applications .....71 P PD CAL Application ................95 pd_hcaps.bas .........................55 pd_hcaps.h ..................... 54, 55 pd_hcaps.pas .........................54 PD2-MF Series ..........................3 PD2-MFS Series ........................4 PD2-MFS Series Gain Option ...5 PD2-MFS-DGx ........................29 PdAInAsyncTerm ....................
Index voltage divider....................... 114 W WaitForSingleObject ...............64 WaitForSingleObject ............... 73 Warranty ............................... 116 Waveform – auto retriggerable .......................82 Waveform – buffered event based .................................. 77 Waveform – buffered polled I/O ..................................... 80 Windows 9x ...........................
Index 149
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