Processor Users Manual

ManualsBrandsMotorola ManualsComputer HardwareMPC8260

MPC8260UM/D

4/1999

Rev. 0

MPC8260 PowerQUICC II

UserÕs Manual

Summary of content (1006 pages)

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MPC8260UM/D 4/1999 Rev.
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PowerQUICC II, Mfax, and DigitalDNA are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, PowerPC 604e, and RS/6000 are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. I2C is a registered trademark of Philips Semiconductors Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors.
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Overview PowerPC Processor Core Memory Map System Interface Unit (SIU) Reset External Signals 60x Signals The 60x Bus Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A GLO IND Overview PowerPC Processor Core Memory Map System Interface Unit (SIU) Reset External Signals 60x Signals The 60x Bus Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.
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CONTENTS Paragraph Number Title Page Number About This Book Before Using this ManualÑImportant Note.......................................................... lv Audience ................................................................................................................ lv Organization.......................................................................................................... lvi Suggested Reading...................................................................................
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CONTENTS Paragraph Number 1.7.2 1.7.2.1 1.7.2.2 1.7.2.3 Title Page Number Bus Configurations.........................................................................................1-15 Basic System ..............................................................................................1-15 High-Performance Communication ...........................................................1-16 High-Performance System Microprocessor ...............................................
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CONTENTS Paragraph Number 2.5.1 2.5.2 2.5.3 2.6 2.6.1 2.6.2 2.7 2.8 Title Page Number PowerPC Exception Model ............................................................................2-22 MPC8260 Implementation-Specific Exception Model..................................2-23 Exception Priorities........................................................................................2-26 Memory Management ........................................................................................
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CONTENTS Paragraph Number 4.3.2.2 4.3.2.3 4.3.2.4 4.3.2.5 4.3.2.6 4.3.2.7 4.3.2.8 4.3.2.9 4.3.2.10 4.3.2.11 4.3.2.12 4.3.2.13 4.3.2.14 4.3.2.15 4.3.2.16 4.3.3 4.3.3.1 4.3.3.2 4.3.3.3 4.4 Title Page Number 60x Bus Arbiter Configuration Register (PPC_ACR) ...............................4-28 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL) .............4-28 Local Bus Arbiter Configuration Register (LCL_ACR) ............................
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CONTENTS Paragraph Number Title Page Number External Signals 6.1 6.2 Functional Pinout .................................................................................................6-1 Signal Descriptions ..............................................................................................6-2 Chapter 7 60x Signals 7.1 7.2 7.2.1 7.2.1.1 7.2.1.1.1 7.2.1.1.2 7.2.1.2 7.2.1.2.1 7.2.1.2.2 7.2.1.3 7.2.1.3.1 7.2.1.3.2 7.2.2 7.2.2.1 7.2.2.1.1 7.2.2.2 7.2.3 7.2.3.1 7.2.3.1.1 7.2.3.1.2 7.2.4 7.2.4.
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CONTENTS Paragraph Number 7.2.5.2 7.2.5.2.1 7.2.5.2.2 7.2.6 7.2.6.1 7.2.6.1.1 7.2.6.1.2 7.2.6.2 7.2.6.2.1 7.2.6.2.2 7.2.7 7.2.7.1 7.2.7.1.1 7.2.7.1.2 7.2.7.2 7.2.7.2.1 7.2.7.2.2 7.2.8 7.2.8.1 7.2.8.1.1 7.2.8.1.2 7.2.8.2 7.2.8.2.1 7.2.8.2.2 7.2.8.3 7.2.8.3.1 7.2.8.3.2 Title Page Number Address Retry (ARTRY)............................................................................7-11 Address Retry (ARTRY)ÑOutput.........................................................7-11 Address Retry (ARTRY)ÑInput ...
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CONTENTS Paragraph Number 8.4.3.1 8.4.3.2 8.4.3.3 8.4.3.4 8.4.3.5 8.4.3.6 8.4.3.7 8.4.3.8 8.4.4 8.4.4.1 8.4.4.2 8.4.5 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.6 8.7 8.7.1 8.7.2 8.8 Title Page Number Transfer Type Signal (TT[0Ð4]) Encoding ................................................8-10 Transfer Code Signals TC[0Ð2] .................................................................8-13 TBST and TSIZ[0Ð3] Signals and Size of Transfer...................................
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CONTENTS Paragraph Number 9.8 9.9 9.10 Title Page Number System Clock Control Register (SCCR) ..............................................................9-8 System Clock Mode Register (SCMR) ................................................................9-9 Basic Power Structure ........................................................................................9-10 Chapter 10 Memory Controller 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.2.8 10.2.9 10.2.10 10.2.11 10.2.12 10.2.
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CONTENTS Paragraph Number 10.4.5 10.4.5.1 10.4.6 10.4.6.1 10.4.6.2 10.4.6.3 10.4.6.4 10.4.6.5 10.4.6.6 10.4.6.7 10.4.6.8 10.4.7 10.4.8 10.4.9 10.4.10 10.4.11 10.4.12 10.4.12.1 10.4.13 10.5 10.5.1 10.5.1.1 10.5.1.2 10.5.1.3 10.5.1.4 10.5.1.5 10.5.1.6 10.5.2 10.5.3 10.5.4 10.6 10.6.1 10.6.1.1 10.6.1.2 10.6.1.3 10.6.1.4 10.6.2 10.6.3 10.6.4 10.6.4.1 10.6.4.1.1 10.6.4.1.2 10.6.4.1.3 MOTOROLA Title Page Number Bank Interleaving .................................................................................
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CONTENTS Paragraph Number 10.6.4.1.4 10.6.4.1.5 10.6.4.2 10.6.4.3 10.6.4.4 10.6.4.5 10.6.4.6 10.6.5 10.6.6 10.7 10.7.0.1 10.8 10.8.1 10.8.2 10.9 10.9.1 10.9.2 10.9.3 10.9.4 10.9.5 10.9.6 10.9.6.1 Title Page Number Loop Control ........................................................................................10-76 Repeat Execution of Current RAM Word (REDO) ............................10-76 Address Multiplexing ...............................................................................
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CONTENTS Paragraph Number 12.5 12.6 Title Page Number MPC8260 Restrictions .....................................................................................12-30 Nonscan Chain Operation ................................................................................12-30 Chapter 13 Communications Processor Module Overview 13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.3.8 13.3.9 13.4 13.4.1 13.4.1.1 13.4.2 13.4.3 13.5 13.5.1 13.5.2 13.6 13.6.1 13.6.2 13.6.3 13.6.4 13.6.5 13.6.
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CONTENTS Paragraph Number Title Page Number Chapter 14 Serial Interface with Time-Slot Assigner 14.1 14.2 14.3 14.4 14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 14.5 14.5.1 14.5.2 14.5.3 14.5.4 14.5.5 14.6 14.6.1 14.6.2 14.7 14.7.1 14.7.2 14.7.2.1 14.7.2.2 Features...............................................................................................................14-3 Overview ............................................................................................................
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CONTENTS Paragraph Number Title Page Number Chapter 16 Baud-Rate Generators (BRGs) 16.1 16.2 16.3 BRG Configuration Registers 1Ð8 (BRGCx).....................................................16-2 Autobaud Operation on a UART .......................................................................16-4 UART Baud Rate Examples ..............................................................................16-5 Chapter 17 Timers 17.1 17.2 17.2.1 17.2.2 17.2.3 17.2.4 17.2.5 17.2.6 17.2.7 Features ............
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CONTENTS Paragraph Number 18.5.3 18.6 18.7 18.7.1 18.7.1.1 18.7.1.2 18.7.2 18.8 18.8.1 18.8.2 18.8.2.1 18.8.2.2 18.8.2.3 18.8.3 18.8.4 18.8.5 18.9 18.9.1 18.9.2 18.10 18.10.1 18.11 18.12 18.12.1 18.12.2 Title Page Number Controlling 60x Bus Bandwidth...................................................................18-12 IDMA Priorities................................................................................................18-12 IDMA Interface Signals...............................................
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CONTENTS Paragraph Number 19.3.5.2 19.3.6 19.3.6.1 19.3.7 19.3.8 19.3.8.1 19.3.8.2 19.3.8.3 19.3.8.4 19.3.8.5 19.3.9 Title Page Number Asynchronous Protocols ..........................................................................19-21 Digital Phase-Locked Loop (DPLL) Operation...........................................19-22 Encoding Data with a DPLL ....................................................................19-24 Clock Glitch Detection..........................................................
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CONTENTS Paragraph Number Title Page Number Chapter 21 SCC HDLC Mode 21.1 21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.9 21.10 21.11 21.12 21.13 21.13.1 21.13.2 21.14 21.14.1 21.14.2 21.14.3 21.14.4 21.14.5 21.14.6 21.14.6.1 21.14.6.2 SCC HDLC Features ..........................................................................................21-2 SCC HDLC Channel Frame Transmission.........................................................21-2 SCC HDLC Channel Frame Reception ....................................
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CONTENTS Paragraph Number 22.12 22.13 22.14 22.15 22.16 22.17 Title Page Number SCC BISYNC Receive BD (RxBD) ................................................................22-12 SCC BISYNC Transmit BD (TxBD) ...............................................................22-14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) ..............22-15 SCC Status Registers (SCCS) ..........................................................................22-16 Programming the SCC BISYNC Controller ........
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CONTENTS Paragraph Number 24.6 24.7 24.8 24.9 24.10 24.11 24.12 24.13 24.14 24.15 24.16 24.17 24.18 24.19 24.20 24.21 Title Page Number The Content-Addressable Memory (CAM) Interface ........................................24-7 SCC Ethernet Parameter RAM...........................................................................24-8 Programming the Ethernet Controller ..............................................................24-10 SCC Ethernet Commands..................................................
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CONTENTS Paragraph Number 26.2.4.4 26.2.4.5 26.2.5 26.2.6 26.3 26.3.1 26.3.2 26.3.3 26.3.4 26.3.5 26.3.6 26.3.7 26.3.8 26.3.9 26.3.10 26.3.11 26.3.12 26.4 26.4.1 26.4.2 26.4.3 26.4.4 26.4.5 26.4.6 26.4.7 26.4.8 26.4.9 26.4.10 26.4.11 26.5 26.5.1 26.5.2 26.5.2.1 26.5.2.2 26.5.3 26.5.3.1 26.5.3.2 26.5.4 26.5.5 26.5.6 26.5.7 26.5.8 26.5.9 MOTOROLA Title Page Number SMC Receiver Shortcut Sequence ...........................................................26-10 Switching Protocols ...........................
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CONTENTS Paragraph Number Title Page Number Chapter 27 Multi-Channel Controllers (MCCs) 27.1 27.2 27.3 27.4 27.5 27.6 27.6.1 27.6.2 27.6.3 27.6.4 27.7 27.7.1 27.8 27.9 27.10 27.10.1 27.10.1.1 27.11 27.11.1 27.11.2 27.12 27.12.1 27.12.2 27.13 Features...............................................................................................................27-1 MCC Data Structure Organization .....................................................................27-2 Global MCC Parameters..............
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CONTENTS Paragraph Number 28.8.3 28.9 28.10 28.11 28.12 28.12.1 28.12.2 28.12.3 28.12.4 28.12.5 28.13 Title Page Number FCC Status Registers (FCCSx) ....................................................................28-14 FCC Initialization.............................................................................................28-14 FCC Interrupt Handling ...................................................................................28-15 FCC Timing Control ......................................
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CONTENTS Paragraph Number 29.3.6 29.4 29.4.1 29.4.2 29.4.2.1 29.4.2.2 29.4.3 29.4.4 29.5 29.5.1 29.5.1.1 29.5.1.2 29.5.1.3 29.5.2 29.5.2.1 29.5.3 29.6 29.6.1 29.6.2 29.6.3 29.6.4 29.6.5 29.6.6 29.6.6.1 29.6.6.2 29.6.6.3 29.6.6.4 29.7 29.7.1 29.8 29.9 29.9.1 29.9.2 29.9.3 29.9.4 29.9.5 29.9.6 29.9.7 29.9.8 29.10 29.10.1 29.10.1.1 29.10.1.2 xxvi Title Page Number Determining the Priority of an ATM Channel .............................................29-13 VCI/VPI Address Lookup Mechanism..................
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CONTENTS Paragraph Number 29.10.1.3 29.10.2 29.10.2.1 29.10.2.2 29.10.2.2.1 29.10.2.2.2 29.10.2.2.3 29.10.2.2.4 29.10.2.3 29.10.2.3.1 29.10.2.3.2 29.10.2.3.3 29.10.2.3.4 29.10.2.3.5 29.10.2.3.6 29.10.3 29.10.4 29.10.4.1 29.10.4.2 29.10.4.3 29.10.5 29.10.5.1 29.10.5.2 29.10.5.2.1 29.10.5.2.2 29.10.5.2.3 29.10.5.2.4 29.10.5.3 29.10.5.4 29.10.5.5 29.10.5.6 29.10.5.7 29.10.5.8 29.10.5.9 29.10.5.10 29.10.5.11 29.10.6 29.10.7 29.11 29.11.1 29.11.2 29.11.3 29.
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CONTENTS Paragraph Number 29.12.1 29.12.1.1 29.12.2 29.12.2.1 29.12.2.2 29.12.2.3 29.13 29.13.1 29.13.2 29.13.3 29.13.4 29.14 29.15 29.16 29.16.1 29.16.2 29.16.3 Title Page Number UTOPIA Interface Master Mode..................................................................29-82 UTOPIA Master Multiple PHY Operation ..............................................29-83 UTOPIA Interface Slave Mode ....................................................................29-83 UTOPIA Slave Multiple PHY Operation...
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CONTENTS Paragraph Number 30.19 30.20 Title Page Number Ethernet RxBDs................................................................................................30-23 Ethernet TxBDs................................................................................................30-26 Chapter 31 FCC HDLC Controller 31.1 31.2 31.3 31.4 31.5 31.5.1 31.5.2 31.6 31.7 31.8 31.9 31.10 Key Features.......................................................................................................
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CONTENTS Paragraph Number 33.4.3 33.5 33.5.1 33.6 33.7 33.7.1 33.7.1.1 33.7.1.2 33.8 33.9 33.10 Title Page Number SPI Command Register (SPCOM) .................................................................33-9 SPI Parameter RAM .........................................................................................33-10 Receive/Transmit Function Code Registers (RFCR/TFCR) ........................33-12 SPI Commands .......................................................................................
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CONTENTS Paragraph Number 35.2.3 35.2.4 35.2.5 35.3 35.4 35.4.1 35.4.2 35.5 35.6 Title Page Number Port Data Direction Registers (PDIRAÐPDIRD)...........................................35-3 Port Pin Assignment Register (PPAR)...........................................................35-4 Port Special Options Registers AÐD (PSORAÐPSORD)...............................35-4 Port Block Diagram............................................................................................35-6 Port Pins Functions .
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CONTENTS Paragraph Number xxxii Title MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA
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ILLUSTRATIONS Figure Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 2-1 2-2 2-3 2-4 2-5 2-6 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 Title Page Number MPC8260 Block Diagram ......................................................................................... 1-5 MPC8260 External Signals........................................................................................ 1-8 Remote Access Server Configuration.......................................
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ILLUSTRATIONS Figure Number 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 5-1 5-2 5-3 5-4 5-5 5-6 6-1 7-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 9-1 9-2 xxxiv Page Number SIU External Interrupt Control Register (SIEXR)................................................... 4-25 Bus Configuration Register (BCR).......................................................................... 4-26 PPC_ACR ............................................
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ILLUSTRATIONS Figure Number 9-3 9-4 9-5 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31 10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 Title Page Number System Clock Control Register (SCCR).................................................................... 9-8 System Clock Mode Register (SCMR)......................................................................
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ILLUSTRATIONS Figure Number 10-41 10-42 10-43 10-44 10-45 10-46 10-47 10-48 10-49 10-50 10-51 10-52 10-53 10-54 10-55 10-56 10-57 10-58 10-59 10-60 10-61 10-62 10-63 10-64 10-65 10-66 10-67 10-68 10-69 10-70 10-71 10-72 10-73 10-74 10-75 10-76 10-77 10-78 10-79 10-80 10-81 xxxvi Page Number GPCM Peripheral Device Interface ....................................................................... 10-53 GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0) ...................
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ILLUSTRATIONS Figure Number 10-82 10-83 10-84 10-85 10-86 11-1 11-2 11-3 11-4 12-1 12-2 12-3 12-4 12-5 12-6 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 Title Page Number Refresh Cycle (CBR) to EDO DRAM................................................................... 10-98 Exception Cycle For EDO DRAM ........................................................................
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ILLUSTRATIONS Figure Number 14-17 14-18 14-19 14-20 14-21 14-22 14-23 14-24 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 16-1 16-2 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 19-1 xxxviii Page Number Falling Edge (FE) Effect When CE = 0 and xFSD = 00 ....................................... 14-23 SIx RAM Shadow Address Registers (SIxRSR) ................................................... 14-24 SI Command Register (SIxCMDR)..............
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ILLUSTRATIONS Figure Number 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 21-14 21-15 21-16 22-1 Title Page Number GSMR_HÑGeneral SCC Mode Register (High Order) ......................................... 19-3 GSMR_LÑGeneral SCC Mode Register (Low Order) .......................................... 19-6 Data Synchronization Register (DSR)...........
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ILLUSTRATIONS Figure Number 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 23-1 23-2 23-3 23-4 23-5 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 25-1 25-2 26-1 26-2 26-3 26-4 26-5 26-6 26-7 26-8 26-9 26-10 26-11 26-12 26-13 26-14 26-15 26-16 26-17 26-18 xl Page Number Control Character Table and RCCM ....................................................................... 22-6 BISYNC SYNC (BSYNC) ...................................................................................... 22-7 BISYNC DLE (BDLE)...
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ILLUSTRATIONS Figure Number 26-19 27-1 27-2 27-3 27-4 27-5 27-6 27-7 27-8 27-9 27-10 27-11 27-12 27-13 27-14 27-15 27-16 28-1 28-2 28-3 28-4 28-5 28-6 28-7 28-8 28-9 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 29-9 29-10 29-11 29-12 29-13 29-14 29-15 29-16 29-17 Title Page Number SMC GCI Event Register (SMCE)/Mask Register (SMCM)................................ 26-34 BD Structure for One MCC..................................................................................... 27-3 Super Channel Table Entry...
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ILLUSTRATIONS Figure Number 29-18 29-19 29-20 29-21 29-22 29-23 29-24 29-25 29-26 29-27 29-28 29-29 29-30 29-31 29-32 29-33 29-34 29-35 29-36 29-37 29-38 29-39 29-40 29-41 29-42 29-43 29-44 29-45 29-46 29-47 29-48 29-49 29-50 29-51 29-52 29-53 29-54 29-55 29-56 29-57 29-58 29-59 29-60 xlii Page Number FMC, BRC Insertion.............................................................................................. 29-32 Format of User-Defined Cells ...........................................................
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ILLUSTRATIONS Figure Number 29-62 29-61 29-63 29-64 29-65 30-1 30-2 30-3 30-4 30-5 30-6 30-7 30-8 30-9 30-10 31-1 31-2 31-3 31-4 31-5 31-6 31-7 31-8 31-9 32-1 32-2 33-1 33-2 33-3 33-4 33-5 33-6 33-7 33-8 33-9 33-10 33-11 33-12 34-1 34-2 34-3 34-4 34-5 Title Page Number FCC Transmit Internal Rate Clocking ................................................................... 29-89 FCC Transmit Internal Rate Registers (FTIRRx).................................................. 29-89 COMM_INFO Field ...........
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ILLUSTRATIONS Figure Number 34-6 34-7 34-8 34-9 34-10 34-11 34-12 34-13 34-14 35-1 35-2 35-3 35-4 35-5 35-6 35-7 xliv Page Number I2C Mode Register (I2MOD)................................................................................... 34-6 I2C Address Register (I2ADD) ............................................................................... 34-7 I2C Baud Rate Generator Register (I2BRG) ........................................................... 34-7 I2C Event/Mask Registers (I2CER/I2CMR) .......
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TABLES Table Number i ii iii iv 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 v 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 Title Page Number Acronyms and Abbreviated Terms ............................................................................. lxi Terminology Conventions ....................................................................................... lxiv Instruction Field Conventions .................................................................
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TABLES Table Number 4-21 4-22 4-23 4-24 5-1 5-2 5-3 5-4 5-5 5-6 5-7 vi 6-1 7-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 xlvi Title Page Number PISCR Field Descriptions........................................................................................ 4-43 PITC Field Descriptions .......................................................................................... 4-44 PITR Field Descriptions ...........
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TABLES Table Number 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31 10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 10-41 10-42 10-43 12-1 12-2 12-3 vii 13-1 13-2 13-3 13-4 13-5 13-6 13-7 Title Page Number 60x Bus-Assigned UPM Refresh Timer (PURT) .................................................. 10-30 Local Bus-Assigned UPM Refresh Timer (LURT)...............................................
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TABLES Table Number 13-8 13-9 13-10 13-11 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 15-1 15-2 15-3 15-4 15-5 15-6 15-7 16-1 16-2 16-3 17-1 17-2 17-3 17-4 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 xlviii Title Page Number Command Descriptions ......................................................................................... 13-14 Buffer Descriptor Format ......................................................................................
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TABLES Table Number 18-14 18-15 18-16 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 22-1 22-2 22-3 22-4 22-5 22-6 22-7 Title Page Number Parallel I/O Register ProgrammingÑPort D ......................................................... 18-29 Example: Peripheral-to-Memory ModeÑIDMA2 ................................................
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TABLES Table Number 22-8 22-9 22-10 22-11 22-12 22-13 22-14 22-15 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 23-10 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 26-1 26-2 26-3 26-4 26-5 26-6 26-7 26-8 26-9 26-10 26-11 26-12 26-13 26-14 26-15 26-16 l Title Page Number Transmit Errors ...................................................................................................... 22-10 Receive Errors ...................................................................................................
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TABLES Table Number 26-17 26-18 26-19 26-20 26-21 26-22 26-23 27-1 27-2 27-3 27-4 27-5 27-6 27-7 27-8 27-9 27-10 27-11 27-12 27-13 27-14 27-15 27-16 28-1 28-2 28-3 28-4 28-5 28-6 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 29-9 29-10 29-11 29-12 29-13 29-14 Title Page Number SMC GCI Parameter RAM Memory Map............................................................. 26-30 SMC GCI Commands............................................................................................
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TABLES Table Number 29-15 29-16 29-17 29-18 29-19 29-20 29-21 29-22 29-23 29-24 29-25 29-26 29-27 29-28 29-29 29-30 29-31 29-32 29-33 29-34 29-35 29-36 29-37 29-38 29-39 29-40 29-41 29-42 29-43 29-44 29-45 29-46 29-47 29-48 29-49 29-50 30-1 30-2 30-3 30-4 30-5 30-6 30-7 lii Title Page Number Receive and Transmit Connection Table Sizes ..................................................... 29-42 RCT Field Descriptions ........................................................................................
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TABLES Table Number 30-8 30-9 30-10 30-11 31-1 31-2 31-3 31-4 31-5 31-6 31-7 31-8 31-9 31-10 33-1 33-2 33-3 33-4 33-5 33-6 33-7 33-8 33-9 34-1 34-2 34-3 34-4 34-5 34-6 34-7 34-8 34-9 34-10 35-1 35-2 35-3 35-4 35-5 35-6 35-7 35-8 A-1 A-2 Title Page Number FPSMR Ethernet Field Descriptions ..................................................................... 30-20 FCCE/FCCM Field Descriptions........................................................................... 30-22 RxBD Field Descriptions...........
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TABLES Table Number A-3 A-4 A-5 liv Title Page Number Supervisor-Level PowerPC Registers (Non-SPR).................................................... A-2 Supervisor-Level PowerPC SPRs............................................................................. A-2 MPC8260-Specific Supervisor-Level SPRs .............................................................
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About This Book The primary objective of this manual is to help communications system designers build systems using the Motorola MPC8260 and to help software designers provide operating systems and user-level applications to take fullest advantage of the MPC8260. Although this book describes aspects regarding the PowerPCª architecture that are critical for understanding the MPC8260 core, it does not contain a complete description of the architecture.
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Organization Following is a summary and a brief description of the chapters of this manual: ¥ Part I, ÒOverview,Ó provides a high-level description of the MPC8260, describing general operation and listing basic features. Ñ Chapter 1, ÒOverview,Ó provides a high-level description of MPC8260 functions and features. It roughly follows the structure of this book, summarizing the relevant features and providing references for the reader who needs additional information.
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Ñ Chapter 13, ÒCommunications Processor Module Overview,Ó provides a brief overview of the MPC8260 CPM. Ñ Chapter 14, ÒSerial Interface with Time-Slot Assigner,Ó describes the SIU, which controls system start-up, initialization and operation, protection, as well as the external system bus.
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Ñ Chapter 27, ÒMulti-Channel Controllers (MCCs),Ó describes the MPC8260Õs multi-channel controller (MCC), which handles up to 128 serial, full-duplex data channels. Ñ Chapter 28, ÒFast Communications Controllers (FCCs),Ó describes the MPC8260Õs fast communications controllers (FCCs), which are SCCs optimized for synchronous high-rate protocols. Ñ Chapter 29, ÒATM Controller,Ó describes the MPC8260 ATM controller, which provides the ATM and AAL layers of the ATM protocol.
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Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC8xx Documentation Supporting documentation for the MPC8260 can be accessed through the world-wide web at http://www.mot.com/netcomm. This documentation includes technical speciÞcations, reference materials, and detailed applications notes.
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¥ Application notesÑThese short documents contain useful information about speciÞc design issues useful to programmers and engineers working with PowerPC processors. For a current list of PowerPC documentation, refer to the world-wide web at http://www.mot.com/PowerPC.
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Acronyms and Abbreviations Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. Table i. Acronyms and Abbreviated Terms Term Meaning A/D Analog-to-digital ALU Arithmetic logic unit ATM Asynchronous transfer mode BD Buffer descriptor BIST Built-in self test BPU Branch processing unit BRI Basic rate interface.
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Table i.
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Table i.
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Table i.
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Table iii describes instruction Þeld notation conventions used in this manual. Table iii. Instruction Field Conventions The Architecture SpeciÞcation Equivalent to: BA, BB, BT crbA, crbB, crbD (respectively) BF, BFA crfD, crfS (respectively) D d DS ds FLM FM FXM CRM RA, RB, RT, RS rA, rB, rD, rS (respectively) SI SIMM U IMM UI UIMM /, //, /// 0...
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lxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
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Part I Overview Intended Audience Part I is intended for readers who need a high-level understanding of the MPC8260. Contents Part I provides a high-level description of the MPC8260, describing general operation and listing basic features. ¥ ¥ ¥ Chapter 1, ÒOverview,Ó provides a high-level description of MPC8260 functions and features. It roughly follows the structure of this book, summarizing the relevant features and providing references for the reader who needs additional information.
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Part I. Overview REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register. x In certain contexts, such as in a signal encoding or a bit Þeld, indicates a donÕt care.
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Part I. Overview Table iv.
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Part I. Overview Table iv.
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Chapter 1 Overview 10 10 The MPC8260 PowerQUICC IIª is a versatile communications processor that integrates on one chip a high-performance PowerPCª RISC microprocessor, a very ßexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and networking systems.
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Part I. Overview Ñ PowerPC architecture-compliant memory management unit (MMU) Ñ Common on-chip processor (COP) test interface Ñ Supports bus snooping for cache coherency Ñ No ßoating-point unit (FPU). Floating-point arithmetic is not supported. Ñ Support for ßoating-point loads and stores. Ñ Support for cache locking. ¥ Low-power (less than 2.5 W when fully operational at 133 MHz, 2-V internal and 3.3-V I/O) ¥ ¥ Separate power supply for internal logic (2 V) and for I/O (3.
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Part I.
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Part I.
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Part I. Overview 16-Kbyte Instruction Cache 60x Bus IMMU MPC603e PowerPC Core 16-Kbyte Data Cache 60x -to-Local Bus Bridge DMMU Memory Controller Local Bus Bus Interface Unit Timers Interrupt Controller Parallel I/O Baud Rate Gen.
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Part I. Overview The MPC603e core has an internal common on-chip (COP) debug processor. This processor allows access to internal scan chains for debugging purposes. It is also used as a serial connection to the core for emulator support. The MPC603e core performance for the SPEC 95 benchmark for integer operations ranges between 4.4 and 5.1 at 200 MHz. In Dhrystone 2.1 MIPS, the MPC603e is 280 MIPS at 200 MHz (compared to 86 MIPS of the MPC860 at 66 MHz). The MPC603e core can be disabled.
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Part I. Overview The following list summarizes the major features of the CPM: ¥ The CP is an embedded 32-bit RISC controller residing on a separate bus (CPM local bus) from the 60x bus (used by the system core). With this separate bus, the CP does not affect the performance of the PowerPC core. The CP handles the lower layer tasks and DMA control activities, leaving the PowerPC core free to handle higher layer activities.
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Part I. Overview NOTE A bar over a signal name indicates that the signal is active lowÑfor example, BB (bus busy). Active-low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as TSIZ[0Ð3] (transfer size signals) are referred to as asserted when they are high and negated when they are low.
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Part I. Overview 1.4 Differences between MPC860 and MPC8260 The following MPC860 features are not included in the MPC8260.
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Part I. Overview 1.6 MPC8260 ConÞgurations The MPC8260 offers ßexibility in conÞguring the device for speciÞc applications. The functions mentioned in the above sections are all available in the device, but not all of them can be used at the same time. This does not imply that the device is not fully activated in any given implementation: The CPM architecture has the advantage of using common hardware resources for many different protocols, and applications.
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Part I. Overview FCCs can also be used to run slower HDLC or 10 BaseT, for example. The CPÕs RISC architecture has the advantage of using common hardware resources for all FCCs. 1.7 MPC8260 Application Examples The MPC8260 can be conÞgured to meet many system application needs, as shown in the following sections. 1.7.
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Part I. Overview In this application, eight TDM ports are connected to external framers. In the MPC8260, each group of four ports support up to 128 channels. One TDM interface can support 32Ð 128 channels. The MPC8260 receives and transmits data in transparent or HDLC mode, and stores or retrieves the channelized data from memory. The data can be stored either in memory residing on the 60x bus or in memory residing on the local bus.
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Part I. Overview In this application, the MPC8260 is connected to four TDM interfaces channalizing up to 128 channels. Each TDM port supports 32Ð128 channels. If 128 channels are needed, each TDM port can be conÞgured to support 32 channels. This example has two MII ports for 10/100 BaseT LAN connections. In all the examples, the SCC ports can be used for management. 1.7.1.3 LAN-to-WAN Bridge Router Figure 1-5 shows a LAN-to-WAN router conÞguration, which is similar to the previous example.
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Part I. Overview 1.7.1.4 Cellular Base Station Figure 1-6 shows a cellular base station conÞguration. MPC8260 SDRAM/DRAM/SRAM TDM0 Framer 60x Bus Channelized Data (up to 256 channels) TDM1 DSP Bank Local Bus Slow Comm Slaves on Local Bus SMC/I2C/SPI/SCC PHY Figure 1-6. Cellular Base Station Configuration Here the MPC8260 channelizes two E1s (up to 256, 16-Kbps channels). The local bus can control a bank of DSPs.
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Part I. Overview The MPC8260 CPM supports a total aggregate throughput of 710 Mbps at 133 MHz. This includes two full-duplex 100 BaseT and one full-duplex 155 Mbps for ATM. The MPC603e core can operate at a different (higher) speed, if the application requires it. 1.7.1.6 SONET Transmission Controller Figure 1-8 shows a SONET transmission controller conÞguration.
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Part I. Overview not need to be heavily processed by the core. The CP can store large data frames in the local memory without interfering with the operation of the system core. SDRAM/SRAM/DRAM/Flash MPC8260 60x Bus PHY Communication Channels SDRAM/SRAM/DRAM 155 Mbps ATM PHY UTOPIA Local Bus ATM Connection Tables Figure 1-9. Basic System Configuration 1.7.2.2 High-Performance Communication Figure 1-10 shows a high-performance communication conÞguration.
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Part I. Overview Serial throughput is enhanced by connecting one MPC8260 in master or slave mode (with system core enabled or disabled) to another MPC8260 in master mode with the core enabled. The core in MPC8260 A can access the memory on the local bus of MPC8260 B. 1.7.2.3 High-Performance System Microprocessor Figure 1-11 shows a conÞguration with a high-performance system microprocessor (MPC750).
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Part I.
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Chapter 2 PowerPC Processor Core 20 20 The MPC8260 contains an embedded version of the PowerPC 603eª processor. This chapter provides an overview of the basic functionality of the processor core.
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Part I.
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Part I. Overview The processor core integrates four execution unitsÑan integer unit (IU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute four instructions in parallel and the use of simple instructions with rapid execution times yield high efÞciency and throughput. Most integer instructions execute in one clock cycle. The processor core supports integer data types of 8, 16, and 32 bits, and ßoating-point data types of 32 and 64 bits.
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Part I. Overview ¥ Four independent execution units and two register Þles Ñ Ñ Ñ Ñ ¥ ¥ 2-4 BPU featuring static branch prediction A 32-bit IU LSU for data transfer between data cache and GPRs and FPRs SRU that executes condition register (CR), special-purpose register (SPR), and integer add/compare instructions Ñ Thirty-two GPRs for integer operands Ñ Thirty-two FPRs.
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Part I.
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Part I. Overview are dispatched to their respective execution units from the dispatch unit at a maximum rate of two instructions per cycle. Reservation stations at the IU, LSU, and SRU facilitate instruction dispatch to those units. The dispatch unit checks for source and destination register dependencies, determines dispatch serializations, and inhibits subsequent instruction dispatching as required. Section 2.7, ÒInstruction Timing,Ó describes instruction dispatch in detail. 2.2.
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Part I. Overview 2.2.4.2 Load/Store Unit (LSU) The LSU executes all load and store instructions and provides the data transfer interface between the GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data alignment, and provides sequencing for load/store string and multiple instructions. Load and store instructions are issued and translated in program order; however, the actual memory accesses can occur out of order.
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Part I. Overview 2.2.6 Memory Subsystem Support The processor core supports cache and memory management through separate instruction and data MMUs (IMMU and DMMU). The processor core also provides dual 16-Kbyte instruction and data caches, and an efÞcient processor bus interface to facilitate access to main memory and other bus subsystems. The memory subsystem support functions are described in the following subsections. 2.2.6.
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Part I. Overview environment architecture (OEA), as well as the MPC8260 core implementation-speciÞc registers. Full descriptions of the basic register set deÞned by the PowerPC architecture are provided in Chapter 2, ÒPowerPC Register Set,Ó in The Programming Environments Manual. The PowerPC architecture deÞnes register-to-register operations for all arithmetic instructions.
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Part I.
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Part I. Overview Although the MPC8260 does not support ßoating-point arithmetic instructions, the FPRs are provided to support ßoating-point load and store instructions, which can be executed by the LSU. For these instructions to execute, the FPRs must be enabled (MSR[FP] = 1); otherwise, a ßoating-point unavailable exception is taken. It is recommended that the FPRs be enabled only when there is a need to access the FPRs, for example, to handle ßash memory updates.
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Part I. Overview Table 2-1 shows the bit deÞnitions for HID0. Table 2-1. HID0 Field Descriptions Bits Name Description 0 EMCP Enable machine check input pin 0 The assertion of the MCP does not cause a machine check exception. 1 Enables the entry into a machine check exception based on assertion of the MCP input, detection of a Cache Parity Error, detection of an address parity error, or detection of a data parity error.
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Part I. Overview Table 2-1. HID0 Field Descriptions (Continued) Bits Name 11 DPM 12Ð14 Ñ 15 NHR Not hard reset (software-use only)ÑHelps software distinguish a hard reset from a soft reset. 0 A hard reset occurred if software had previously set this bit. 1 A hard reset has not occurred. If software sets this bit after a hard reset, when a reset occurs and this bit remains set, software can tell it was a soft reset.
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Part I. Overview Table 2-1. HID0 Field Descriptions (Continued) 1 2 Bits Name Description 20 ICFI Instruction cache ßash invalidate 2 0 The instruction cache is not invalidated. The bit is cleared when the invalidation operation begins (usually the next cycle after the write operation to the register). The instruction cache must be enabled for the invalidation to occur.
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Part I. Overview PLLCFG 0 Ñ 4 5 31 Figure 2-4. Hardware Implementation Register 1 (HID1) Table 2-2 shows the bit deÞnitions for HID1. Table 2-2. HID1 Field Descriptions Bits 0Ð4 5Ð31 Name Function PLLCFG PLL conÞguration setting Ñ Reserved 2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) The processor core implements an additional hardware implementation-dependent register not described in the MPC603e UserÕs Manual, shown in Figure 2-5.
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Part I. Overview 2.3.1.2.4 Processor Version Register (PVR) Software can identify the MPC8260Õs processor core by reading the processor version register (PVR). The MPC8260Õs processor version number is 0x0081; the processor revision level starts at 0x0100 and is incremented for each revision of the chip. 2.3.2 PowerPC Instruction Set and Addressing Modes All PowerPC instructions are encoded as single-word (32-bit) opcodes.
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Part I. Overview ¥ Load/store instructionsÑThese include integer and ßoating-point load and store instructions. Ñ Ñ Ñ Ñ ¥ ¥ ¥ Integer load and store Integer load and store with byte reverse Integer load and store string/multiple Floating-point load and store. Setting MSR[FPE] allows the MPC8260 to access the FPRs with the ßoating-point load and store instructions described in the MPC603e UserÕs Manual.
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Part I. Overview Computational instructions do not modify memory. To use a memory operand in a computation and then modify the same or another memory location, the memory contents must be loaded into a register, modiÞed, and then written back to the target location with separate instructions. Decoupling arithmetic instructions from memory accesses increases throughput by facilitating pipelining. PowerPC processors follow the program ßow when they are in the normal execution state.
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Part I. Overview PowerPC microprocessors control the following memory access modes on a page or block basis: ¥ Write-back/write-through mode ¥ Caching-inhibited mode ¥ Memory coherency The PowerPC cache management instructions provide a means by which the application programmer can affect the cache contents. 2.4.2 MPC8260 Implementation-SpeciÞc Cache Implementation As shown in Figure 2-1, the caches provide a 64-bit interface to the instruction fetch unit and load/store unit.
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Part I. Overview 128 Sets Block 0 Address Tag 0 State Words 0Ð7 Block 1 Address Tag 1 State Words 0Ð7 Block 2 Address Tag 2 State Words 0Ð7 Block 3 Address Tag 3 State Words 0Ð7 8 Words/Block Figure 2-6. Data Cache Organization Because the processor core data cache tags are single-ported, simultaneous load or store and snoop accesses cause resource contention.
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Part I. Overview maximizing the efÞciency of the internal bus without sacriÞcing coherency of the data. The processor core allows pending read operations to precede previous store operations (except when a dependency exists, or in cases where a non-cacheable access is performed), and provides support for a write operation to proceed a previously queued read data tenure (for example, allowing a snoop push to be enveloped by the address and data tenures of a read operation).
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Part I. Overview ways 0, 1, and 2 but it is not possible to lock just way0 and way2). When using way locking at least one way must be left unlocked. The maximum number of lockable ways is three. Unlike entire cache locking, invalid entries in a locked way are accessible and available for data placement. As hits to the cache Þll invalid entries within a locked way, the entries become valid and locked.
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Part I. Overview an instruction-caused exception in the exception handler. SRR0 and SRR1 should also be saved before enabling external interrupts. The PowerPC architecture supports four types of exceptions: ¥ ¥ ¥ ¥ Synchronous, preciseÑThese are caused by instructions. All instruction-caused exceptions are handled precisely; that is, the machine state at the time the exception occurs is known and can be completely restored.
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Part I. Overview Table 2-4.
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Part I. Overview Table 2-5. Exceptions and Conditions (Continued) Exception Type Vector Offset (hex) Causing Conditions ISI 00400 An ISI exception is caused when an instruction fetch cannot be performed for any of the following reasons: ¥ The effective (logical) address cannot be translated. That is, there is a page fault for this portion of the translation, so an ISI exception must be taken to load the PTE (and possibly the page) into memory.
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Part I. Overview Table 2-5. Exceptions and Conditions (Continued) Exception Type Vector Offset (hex) Causing Conditions Trace 00D00 A trace exception is taken when MSR[SE] = 1 or when the currently completing instruction is a branch and MSR[BE] = 1. Floating-point assist 00E00 Not implemented. Reserved 00E10Ð00FFF Ñ Instruction translation miss 01000 An instruction translation miss exception is caused when the effective address for an instruction fetch cannot be translated by the ITLB.
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Part I. Overview 2.6.1 PowerPC MMU Model The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for memory accesses, and to provide access protection on blocks and pages of memory. There are two types of accesses generated by the processor core that require address translationÑinstruction accesses and data accesses to memory generated by load and store instructions. The PowerPC MMU and exception models support demand-paged virtual memory.
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Part I. Overview 2.6.2 MPC8260 Implementation-SpeciÞc MMU Features The instruction and data MMUs in the processor core provide 4-Gbytes of logical address space accessible to supervisor and user programs with a 4-Kbyte page size and 256-Mbyte segment size. The MPC8260Õs MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gbytes (232) of physical memory (referred to as real memory in the PowerPC architecture speciÞcation) for instructions and data.
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Part I. Overview 2.7 Instruction Timing The processor core is a pipelined superscalar processor. A pipelined processor is one in which the processing of an instruction is broken into discrete stages. Because the processing of an instruction is broken into a series of stages, an instruction does not require the entire resources of an execution unit at one time.
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Part I. Overview The new latency is reßected in Table 2-6. Table 2-6. Integer Divide Latency Primary Opcode Extended Opcode Mnemonic Form Unit Cycles 31 459 divwu[o][.] xo IU 20 31 491 divw[o][.] xo IU 20 2.8 Differences between the MPC8260Õs Core and the PowerPC 603e Microprocessor The MPC8260Õs processor core is a derivative of the MPC603e microprocessor design. Some changes have been made and are visible either to a programmer or a system designer.
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Part I. Overview Table 2-7. Major Differences between MPC8260Õs Core and the MPC603e UserÕs Manual Description Addition of speed-for-power functionality Impact The processor core implements an additional dynamic power management mechanism. HID2[SFP] controls this function. See Section 2.3.1.2.3, ÒHardware Implementation-Dependent Register 2 (HID2).Ó Improved access to cache during block The MPC8260 provides quicker access to incoming data and instruction on Þlls a cache block Þll. See Section 2.4.
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Part I.
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Chapter 3 Memory Map 30 30 The MPC8260's internal memory resources are mapped within a contiguous block of memory. The size of the internal space in the MPC8260 is 128 Kbytes. The location of this block within the global 4-Gbyte real memory space can be mapped on 128 Kbytes resolution through an implementation speciÞc special register called the internal memory map register (IMMR). For more information, see Section 4.3.2.7, ÒInternal Memory Map Register (IMMR).
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size Section/Page Number 10030 PPC_ALRL 60x bus arbitration-level register low (next 8 clients) 32 bits 4.3.2.3/4-28 10034 LCL_ACR Local arbiter conÞguration register 8 bits 4.3.2.4/4-29 10038 LCL_ALRH Local arbitration-level register (Þrst 8 clients) 32 bits 4.3.2.5/4-30 1003C LCL_ALRL Local arbitration-level register (next 8 clients) 32 bits 4.3.2.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size Section/Page Number 10134 OR6 Option register bank 6 32 bits 10.3.2/10-16 10138 BR7 Base register bank 7 32 bits 10.3.1/10-14 1013C OR7 Option register bank 7 32 bits 10.3.2/10-16 10140 BR8 Base register bank 8 32 bits 10.3.1/10-14 10144 OR8 Option register bank 8 32 bits 10.3.2/10-16 10148 BR9 Base register bank 9 32 bits 10.3.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size Section/Page Number System Integration Timers 10200Ð10 21F Reserved Ñ 32 bytes 10220 TMCNTSC Time counter status and control register 16 bits 4.3.2.14/4-40 10224 TMCNT Time counter register 32 bits 4.3.2.15/4-41 10228 Reserved Ñ 32 bits Ñ 1022C TMCNTAL Time counter alarm register 32 bits 4.3.2.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size Section/Page Number Input/Output Port 10D00 PDIRA Port A data direction register 32 bits 35.2.3/35-3 10D04 PPARA Port A pin assignment register 32 bits 35.2.4/35-4 10D08 PSORA Port A special options register 32 bits 35.2.5/35-4 10D0C PODRA Port A open drain register 32 bits 35.2.1/35-2 10D10 PDATA Port A data register 32 bits 35.2.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size Section/Page Number 10D92 TMR2 Timer 2 mode register 16 bits 17.2.3/17-6 10D94 TRR1 Timer 1 reference register 16 bits 17.2.4/17-7 10D96 TRR2 Timer 2 reference register 16 bits 17.2.4/17-7 10D98 TCR1 Timer 1 capture register 16 bits 17.2.5/17-8 10D9A TCR2 Timer 2 capture register 16 bits 17.2.5/17-8 10D9C TCN1 Timer 1 counter 16 bits 17.2.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size 24 bits Section/Page Number 11029 Reserved Ñ Ñ 1102C IDMR2 IDMA 2 mask register 8 bits 18.8.4/18-22 1102D Reserved Ñ 24 bits Ñ 11030 IDSR3 IDMA 3 event register 8 bits 18.8.4/18-22 11031 Reserved Ñ 24 bits Ñ 11034 IDMR3 IDMA 3 mask register 8 bits 18.8.4/18-22 11035 Reserved Ñ 24 bits Ñ 11038 IDSR4 IDMA 4 event register 8 bits 18.8.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation 11328 FTODR2 1132A 1132C Name Size Section/Page Number FCC2 transmit on-demand register 16 bits 28.5/28-7 Reserved Ñ 2 bytes Ñ FDSR2 FCC2 data synchronization register 16 bits 28.4/28-7 1132E Reserved Ñ 2 bytes Ñ 11330 FCCE2 FCC2 event register 32 bits 11334 FCCM2 FCC2 mask register 32 bits 29.13.3/29-87 (ATM) 30.18.2/30-21 (Ethernet) 31.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size Section/Page Number I2C 11860 I2MOD I2C mode register 8 bits 34.4.1/34-6 11862 Reserved Ñ 24 bits Ñ 11864 I2ADD I2C address register 8 bits 34.4.2/34-7 11866 Reserved Ñ 24 bits Ñ 11868 I2BRG I2C BRG register 8 bits 34.4.3/34-7 1186A Reserved Ñ 24 bits Ñ 2 1186C I2COM I C command register 8 bits 34.4.5/34-8 1186E Reserved Ñ 24 bits Ñ 8 bits 34.4.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address 11A08 Abbreviation PSMR1 Name Size Section/Page Number SCC1 protocol-speciÞc mode register 16 bits 19.1.2/19-9 20.16/20-13 (UART) 21.8/21-7 (HDLC) 22.11/22-10 (BISYNC) 23.9/23-9 (Transparent) 24.17/24-15 (Ethernet) 11A0A Reserved Ñ 2 bytes Ñ 11A0C TODR1 SCC1 transmit-on-demand register 16 bits 19.1.4/19-9 11A0E DSR1 SCC1 data synchronization register 16 bits 19.1.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size Section/Page Number SCC3 11A40 GSMR_L3 SCC3 general mode register 32 bits 19.1.1/19-3 11A44 GSMR_H3 SCC3 general mode register 32 bits 11A48 PSMR3 SCC3 protocol-speciÞc mode register 16 bits 19.1.2/19-9 20.16/20-13 (UART) 21.8/21-7 (HDLC) 22.11/22-10 (BISYNC) 23.9/23-9 (Transparent) 24.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size Section/Page Number 11A77 SCCS4 SCC4 status register 8 bits 20.20/20-21 (UART) 21.12/21-14 (HDLC) 22.15/22-16 (BISYNC) 23.13/23-13 (Transparent) 11A78Ð11A7F Reserved Ñ 8 bytes Ñ SMC1 11A82 SMCMR1 SMC1 mode register 16 bits 26.2.1/26-3 11A86 SMCE1 SMC1 event register 8 bits 11A8A SMCM1 SMC1 mask register 8 bits 26.3.11/26-18 (UART) 26.4.10/26-28 (Transparent) 26.5.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size Section/Page Number 11B0E CMXUAR CPM mux UTOPIA address register 16 bits 15.4.1/15-7 11B10Ð11B1F Reserved Ñ 16 bytes Ñ 14.5.2/14-17 SI1 Registers 11B20 SI1AMR SI1 TDMA1 mode register 16 bits 11B22 SI1BMR SI1 TDMB1 mode register 16 bits 11B24 SI1CMR SI1 TDMC1 mode register 16 bits 11B26 SI1DMR SI1 TDMD1 mode register 16 bits 11B28 SI1GMR SI1 global mode register 8 bits 14.
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Part I. Overview Table 3-1. Internal Memory Map (Continued) Internal Address Abbreviation Name Size Section/Page Number MCC2 Registers 11B50 MCCE2 MCC2 event register 16 bits 27.10.1/27-18 11B54 MCCM2 MCC2 mask register 16 bits 11B58 MCCF2 MCC2 conÞguration register 8 bits 27.8/27-15 11B59Ð11FFF Reserved Ñ 1,159 bytes Ñ 512 14.4.
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Part II ConÞguration and Reset Audience Part II is intended for system designers and programmers who need to understand the operation of the MPC8260 at start up. It assumes understanding of the PowerPC programming model described in the previous chapters and a high level understanding of the MPC8260. Contents Part II describes start-up behavior of the MPC8260.
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Part II. Configuration and Reset Conventions This chapter uses the following notational conventions: Bold entries in Þgures and tables showing registers and parameter RAM should be initialized by the user. Bold mnemonics italics Instruction mnemonics are shown in lowercase bold. Italics indicate variable command parameters, for example, bcctrx. Book titles in text are set in italics.
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Part II. Configuration and Reset Table v. Acronyms and Abbreviated Terms (Continued) Term Meaning msb Most-signiÞcant bit MSR Machine state register PCI Peripheral component interconnect RTOS Real-time operating system Rx Receive SPR Special-purpose register SWT Software watchdog timer Tx Transmit MOTOROLA Part II.
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Part II.
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Chapter 4 System Interface Unit (SIU) 40 40 The system interface unit (SIU) consists of several functions that control system start-up and initialization, as well as operation, protection, and the external system bus. Key features of the SIU include the following: ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ System conÞguration and protection System reset monitoring and generation Clock synthesizer Power management 60x bus interface Flexible, high-performance memory controller Level-two cache controller interface IEEE 1149.
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Part II. ConÞguration and Reset The system conÞguration and protection functions provide various monitors and timers, including the bus monitor, software watchdog timer, periodic interrupt timer, and time counter. The clock synthesizer generates the clock signals used by the SIU and other MPC8260 modules. The SIU clocking scheme supports stop and normal modes. The 60x bus interface is a standard pipelined bus. The MPC8260 allows external bus masters to request and obtain system bus mastership.
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Part II. ConÞguration and Reset Figure 4-2 is a block diagram of the system conÞguration and protection logic. Module Configuration Bus clock/8 Bus Monitors timersclk Periodic Interrupt Timer Bus Clock Software Watchdog Timer timersclk Time Counter System Reset CoreÕs MCP TEA Interrupt System Reset CoreÕs MCP Interrupt Figure 4-2. System Configuration and Protection Logic Many aspects of system conÞguration are controlled by several SIU module conÞguration registers, described in Section 4.
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Part II. ConÞguration and Reset 4.1.2 Timers Clock The two SIU timers (the time counter and the periodic interrupt timer) use the same clock source, timersclk, which can be derived from several sources, as described in Figure 4-3. The user should select external clock and/or BRG1 programming to yield either 4 MHz or 32 KHz at this point.
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Part II. ConÞguration and Reset SEC Interrupt timersclk for TMCNT (8,192 Hz) Divide by 8,192 32-Bit Counter = Alarm Interrupt 32-Bit Register Figure 4-4. TMCNT Block Diagram Section 4.3.2.15, ÒTime Counter Register (TMCNT),Ó describes the time counter register. 4.1.4 Periodic Interrupt Timer (PIT) The periodic interrupt timer consists of a 16-bit counter clocked by timersclk.
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Part II. ConÞguration and Reset The time-out period is calculated as follows: PIT period PITC + 1 PITC + 1 = ------------------------------------- = ------------------------F 8192 timersclk This gives a range from 122 µs (PITC = 0x0000) to 8 seconds (PITC = 0xFFFF). 4.1.5 Software Watchdog Timer The SIU provides the software watchdog timer option to prevent system lock in case the software becomes trapped in loops with no controlled exit.
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Part II. ConÞguration and Reset Although most software disciplines permit or even encourage the watchdog concept, some systems require a selection of time-out periods. For this reason, the software watchdog timer must provide a selectable range for the time-out period. Figure 4-7 shows how to handle this need. SWSR SWE Clock Disable Bus Clock Service Logic SYPCR[SWTC] Divide By 2,048 Reload MUX 16-Bit SWR/Decrementer Rollover = 0 SWP Time-out Reset or MCP Figure 4-7.
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Part II. ConÞguration and Reset ¥ Two priority schemes for the SCCs: grouped, spread ¥ Programmable highest priority request ¥ Unique vector number for each interrupt source 4.2.1 Interrupt ConÞguration Figure 4-8 shows the MPC8260 interrupt structure. The interrupt controller receives interrupts from internal sources, such as the PIT or TMCNT, from the CPM, and from external pins (port C parallel I/O pins).
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Part II. ConÞguration and Reset If the software watchdog timer is programmed to generate an interrupt, it always generates a machine check interrupt to the core. The external IRQ0 can generate MCP as well. Note that the core takes the machine check interrupt when MCP is asserted; it takes an external interrupt for any other interrupt asserted by the interrupt controller. The interrupt controller allows masking of each interrupt source. Multiple events within a CPM sub-block event are also maskable.
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Part II. ConÞguration and Reset Table 4-2.
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Part II. ConÞguration and Reset Table 4-2.
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Part II. ConÞguration and Reset Table 4-2. Interrupt Source Priority Levels (Continued) Priority Level Interrupt Source Description Multiple Events 66 SMC1 Yes 67 YCC7 (spread) Yes 68 SMC2 Yes 69 Parallel I/OÐPC1 No 70 Parallel I/OÐPC0 No 71 XSIU8 (GSIU = 1) No (TMCNT,PIT = Yes) 72 YCC8(spread) Yes 73 Reserved Ñ Notice the lack of SDMA interrupt sources, which are reported through each individual FCC, SCC, SMC, SPI, or I2C channel.
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Part II. ConÞguration and Reset 4.2.2.3 Highest Priority Interrupt In addition to the FCC/MCC/SCC relative priority option, SICR[HP] can be used to specify one interrupt source as having highest priority. This interrupt remains within the same interrupt level as the other interrupt controller interrupts, but is serviced before any other interrupt in the table.
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Part II. ConÞguration and Reset SCCE SIPNR Event Bit 13 Input (or 13 Event Bits) Request to the core (Other Unmasked Requests) SCCM SIMR Mask Bit Mask Bit Figure 4-9. Interrupt Request Masking 4.2.4 Interrupt Vector Generation and Calculation Pending unmasked interrupts are presented to the core in order of priority. The interrupt vector that allows the core to locate the interrupt service routine is made available to the core by reading SIVEC.
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Part II. ConÞguration and Reset Table 4-3.
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Part II. ConÞguration and Reset Table 4-3.
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Part II. ConÞguration and Reset 4.3 Programming Model The SIU registers are grouped into the following three categories: ¥ Interrupt controller registers. These registers control conÞguration, prioritization, and masking of interrupts. They also include registers for determining the interrupt sources. These registers are described in Section 4.3.1, ÒInterrupt Controller Registers.Ó ¥ System conÞguration and protection registers.
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Part II. ConÞguration and Reset The SICR register bits are described in Table 4-4. Table 4-4. SICR Field Descriptions Bits Name Description 0Ð1 Ñ Reserved, should be cleared. 2Ð7 HP Highest priority. SpeciÞes the 6-bit interrupt number of the single interrupt controller interrupt source that is advanced to the highest priority in the table. HP can be modiÞed dynamically. To retain the original priority, program HP to the interrupt number assigned to XSIU1. 8Ð14 Ñ Reserved, should be cleared.
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Part II. ConÞguration and Reset The SIPRR register bits are described in Table 4-5. Table 4-5. SIPRR Field Descriptions Bits Name Description 0Ð3 XS1PÐXSIU1 Priority order. DeÞnes which PIT/TMCNT/IRQs asserts its request in the XSIU1 priority position. The user should not program the same PIT/TMCNT/IRQs to more than one priority position (1Ð8). These bits can be changed dynamically. 000 TMCNT asserts its request in the XSIU1 position. 001 PIT asserts its request in the XSIU1 position.
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Part II. ConÞguration and Reset Table 4-6 describes SCPRR_H Þelds. Table 4-6. SCPRR_H Field Descriptions Bits Name Description 0Ð2 XC1PÐXCC1 Priority order. DeÞnes which FCC/MCC asserts its request in the XCC1 priority position. The user should not program the same FCC/MCC to more than one priority position (1Ð8). These bits can be changed dynamically. 000 FCC1 asserts its request in the XCC1 position. 001 FCC2 asserts its request in the XCC1 position. 010 FCC3 asserts its request in the XCC1 position.
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Part II. ConÞguration and Reset Table 4-7. SCPRR_L Field Descriptions (Continued) Bits 3Ð11 Name Description YC2PÐYC8P Same as YC1P, but for YCC2ÐYCC8 12Ð15 Ñ Reserved, should be cleared. 4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L) Each bit in the interrupt pending registers (SIPNR_H and SIPNR_L), shown in Figure 4-14 and Figure 4-15, corresponds to an interrupt source. When an interrupt is received, the interrupt controller sets the corresponding SIPNR bit.
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Part II. ConÞguration and Reset When a pending interrupt is handled, the user clears the corresponding SIPNR bit. However, if an event register exists, the unmasked event register bits should be cleared instead, causing the SIPNR bit to be cleared. SIPNR bits are cleared by writing ones to them. Because the user can only clear bits in this register, writing zeros to this register has no effect. Note that the SCC/FCC/MCC SIPNR bit positions are not changed according to their relative priority. 4.3.1.
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Part II. ConÞguration and Reset Bits 0 1 2 Field FCC1 FCC2 FCC3 3 Ñ 4 5 6 MCC1 MCC2 7 8 Ñ 9 10 12 13 SCC1 SCC2 SCC3 SCC4 Reset 0000_0000_0000_0000 R/W R/W Addr 11 14 15 30 31 Ñ 0x10C20 Bits 16 17 Field I2C SPI 18 19 20 21 22 23 24 25 26 RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA Reset 0000_0000_0000_0000 R/W R/W Addr 0x10C22 Ñ 27 28 29 TIMER1 TIMER2 TIMER3 TIMER4 Ñ Figure 4-17.
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Part II. ConÞguration and Reset The SIVEC can be read as either a byte, half word, or a word. When read as a byte, a branch table can be used in which each entry contains one instruction (branch). When read as a half word, each entry can contain a full routine of up to 256 instructions. The interrupt code is deÞned such that its two lsbs are zeroes, allowing indexing into the table, as shown in Figure 4-19.
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Part II. ConÞguration and Reset Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field EDPC0 EDPC1 EDPC2 EDPC3 EDPC4 EDPC5 EDPC6 EDPC7 EDPC8 EDPC9 EDPC10 EDPC11 EDPC12 EDPC13 EDPC14 EDPC15 Reset 0000_0000_0000_0000 R/W R/W Addr 0x10C24 Bit 16 17 18 19 20 21 22 Field EDI0 EDI1 EDI2 EDI3 EDI4 EDI5 EDI6 Reset 23 24 25 26 EDI7 27 28 29 30 Ñ 0000_0000_0000_0000 R/W R/W R Addr 0x10C26 Figure 4-20.
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Part II. ConÞguration and Reset Bits 0 Field EBM 1 2 3 4 APD 5 L2C 6 7 L2D 8 9 10 PLDP EAV 11 Ñ 12 13 14 ETM LETM EPAR LEPAR Reset Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó R/W R/W Bits Field 16 17 NPQM 18 19 20 Ñ 21 EXDD 22 23 24 25 26 Ñ 27 15 28 ISPS 29 30 31 Ñ Reset Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó R/W R/W Addr 0x10024 Figure 4-21.
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Part II. ConÞguration and Reset Table 4-9. BCR Field Descriptions (Continued) Bits Name Description 13 LETM Local bus compatibility mode enable. See Section 8.4.3.8, ÒExtended Transfer Mode.Ó 1 Extended transfer mode is enable on the local bus. 0 Extended transfer mode is disabled in the local bus. Note that if the local bus memory controller is conÞgured to work with read-modify-write parity, LETM must be cleared. 14 EPAR 15 LEPAR Local bus even parity.
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Part II. ConÞguration and Reset 4.3.2.2 60x Bus Arbiter ConÞguration Register (PPC_ACR) The 60x bus arbiter conÞguration register (PPC_ACR), shown in Figure 4-22, deÞnes the arbiter modes and parked master on the 60x bus. 0 Bit Field 1 Ñ 2 3 DBGD EARB 4 5 6 7 PRKM Reset Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó R/W R/W Addr 0x10028 Figure 4-22. PPC_ACR Table 4-10 describes PPC_ACR Þelds. Table 4-10.
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Part II. ConÞguration and Reset Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Field Priority Field 0 Priority Field 1 Priority Field 2 Priority Field 3 Reset 0000 0001 0010 0011 R/W R/W Addr Bit 15 0x1002C 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Field Priority Field 4 Priority Field 5 Priority Field 6 Priority Field 7 Reset 0100 0101 0110 0111 R/W R/W Addr 0x1002E 31 Figure 4-23.
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Part II. ConÞguration and Reset Table 4-11 describes LCL_ACR register bits. Table 4-11. LCL_ACR Field Descriptions Bits Name 0Ð1 Ñ 2 3 4Ð7 Description Reserved, should be cleared. DBGD Data bus grant delay. SpeciÞes the minimum number of data tenure wait states for PowerPC master-initiated data operations. This is the minimum delay between TS and DBG. 0 DBG is asserted with TS if the data bus is free. 1 DBG is asserted one cycle after TS if the data bus is not busy. See Section 8.5.
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Part II. ConÞguration and Reset Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Field Priority Field 8 Priority Field 9 Priority Field 10 Priority Field 11 Reset 1000 1001 1010 1011 R/W R/W Addr Bit 15 0x1003C 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Field Priority Field 12 Priority Field 13 Priority Field 14 Priority Field 15 Reset 1100 1101 1110 1111 R/W R/W Addr 0x1003E 31 Figure 4-27. LCL_ALRL 4.3.2.
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Part II. ConÞguration and Reset Table 4-12 describes SIUMCR Þelds. Table 4-12. SIUMCR Register Field Descriptions Bits Name Description 0 BBD Bus busy disable. 0 ABB/IRQ2 pin is ABB, DBB/IRQ3 pin is DBB 1 ABB/IRQ2 pin is IRQ2, DBB/IRQ3 pin is IRQ3 1 ESE External snoop enable. ConÞgures GBL/IRQ1 0 External snooping disabled. (GBL/IRQ1 pin is IRQ1.) 1 External snooping enabled. (GBL/IRQ1 pin is GBL.) 2 PBSE Parity byte select enable. 0 Parity byte select is disabled.
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Part II. ConÞguration and Reset Table 4-12. SIUMCR Register Field Descriptions (Continued) Bits 10Ð11 Name APPC Description Address parity pins conÞguration. Note that during power on reset the MODCK pins are used for PLL conÞguration. The pin multiplexing indicated in the table applies only to normal operation. Selection between IRQ7 and INT_OUT is according to CPU state. If the core is disabled, the pin is INT_OUT; otherwise it is IRQ7.
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Part II. ConÞguration and Reset 4.3.2.7 Internal Memory Map Register (IMMR) The internal memory map register (IMMR), shown in Figure 4-29, contains identiÞcation of a speciÞc device as well as the base address for the internal memory map. Software can deduce availability and location of any on-chip system resources from the values in IMMR. PARTNUM and MASKNUM are mask programmed and cannot be changed for any particular device.
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Part II. ConÞguration and Reset 4.3.2.8 System Protection Control Register (SYPCR) The system protection control register, shown in Figure 4-30, controls the system monitors, software watchdog period, and bus monitor timing. SYPCR can be read at any time but can be written only once after system reset.
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Part II. ConÞguration and Reset 4.3.2.9 Software Service Register (SWSR) The software service register (SWSR) is the location to which the software watchdog timer servicing sequence is written. To prevent software watchdog timer time-out, the user should write 0x556C followed by 0xAA39 to this register, which resides at 0x1000E. SWSR can be written at any time, but returns all zeros when read. 4.3.2.
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Part II. ConÞguration and Reset Table 4-15. TESCR1 Field Descriptions (Continued) Bits Name Description 6 EXT 7Ð9 TC Transfer code. Indicates the transfer code of the 60x bus transaction that caused the TEA. See Section 8.4.3.2, ÒTransfer Code Signals TC[0Ð2],Ó for a description of the various transfer codes. 10 Ñ Reserved, should be cleared. 11Ð15 TT Transfer type. These bits indicates the transfer type of the 60x bus transaction that caused the TEA. See Section 8.4.3.
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Part II. ConÞguration and Reset The TESCR2 register is described in Table 4-16. Table 4-16. TESCR2 Field Descriptions Bits Name 0 Ñ 1 2 Description Reserved, should be cleared. REGS Internal registers error. An error occurred in a transaction to the MPC8260Õs internal registers. DPR Dual port ram error. An error occurred in a transaction to the MPC8260Õs dual-port RAM. 3Ð6 Ñ 7 LCL Local bus bridge error. An error occurred in a transaction to the MPC8260Õs 60x bus to local bus bridge.
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Part II. ConÞguration and Reset The L_TESCR1 register bits are described in Table 4-17. Table 4-17. L_TESCR1 Field Descriptions Bits Name Description 0 BM Bus monitor time-out. Indicates that TEA was asserted due to the local bus monitor time-out. 1 Ñ Reserved, should be cleared. 2 PAR 3Ð4 Ñ 5 WP 6 Ñ Reserved, should be cleared. 7Ð9 TC Transfer code. These bits indicates the transfer code of the local bus transaction that caused the TEA. Section 8.4.3.
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Part II. ConÞguration and Reset Table 4-18 describes L_TESCR2 Þelds. Table 4-18. L_TESCR2 Field Descriptions Bits Name Description 0Ð11 Ñ Reserved, should be cleared. 12Ð15 PB Parity error on byte. There are four parity error status bits, one per 8-bit lane. A bit is set for the byte that had a parity error. 16Ð27 BNK Memory controller bank. There are twelve error status bits, one per memory controller bank. A bit is set for the local bus memory controller bank that had an error.
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Part II. ConÞguration and Reset Table 4-19. TMCNTSC Field Descriptions (Continued) Bits Name Description 14 TCF Time counter frequency. The input clock to the time counter may be either 4 MHz or 32 KHz. The user should set the TCF bit according to the frequency of this clock. 0 The input clock to the time counter is 4 MHz. 1 The input clock to the time counter is 32 KHz. See Section 4.1.2, ÒTimers ClockÓ for further details. 15 TCE Time counter enable. Is not affected by soft or hard reset.
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Part II. ConÞguration and Reset Bits 0 1 2 3 4 5 6 7 8 Field ALARM Reset Ñ R/W R/W Addr Bits 9 10 11 12 13 14 15 25 26 27 28 29 30 31 0x1022C 16 17 18 19 20 21 22 23 24 Field ALARM Reset Ñ R/W R/W Addr 0x1222E Figure 4-37. Time Counter Alarm Register (TMCNTAL) Table 4-20 describes TMCNTAL Þelds. Table 4-20. TMCNTAL Field Descriptions Bits Name Description 0Ð31 ALARM The alarm interrupt is generated when ALARM Þeld matches the corresponding TMCNT bits.
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Part II. ConÞguration and Reset Table 4-21 describes PISCR Þelds. Table 4-21. PISCR Field Descriptions Bits Name Description 0Ð7 Ñ Reserved, should be cleared. 8 PS Periodic interrupt status. Asserted if the PIT issues an interrupt. The PIT issues an interrupt after the modulus counter counts to zero. The PS bit can be negated by writing a one to PS. A write of zero has no effect on this bit. 9Ð12 Ñ Reserved, should be cleared. 13 PIE Periodic interrupt enable.
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Part II. ConÞguration and Reset Table 4-22 describes PITC Þelds. Table 4-22. PITC Field Descriptions Bits Name 0Ð15 PITC 16Ð31 Ñ Description Periodic interrupt timing count. Bits 0Ð15 are deÞned as the PITC, which contains the count for the periodic timer. Setting PITC to 0xFFFF selects the maximum count period. Reserved, should be cleared. 4.3.3.
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Part II. ConÞguration and Reset Table 4-24. Table 4-24.
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Part II.
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Chapter 5 Reset 50 50 The MPC8260 has several inputs to the reset logic: ¥ ¥ ¥ ¥ ¥ ¥ ¥ Power-on reset (PORESET) External hard reset (HRESET) External soft reset (SRESET) Software watchdog reset Bus monitor reset Checkstop reset JTAG reset All of these reset sources are fed into the reset controller and, depending on the source of the reset, different actions are taken. The reset status register, described in Section 5.2, ÒReset Status Register (RSR),Ó indicates the last sources to cause a reset. 5.
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Part II. ConÞguration and Reset 5.1.1 Reset Actions The reset block has a reset control logic that determines the cause of reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset. Soft reset initializes the internal logic while maintaining the system conÞguration. Table 5-2 identiÞes reset actions for each reset source. Table 5-2.
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Part II. ConÞguration and Reset Figure 5-3 shows the power-on reset ßow. PORESET Input External pin is asserted for min 16 RSTCONF is sampled for master determination PORESET Internal MODCK[1Ð3] are sampled. MODCK_HI bits are ready for PLL HRESET Output PLL is locked (no external indication) SRESET Output PLL locking period PORESET to internal logic is extended for 1024 CLKIN. HRESET /SRESET are extended for 512/515 CLKIN (respectively), from PLL lock time. Interval depends on PLL locking time.
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Part II. ConÞguration and Reset 5.2 Reset Status Register (RSR) The reset status register (RSR), shown in Figure 5-1, is memory-mapped into the MPC8260Õs SIU register map. Bits 0 1 2 3 4 5 6 7 8 9 10 Field Ñ R/W R/W Reset 0000_0000_0000_0000 Addr 0x10C90 Bits 16 Field 17 18 19 20 21 22 23 24 25 Ñ 26 11 12 13 14 15 27 28 29 30 31 JTRS CSRS R/W R/W Reset 0000_0000_0000_0011 Addr 0x10C92 SWRS BMRS ESRS EHRS Figure 5-1.
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Part II. ConÞguration and Reset Table 5-3. RSR Field Descriptions (Continued) Bits Name Function 30 ESRS External soft reset status. When an external soft reset event is detected, ESRS is set and it remains that way until software clears it. ESRS is cleared by writing a 1 to it (writing zero has no effect). 0 No external soft reset event has occurred 1 An external soft reset event has occurred 31 EHRS External hard reset status.
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Part II. ConÞguration and Reset 5.4 Reset ConÞguration Various features may be conÞgured during hard reset or power-on reset. For example, one conÞgurable features is core disable, which can be used to conÞgure a system that uses two MPC8260s, one a slave device and the other a the host with an active core. Most conÞgurable features are reconÞgured whenever HRESET is asserted. However, the clock mode is conÞgured only when PORESET is asserted.
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Part II. ConÞguration and Reset Table 5-6 shows addresses that should be used to conÞgure the various MPC8260s. Byte addresses that do not appear in this table have no effect on the conÞguration of the MPC8260 chips. The values of the bytes in Table 5-6 are always read on byte lane D[0Ð7] regardless of the port size. Table 5-6.
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Part II. ConÞguration and Reset 5.4.1 Hard Reset ConÞguration Word The contents of the hard reset conÞguration word are shown in Figure 5-3. Bits Field 0 1 2 3 EARB EXMC CDIS EBM 4 5 BPS Reset 6 7 8 CIP ISPS 9 L2CPC 10 11 DPPC 12 13 Ñ 14 15 ISB 0000_0000_0000_0000 Bits 16 17 Field BMS BBD Reset 18 19 MMR 20 21 22 LBPC 23 APPC 24 25 26 CS10PC 27 Ñ 28 29 30 31 MODCK_H 0000_0000_0000_0000 Figure 5-3.
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Part II. ConÞguration and Reset Table 5-7. Hard Reset Configuration Word Field Descriptions (Continued) Bits Name Description 13Ð15 ISB Initial internal space base select. DeÞnes the initial value of IMMR[0Ð14] and determines the base address of the internal memory space. 000 0x0000_0000 001 0x00F0_0000 010 0x0F00_0000 011 0x0FF0_0000 100 0xF000_0000 101 0xF0F0_0000 110 0xFF00_0000 111 0xFFF0_0000 See Section 4.3.2.7, ÒInternal Memory Map Register (IMMR).Ó 16 BMS Boot memory space.
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Part II. ConÞguration and Reset PORESET Vcc Configuration Slave Chip HRESET A[0Ð31] Vcc D[0Ð31] PORESET RSTCONF Figure 5-4. Single Chip with Default Configuration 5.4.2.2 Single MPC8260 ConÞgured from Boot EPROM For a conÞguration that differs from the default, the MPC8260 can be used as a conÞguration master by tying RSTCONF to GND as shown in Figure 5-5. The MPC8260 can access the boot EPROM. It is assumed the conÞguration is as deÞned there upon exiting hard reset.
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Part II. ConÞguration and Reset PORESET EPROM Control Signals Configuration Master Chip HRESET Address Bus VCC Boot EPROM A[..] A[0Ð31] PORESET D[0Ð7] D[0Ð31] HRESET PORESET Configuration Slave Chip 1 D[0Ð31] RSTCONF HRESET PORESET Data Bus RSTCONF A0 Configuration Slave Chip 2 D[0Ð31] RSTCONF A1 Configuration Slave Chip 7 HRESET PORESET D[0Ð31] RSTCONF A6 Figure 5-6. Configuring Multiple Chips MOTOROLA Chapter 5.
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Part II. ConÞguration and Reset In this system, the conÞguration master initially reads its own conÞguration word. It then reads other conÞguration words and drives them to the conÞguration slaves by asserting RSTCONF. As Figure 5-6 shows, this complex conÞguration is done without additional glue logic. The conÞguration master controls the whole process by asserting the EPROM control signals and the systemÕs address signals as needed. 5.4.2.
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Part III The Hardware Interface Intended Audience Part III is intended for system designers who need to understand how each MPC8260 signal works and how those signals interact. Contents Part III describes external signals, clocking, memory control, and power management of the MPC8260. It contains the following chapters: ¥ ¥ ¥ ¥ ¥ ¥ ¥ Chapter 6, ÒExternal Signals,Ó shows a functional pinout of the MPC8260 and describes the MPC8260 signals. Chapter 7, Ò60x Signals,Ó describes signals on the 60x bus.
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Part III. The Hardware Interface Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC8xx Documentation Supporting documentation for the MPC8260 can be accessed through the world-wide web at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical speciÞcations, reference materials, and detailed applications notes.
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Part III. The Hardware Interface n Indicates an undeÞned numerical value Â NOT logical operator & | AND logical operator OR logical operator Acronyms and Abbreviations Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. Table vi.
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Part III. The Hardware Interface Table vi.
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Part III. The Hardware Interface Table vi. Acronyms and Abbreviated Terms (Continued) Term Meaning UISA User instruction set architecture UPM User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter MOTOROLA Part III.
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Part III.
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Chapter 6 External Signals 60 60 This chapter describes the MPC8260 external signals. A more detailed description of 60x bus signals is provided in Chapter 8, ÒThe 60x Bus.Ó 6.1 Functional Pinout Figure 6-1 shows MPC8260 signals grouped by function. Note that many of these signals are multiplexed and this Þgure does not indicate how these signals are multiplexed. NOTE A bar over a signal name indicates that the signal is active lowÑfor example, BB (bus busy).
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Part III.
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Part III. The Hardware Interface Table 6-1. External Signals Signal Description BR 60x bus requestÑThis is an output when an external arbiter is used and an input when an internal arbiter is used. As an output the MPC8260 asserts this pin to request ownership of the 60x bus. As an input an external master should assert this pin to request 60x bus ownership from the internal arbiter. BG 60x bus grantÑThis is an output when an internal arbiter is used and an input when an external arbiter is used.
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Part III. The Hardware Interface Table 6-1. External Signals (Continued) Signal Description DBB IRQ3 60x data bus busyÑ(Input/output)As an output the MPC8260 asserts this pin for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the MPC8260 negates DBB for a fraction of a bus cycle and than stops driving this pin. As an input, the MPC8260 does not assume 60x data bus ownership as long as it senses DBB asserted by an external 60x bus master.
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Part III. The Hardware Interface Table 6-1. External Signals (Continued) Signal Description IRQ5 DP[5] TBEN EXT_DBG3 Interrupt request 5ÑThis input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. 60x data parity 5Ñ(Input/output)The 60x agent that drives the data bus drives also the data parity signals.
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Part III. The Hardware Interface Table 6-1. External Signals (Continued) Signal Description WT BADDR30 IRQ3 Write throughÑOutput used for L2 cache control. For each core-initiated MPC8260 60x transaction, the state of this pin indicates if the transaction should be cached using write-through or copy-back mode. Assertion of WT indicates that the transaction should be cached using the write-through mode. Burst address 30ÑThere are Þve burst address output pins.
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Part III. The Hardware Interface Table 6-1. External Signals (Continued) Signal Description BADDR[27Ð28] Burst address 27:28ÑThere are Þve burst address output pins. These pins are outputs of the 60x memory controller. Used in external master conÞguration and connected directly to the memory devices controlled by MPC8260Õs memory controller. ALE BCTL0 Address latch enableÑThis output pin controls the external address latch that should be used in external master 60x bus conÞguration.
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Part III. The Hardware Interface Table 6-1. External Signals (Continued) Signal Description LWE[0Ð3] LSDDQM[0Ð3] LBS[0Ð3] Local bus write enableÑThe write enable pins are outputs of the Local bus GPCM. These pins select speciÞc byte lanes for write operations. Local bus SDRAM DQMÑThe DQM pins are outputs of the SDRAM control machine. These pins select speciÞc byte lanes of SDRAM devices. Local bus UPM byte selectÑThe byte select pins are outputs of the UPM in the memory controller.
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Part III. The Hardware Interface Table 6-1. External Signals (Continued) Signal Description L_A15 SMI PCI_FRAME Local bus address 15ÑLocal bus address bit 15 output pin. In the local address bus bit 14 is most signiÞcant and bit 31 is least signiÞcant. System management interruptÑSystem management interrupt input to the core. PCI frameÑPCI cycle frame input output pin. Used by the current PCI master to indicate the beginning and duration of an access.
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Part III. The Hardware Interface Table 6-1. External Signals (Continued) Signal Description L_A24 PCI_REQ1 Local bus address 24ÑLocal bus address bit 24 output pin. In the local address bus bit 14 is most signiÞcant and bit 31 is least signiÞcant. PCI arbiter request 1ÑPCI request 1 input pin. When MPC8260Õs internal PCI arbiter is used, assertion of this pin indicates that an external PCI agent is requesting the PCI bus. L_A25 PCI_GNT0 Local bus address 25ÑLocal bus address bit 25 output pin.
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Part III. The Hardware Interface Table 6-1. External Signals (Continued) Signal Description LCL_DP[0Ð3] PCI_C/BE[0Ð3] Local bus data parityÑLocal bus data parity input/output pins. In local bus write operations the MPC8260 drives these pins. In local bus read operations the accessed device drives these pins. LCL_DP[0] is driven with a value that gives odd parity with LCL_D[0Ð7]. LCL_DP[1] is driven with a value that gives odd parity with LCL_D[8Ð15].
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Part III. The Hardware Interface Table 6-1. External Signals (Continued) Signal Description MODCK2 AP[2] TC[1] BNKSEL[1] MODCK2ÑClock mode input. DeÞnes the operating mode of internal clock circuits. Address parity 2Ñ(Input/output)The 60x master that drives the address bus, drives also the address parity signals. The value driven on address parity 2 pin should give odd parity (odd number of 1s) on the group of signals that includes address parity 2 and A[16Ð23].
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Chapter 7 60x Signals 70 70 This chapter describes the MPC8260 PowerPC processorÕs external signals. It contains a concise description of individual signals, showing behavior when a signal is asserted and negated, when the signal is an input and an output, and the differences in how signals work in external-master or internal-only conÞgurations. NOTE A bar over a signal name indicates that the signal is active lowÐ for example, ARTRY (address retry) and TS (transfer start).
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Part III. The Hardware Interface ¥ Data transfer signalsÑThese signals, which consist of the data bus, data parity, and data parity error signals, transfer the data and ensure its integrity. ¥ Data transfer termination signalsÑData termination signals are required after each data beat in a data transfer. In a single-beat transaction, the data termination signals also indicate the end of the tenure.
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Part III. The Hardware Interface 7.2 Signal Descriptions This section describes individual MPC8260 60x signals, grouped according to Figure 7-1. Note that the following sections brießy summarize signal functions. Chapter 8, ÒThe 60x Bus,Ó describes many of these signals in greater detail, both in terms of their function and how groups of signals interact. 7.2.
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Part III. The Hardware Interface 7.2.1.1.2 Address Bus Request (BR)ÑInput Following are the state meaning and timing comments for the BR signal input in external master mode. State Meaning AssertedÑIndicates that the external master has a bus transaction to perform and is waiting for a qualiÞed BG to begin the address tenure. BR may be asserted even if the two possible pipelined address tenures have already been granted.
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Part III. The Hardware Interface NegationÑMay occur whenever the MPC8260 must be prevented from using the address bus. The MPC8260 may still assume address bus ownership on the cycle BG is negated if it was asserted the previous cycle with other bus grant qualiÞcations. 7.2.1.2.2 Bus Grant (BG)ÑOutput Following are the state meaning and timing comments for the BG signal output in external master mode.
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Part III. The Hardware Interface 7.2.1.3.2 Address Bus Busy (ABB)ÑInput Following are the state meaning and timing comments for the ABB input signal. State Meaning AssertedÑIndicates that external device is the address bus master. NegatedÑIndicates that the address bus may be available for use by the MPC8260 (see BG). The MPC8260 also tracks the state of ABB on the bus from the TS and AACK inputs. (See section on address arbitration phase.
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Part III. The Hardware Interface Timing Comments Assertion/NegationÑMust be asserted for one cycle only and then immediately negated. Assertion may occur at any time during the assertion of ABB. 7.2.3 Address Transfer Signals In internal only mode the memory controller uses these signals for glueless address transfers to memory and I/O devices. The address transfer signals are used to transmit the address. 7.2.3.
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Part III. The Hardware Interface 7.2.4.1 Transfer Type (TT[0Ð4]) The transfer type signals (TT[0Ð4]) consist of Þve input/output signals on the MPC8260. For a complete description of TT[0Ð4] signals and transfer type encoding, see Section 8.4.3.1, ÒTransfer Type Signal (TT[0Ð4]) Encoding.Ó 7.2.4.1.1 Transfer Type (TT[0Ð4])ÑOutput Following are the state meaning and timing comments for the TT[0Ð4] output signals on the MPC8260. State Meaning Asserted/NegatedÑSpeciÞes the type of transfer in progress.
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Part III. The Hardware Interface High ImpedanceÑSame as A[0Ð31]. 7.2.4.4 Global (GBL) The global (GBL) signal is an input/output signal on the MPC8260. 7.2.4.4.1 Global (GBL)ÑOutput Following are the state meaning and timing comments for the GBL output signal. State Meaning AssertedÑIndicates that the transaction is global and should be snooped by other devices. GBL reßects the M bit (WIM bits) from the MMU except during certain transactions.
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Part III. The Hardware Interface NegatedÑIndicates that the transaction should not operate in writethrough mode. Timing Comments Assertion/NegationÑSame as A[0Ð31]. High ImpedanceÑSame as A[0Ð31]. 7.2.5 Address Transfer Termination Signals The address transfer termination signals are used to indicate either that the address phase of the transaction has completed successfully or must be repeated, and when it should be terminated. For detailed information about how these signals interact, see Section 7.2.
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Part III. The Hardware Interface 7.2.5.2 Address Retry (ARTRY) The address retry (ARTRY) signal is both an input and output signal on the MPC8260 7.2.5.2.1 Address Retry (ARTRY)ÑOutput .Following are the state meaning and timing comments for ARTRY as an output signal. State Meaning AssertedÑIndicates that the MPC8260 detects a condition in which an address tenure must be retried.
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Part III. The Hardware Interface 7.2.6 Data Bus Arbitration Signals The data bus arbitration signals have no meaning in internal-only mode. Like the address bus arbitration signals, data bus arbitration signals maintain an orderly process for determining data bus mastership. Note that there is no data bus arbitration signal equivalent to the address bus arbitration signal BR (bus request), because, except for address-only transactions, TS implies data bus requests.
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Part III. The Hardware Interface 7.2.6.2 Data Bus Busy (DBB) The data bus busy (DBB) signal is both an input and output signal on the MPC8260 7.2.6.2.1 Data Bus Busy (DBB)ÑOutput Following are the state meaning and timing comments for the DBB output signal. State Meaning AssertedÑIndicates that the MPC8260 is the data bus master. The MPC8260 always assumes data bus mastership if it needs the data bus and determines a qualiÞed data bus grant (see DBG).
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Part III. The Hardware Interface 7.2.7.1.1 Data Bus (D[0Ð63])ÑOutput Following are the state meaning and timing comments for the D[0Ð63] output signals. State Meaning Asserted/NegatedÑRepresents the state of data during a data write. Byte lanes not selected for data transfer do not supply valid data. MPC8260 duplicates data to enable valid data to be sent to different port sizes.
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Part III. The Hardware Interface Table 7-1. DP[0Ð7] Signal Assignments Signal Name Data Bus Signal Assignments DP0 D[0Ð7] DP1 D[8Ð15 DP2 D[16Ð23] DP3 D[24Ð31] DP4 D[32Ð39] DP5 D[40Ð47] DP6 D[48Ð55] DP7 D[56Ð63] Timing Comments Assertion/NegationÑThe same as the data bus. High ImpedanceÑThe same as the data bus. 7.2.7.2.2 Data Bus Parity (DP[0Ð7])ÑInput Following are the state meaning and timing comments for the DP input signals.
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Part III. The Hardware Interface NegatedÑ(During assertion of DBB) indicates that, until TA is asserted, the MPC8260 must continue to drive the data for the current write or must wait to sample the data for reads. Timing Comments AssertionÑMust not occur before AACK for the current transaction (if the address retry mechanism is to be used to prevent invalid data from being used by the MPC8260); otherwise, assertion may occur at any time during the assertion of DBB.
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Part III. The Hardware Interface NegatedÑIndicates that no bus error was detected. Timing Comments AssertionÑMay be asserted while DBB is asserted and for the cycle after is TA is asserted during a read operation. TEA should be asserted for one cycle only. NegationÑTEA must be negated no later than the negation of DBB. 7.2.8.2.2 Transfer Error Acknowledge (TEA)ÑOutput Following are the state meaning and timing comments for the TEA output. State Meaning AssertedÑIndicates that a bus error has occurred.
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Part III. The Hardware Interface system can assert PSDVAL for one bus clock cycle and then negate it to insert wait states during the next beat. (Note: when the MPC8260 Processor is conÞgured for 1:1 clock mode and is performing a burst read into the data cache, the MPC8260 requires two wait state between the assertion of TS and the Þrst assertion of PSDVAL for that transaction, or 1 wait state for 1.5:1 clock mode.) 7.2.8.3.
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Chapter 8 The 60x Bus 80 80 The 60x bus, which is used by PowerPC processors, provides ßexible support for the onchip PowerPC MPC603 processor as well as other internal and external bus devices. The 60x bus supports 32-bit addressing, a 64-bit data bus, and burst operations that transfer as many as 256 bits of data in a four-beat burst. The 60x data bus can be accessed in 8-, 16-, 32-, and 64-bit data ports.
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Part III. The Hardware Interface Table 8-1. Terminology (Continued) Term Lane DeÞnition A sub-grouping of signals within a bus. An 8-bit section of the address or data bus may be referred to as a byte lane for that bus. Master The device that owns the address or data bus, the device that initiates or requests the transaction. ModiÞed IdentiÞes a cache block The M state in a MESI or MEI protocol. Parking Granting potential bus mastership without requiring a bus request from that device.
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Part III. The Hardware Interface MPC8260 APE TS Latch & A[0Ð31] DRAM MUX I/O TT[0Ð4] TBST CI WT Address + Attributes TSIZ[0Ð3] MEM GBL ARTRY DBG D[0Ð63] DP[0Ð7] TA Memory Controller Signals Data + Attributes AACK TEA Memory Control Signals Figure 8-1. Single MPC8260 Bus Mode Note that in single MPC8260 bus mode, the MPC8260 uses the address bus as a memory address bus. Slaves cannot use the 60x bus signals because the addresses have memory timing, not address tenure timing. 8.2.
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Part III. The Hardware Interface MPC8260 APE TS BR BG TS A[0Ð31] AP[0Ð3] Latch I/O TT[0Ð4] TSIZ[0Ð3] GBL AACK ARTRY Data + Attributes WT Address + Attributes CI Memory Controller Signals TBST Latch & MEM DRAM MUX DBG External Device Memory Control Signals BR D[0Ð63] BG DP[0Ð7] DBG TA TEA Figure 8-2. 60x-Compatible Bus Mode 8.
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Part III. The Hardware Interface deÞned by the 60x bus speciÞcation. For more information, see Section 8.5.5, ÒPort Size Data Bus Transfers and PSDVAL Termination.Ó Data Tenure Arbitration 1- or 4-Beat Transfer Termination Independent Address and Data Tenures Next Address Tenure Arbitration Transfer Termination Figure 8-3.
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Part III. The Hardware Interface external central bus arbiter or by the internal on-chip arbiter. In the latter case, the system is optimized for three external bus masters besides the MPC8260. The arbitration conÞguration (external or internal) is determined at system reset by sampling conÞguration pins. See Section 10.9, ÒExternal Master Support (60x-Compatible Mode),Ó for more information. The MPC8260 controls bus access through the bus request (BR) and bus grant (BG) signals.
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Part III. The Hardware Interface 8.3.2 Address Pipelining and Split-Bus Transactions The 60x bus protocol provides independent address and data bus capability to support pipelined and split-bus transaction system organizations. Address pipelining allows the next address tenure to begin before the current data tenure has Þnished. Although this ability does not inherently reduce memory latency, support for address pipelining and splitbus transactions can greatly improve effective bus/memory throughput.
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Part III. The Hardware Interface transaction, it skips the bus request delay and assumes address bus mastership on the next cycle. For this case, BR is not asserted and the access latency seen by the device is shortened by one cycle. The MPC8260 and external device bus devices qualify BG by sampling ARTRY in the negated state prior to taking address bus mastership. The negation of ARTRY during the address retry window (one cycle after the assertion of AACK) indicates that no address retry is requested.
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Part III. The Hardware Interface CLKOUT BR INT MPC8260 BG INT BR BG ABB ADDR+ MPC8260 External External TS AACK ARTRY Figure 8-4. Address Bus Arbitration with External Bus Master 8.4.2 Address Pipelining The MPC8260 supports one-level address pipelining by asserting AACK to the current bus master when its data tenure starts and by granting the address bus to the next requesting device before the current data bus tenure completes.
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Part III. The Hardware Interface CLKOUT ADDR + ATTR TS AACK DBG TA Address Tenure Address 1 Address 2 Data Tenure Data 1 Data 2 Figure 8-5. Address Pipelining 8.4.3 Address Transfer Attribute Signals During the address transfer, the address is placed on the address signals, A[0Ð31]. The bus master provides other signals that characterize the address transferÑtransfer type (TT[0Ð 4]), transfer code (TC[0Ð2]), transfer size (TSIZ[0Ð3]), and transfer burst (TBST) signals.
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Part III. The Hardware Interface Table 8-2. Transfer Type Encoding (Continued) 60x Bus SpeciÞcation2 MPC8260 as Bus Master TT[0Ð4]1 Command Transaction Bus Trans. Transaction Source MPC8260 as Snooper MPC8260 as Slave Action on Hit Action on Slave Hit 01000 sync Address only Address only (if sync (if enabled) enabled) Not applicable Assert AACK. BG is to MPC8260 negated until MPC8260 buffers are ßushed.
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Part III. The Hardware Interface Table 8-2. Transfer Type Encoding (Continued) 60x Bus SpeciÞcation2 MPC8260 as Bus Master TT[0Ð4]1 Command Transaction Bus Trans. Transaction Source MPC8260 as Snooper MPC8260 as Slave Action on Hit Action on Slave Hit 01110 Read with intent to modify Burst Burst Load miss, store miss, Flush or I-fetch Read, assert AACK and TA.
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Part III. The Hardware Interface 8.4.3.2 Transfer Code Signals TC[0Ð2] The transfer code signals, TC[0Ð2], provide supplemental information about the corresponding address (mainly regarding the source of the transaction). Note that TCx signals can be used with the TT[0Ð4] and TBST to further deÞne the current transaction.
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Part III. The Hardware Interface Table 8-4.
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Part III. The Hardware Interface Table 8-6. Aligned Data Transfers Data Bus Byte Lanes Program Transfer Size Byte Half-Word Word Double-Word TSIZ[0Ð3] A[29Ð31] D0... ...D31 D32... ...
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Part III. The Hardware Interface software attempt to align code and data where possible. Table 8-7. Unaligned Data Transfer Example (4-Byte Example) Data Bus Byte Lanes Program Size of Word (4 bytes) TSIZ[1Ð3] A[29Ð31] D0... ...D31 D32... ...
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Part III. The Hardware Interface Interface Output Register 0 31 OP0 D[0Ð7] OP0 OP1 OP2 D[8Ð15] OP1 OP3 D[15Ð23] OP2 D[24Ð31] OP3 63 OP4 OP5 D[32Ð39] OP4 D[40Ð47] OP5 OP6 D[48Ð55] OP6 OP7 D[56Ð63] OP7 64-Bit Port Size OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 32-Bit Port Size 16-Bit Port Size 8-Bit Port Size OP7 Figure 8-6. Interface to Different Port Size Devices MOTOROLA Chapter 8.
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Part III. The Hardware Interface Table 8-8.
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Part III. The Hardware Interface Table 8-9.
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Part III. The Hardware Interface Table 8-10.
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Part III. The Hardware Interface bus, but some slaves or masters do not support these features. Clear BCR[ETM] to disable this type of transaction. This places the MPC8260 in strict 60x bus mode. The following tables are extensions to Table 8-9, Table 8-8, and Table 8-10. Table 8-11 lists the patterns of the extended data transfer for write cycles when MPC8260 initiates an access. Note that 16- and 24-byte transfers are always eight-byte aligned and use a 64-bit or less port size. Table 8-11.
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Part III. The Hardware Interface Table 8-13.
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Part III. The Hardware Interface 8.4.4 Address Transfer Termination Address transfer termination occurs with the assertion of the address acknowledge (AACK) signal, or retried with the assertion of ARTRY. ARTRY must remain asserted until one clock after AACK; the bus clock cycle after AACK is called the ARTRY window. The MPC8260 controls assertion of AACK unless the cycle is claimed by an external slave, such as an external L2 cache controller.
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Part III. The Hardware Interface CLKOUT BR INT BG INT BR External BG ABB ADDR + ATTR MPC8260 External MPC8260 TS AACK ARTRY Figure 8-7. Retry Cycle As a bus master, the MPC8260 recognizes either an early or qualiÞed ARTRY and prevents the data tenure associated with the retried address tenure. If the data tenure has begun, the MPC8260 terminates the data tenure immediately even if the burst data has been received.
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Part III. The Hardware Interface also detect this event and abort any transfer in progress. If this TA/ARTRY relationship is not met, the master may enter an undeÞned state. Users may use PPC_ACR[DBGD] to ensure correct operation of the system. During the clock of a qualiÞed ARTRY, each device master determines whether it should negate BR and ignore BG on the following cycle. The following cycle is referred to as the window-of-opportunity for the snooping master.
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Part III. The Hardware Interface 8.4.5 Pipeline Control The MPC8260 supports the two following modes: ¥ One-level pipeline modeÑTo maintain the one-level pipeline, AACK is not asserted for a pipelined address tenure until the current data tenure ends. In 60x-compatible bus mode, a two-level pipeline depth can occur (for example, when an external 60xbus slave does not support one-level pipelining).
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Part III. The Hardware Interface ¥ following cycle. In case the external arbiter asserts DBG on the cycle in which TS was asserted, PPC_ACR[DBGD] should be zero. Otherwise, PPC_ACR[DBGD] should be set. External masters connected to the 60x bus must assert DBB only for the duration of its data tenure. External masters should not use DBB to prevent other masters from using the data bus after their data tenure has ended. 8.5.
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Part III. The Hardware Interface ¥ Asserting ARTRY causes the data tenure to be terminated immediately if the ARTRY is for the address tenure associated with the data tenure in operation (the data tenure may not be terminated due to address pipelining). The earliest allowable assertion of TA depends directly on the latest possible assertion of ARTRY. Figure 8-8 shows both a single-beat and burst data transfer. The MPC8260 asserts TA to mark the cycle in which data is accepted.
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Part III. The Hardware Interface Figure 8-9 shows an extended transaction of 4 words to a port size of 32 bits. The singlebeat transaction is translated to four port-sized beats. CLKOUT ADDR + ATTR TS AACK DBG PSDVAL TA D[0Ð31] D0 D1 D2 D3 Figure 8-9. 128-Bit Extended Transfer to 32-Bit Port Size Figure 8-10 shows a burst transfer to a 32-bit port. Each double-word burst beat is divided into two port-sized beats such that the four double words are transferred in eight beats.
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Part III. The Hardware Interface CLKOUT ADDR + ATTR TS AACK DBG PSDVAL TA D[0Ð31] D0 D1 D2 D3 D4 D5 D6 D7 Figure 8-10. Burst Transfer to 32-Bit Port Size 8.5.6 Data Bus Termination by Assertion of TEA If a device initiates a transaction that is not supported by the MPC8260, the MPC8260 signals an error by asserting TEA.
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Part III. The Hardware Interface CLKOUT ADDR + ATTR For Single For Burst TS AACK DBG TA TEA Data Figure 8-11. Data Tenure Terminated by Assertion of TEA MPC8260 interprets the following bus transactions as bus errors: ¥ ¥ Direct-store transactions, as indicated by the assertion of XATS. Bus errors asserted by slaves (internal or external). 8.
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Part III. The Hardware Interface When the MPC8260 processor is not the address bus master, GBL is an input. The MPC8260 processor snoops a transaction if TS and GBL are asserted together in the same bus clock cycle (a qualiÞed snooping condition). No snoop update to the MPC8260 processor cache occurs if the transaction is not marked global. This includes invalidation cycles.
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Part III. The Hardware Interface 8.7.1 Support for the lwarx/stwcx. Instruction Pair The load word and reserve indexed (lwarx) and the store word conditional indexed (stwcx.) instructions provide a way to update memory atomically by setting a reservation on the load and checking that the reservation is still valid before the store is performed. In the MPC8260, reservations are made on behalf of aligned, 32-byte sections of the memory address space.
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Part III.
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Chapter 9 Clocks and Power Control 90 90 The MPC8260Õs clocking architecture includes two PLLsÑthe main PLL and the core PLL. The clock block, which contains the main PLL, provides the following: ¥ ¥ Internal clocks for all blocks in the chip except core blocks The internal 60x bus clock in the chip The core input clock has the 60x bus frequency, which the core PLL multiplies by a conÞgurable factor and provides to all core blocks.
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Part III. The Hardware Interface 9.2 Clock ConÞguration To conÞgure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the MODCK[1Ð3] pins are sampled while HRESET is asserted. Table 9-1 shows the eight basic conÞguration modes. Another 49 modes are available by using the conÞguration pin (RSTCONF) and driving four pins on the data bus. Table 9-1.
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Part III. The Hardware Interface Table 9-2.
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Part III. The Hardware Interface Table 9-2. Clock Configuration Modes (Continued) MODCK_HÐMODCK[1Ð3] Input Clock Frequency CPM Multiplication Factor CPM Frequency Core Multiplication Factor Core Frequency 0101_110 66 MHz 2 133 MHz 2.5 166 MHz 0101_111 66 MHz 2 133 MHz 3 200 MHz 0110_000 66 MHz 2 133 MHz 3.5 233 MHz 0110_001 66 MHz 2 133 MHz 4 266 MHz 0110_010 66 MHz 2 133 MHz 4.5 300 MHz 0110_011 66 MHz 2.5 166 MHz 2 133 MHz 0110_100 66 MHz 2.5 166 MHz 2.
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Part III. The Hardware Interface 9.3 External Clock Inputs The input clock source to the PLL is an external clock oscillator at the bus frequency. The PLL skew elimination between the CLOCKIN pin and the internal bus clock is guaranteed. 9.4 Main PLL The main PLL performs frequency multiplication and skew elimination.
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Part III. The Hardware Interface The direction selected depends on whether the feedback signal phase lags or leads the reference signal. The output of the charge pump drives the VCO whose output frequency is divided and fed back to the phase comparator for comparison with the reference signal, CLKIN. Ranging between 1 and 4,096, the PLL multiplication factor is held in the system clock mode register (SCMR[PLLMF]). Also, when the PLL is operating, its output frequency is twice the CPM frequency.
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Part III. The Hardware Interface 9.6.1 General System Clocks The general system clocks (CPM_CLK, CPM_CLK_90) are the basic clocks supplied to most modules and sub-modules on the CPM. The following points should be kept in mind: ¥ ¥ BUS_CLK and BUS_CLK_90 are supplied to the 60x bus and to the core. Many modules use both clocks (SIU, serials) ¥ The external clock, CLKIN, is the same as BUS_CLK 9.7 PLL Pins Table 9-3 shows dedicated PLL pins. Table 9-3.
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Part III. The Hardware Interface VDD VCCSYN 10 W 10 µF 0.1 µF Figure 9-2. PLL Filtering Circuit 9.8 System Clock Control Register (SCCR) The system clock control register (SCCR), shown in Figure 9-3, is memory-mapped into the MPC8260Õs internal space. Bits 0 1 2 3 4 5 6 7 Field 8 9 10 11 12 13 14 15 25 26 27 28 29 30 31 Ñ Reset Ñ R/W R/W Addr 0x10C80 Bits 16 17 18 19 20 21 22 Field Ñ Reset Ñ 23 24 R/W R/W Addr 0x10C82 CLPD DFBRG 0 01 Figure 9-3.
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Part III. The Hardware Interface Table 9-4. SCCR Field Descriptions Defaults Bits Name Description POR 30Ð31 DFBRG 01 Hard Reset Unaffected Division factor of BRGCLK from VCO_OUT (twice the CPM clock). DeÞnes the BRGCLK frequency. Changing the value does not result in a loss of lock condition. The BRGCLK is divided from the CPM clock. 00 Divide by 4 01 Divide by 16 (normal operation) 10 Divide by 64 11 Divide by 128 9.
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Part III. The Hardware Interface Table 9-5. SCMR Field Descriptions (Continued) Defaults Bits Name Description POR Hard Reset 19 PLLDF ConÞg pins Unaffected PLL pre-divider value. Ensures that PLLMF is an integer value regardless of whether CPM_CLK/CLKIN is an integer. 0 The ratio, CPM_CLK/CLKIN, is an integer 1 The ratio, CPM_CLK/CLKIN, is not an integer PLL division factor can be either 1 or 2. 20Ð31 PLLMF ConÞg pins Unaffected PLL multiplication factor.
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Chapter 10 Memory Controller 100 100 The memory controller is responsible for controlling a maximum of twelve memory banks shared by a high performance SDRAM machine, a general-purpose chip-select machine (GPCM), and three user-programmable machines (UPMs). It supports a glueless interface to synchronous DRAM (SDRAM), SRAM, EPROM, ßash EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other peripherals.
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Part III. The Hardware Interface The MPC8260 supports the following new features as compared to the MPC860 and MPC850. ¥ The synchronous DRAM machine enables back-to-back memory read or write operations using page mode, pipelined operation and bank interleaving for high-performance systems. ¥ The memory controller supports the local bus and the 60x bus in parallel. The 60x bus and the local bus share twelve memory banks as well as two SDRAM machines, three user-programmable machines (UPMs) and GPCMs.
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Part III.
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Part III.
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Part III.
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Part III. The Hardware Interface MxMR[BS] Bank 0 MS 60x Bank 1 MS Bank 2 MS User-Programmable Machine (A/B/C) Local 60x SDRAM Machine Bank 3 60x MS Local SDRAM Machine 60x General-Purpose Chip-Select Machine Bank 10 MS Bank11 MS Local General-Purpose Chip-Select Machine Local 60x Local Figure 10-2. Memory Controller Machine Selection Some features are common to all machines.
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Part III. The Hardware Interface EPROM MPC8260 GPCM Address CS0 GPL1/OE BS/WE[0Ð7] Data Address CE OE WE Data DRAM CS1 UPMA GPLx Address RAS CAS[0Ð7] W Data Figure 10-3. Simple System Configuration Implementation differences between the supported machines are described in the following: ¥ The SDRAM machine provides a glueless interface to JEDEC-compliant SDRAM devices, and using SDRAM pipelining, page mode, and bank interleaving delivers very high performance.
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Part III. The Hardware Interface selected according to the type of external access transacted. At every clock cycle, the logical value of the external signals speciÞed in the RAM array is output on the corresponding UPM pins. Figure 10-4 shows a basic conÞguration. Internal/External Memory Access Request Select Address (A), Address Type (AT) Address Comparator Bank Select MS/BS Fields SDRAM Machine UPMx GPCM Signals Timing Generator MUX External Signals Figure 10-4.
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Part III. The Hardware Interface 10.2.2 Page Hit Checking The SDRAM machine supports page-mode operation. Each time a page is activated on the SDRAM device, the SDRAM machine stores its address in a page register. The page information, which the user writes to the ORx register, is used along with the bank size to compare page bits of the address to the page register each time a bus-cycle access is requested. If a match is found together with bank match, the bus cycle is deÞned as a page hit.
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Part III. The Hardware Interface 10.2.7 Data Buffer Controls (BCTLx) The memory controller provides two data buffer controls for the 60x bus (BCTL0 and BCTL1) and one for the local bus (LWR). These controls are activated when a GPCM- or UPM-controlled bank is accessed. The BCTLx controls can be disabled by setting ORx[BCTLD]. Access to SDRAM-machine controlled bank does not activate the BCTLx controls.
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Part III. The Hardware Interface Note that this feature cannot be used with L2 cacheable banks and that in systems that involve both PowerQUICC II-type masters and 60x compatible master, this feature can still be used on the 60x bus under the following restrictions: 1. The arbiter and the memory controller are in the same MPC8260. 2. The register Þeld BCR[NPQM] is setup correctly. See ÒSection 10.9, ÒExternal Master Support (60x-Compatible ÒSection 4.3.2.1, ÒBus ConÞguration Register (BCR).
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Part III. The Hardware Interface 10.2.13 Partial Data Valid Indication (PSDVAL) The 60x and local buses have an internal 64-bit data bus. According to the 60x bus speciÞcation, TA is asserted when up to a double word of data is transferred. Because the MPC8260 supports memories with port sizes smaller than 64 bits, there is a need for partial data valid indication. The memory controller uses PSDVAL to indicate that data is latched by the memory on write accesses or valid data is present on read accesses.
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Part III. The Hardware Interface Clock External Data Bus (32 msb) Upper 4 bytes Lower 4 bytes PSDVAL Internal Data Bus (32 msb) Upper 4 bytes Internal Data Bus (32 lsb) Lower 4 bytes TA Figure 10-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer 10.3 Register Descriptions Table 10-2 lists registers used to control the 60x bus memory controller. Table 10-2. 60x Bus Memory Controller Registers Abbreviation BR0ÐBR11 Name Reference Base register banks 0Ð11 Section 10.3.
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Part III. The Hardware Interface 10.3.1 Base Registers (BRx) The base registers (BR0ÐBR11) contain the base address and address types that the memory controller uses to compare the address bus value with the current address accessed. Each register also includes a memory attribute and selects the machine for memory operation handling. Figure 10-6 shows the BRx register format. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Field BA Reset Depends on reset conÞguration sequence. See Section 5.4.
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Part III. The Hardware Interface Table 10-3. BRx Field Descriptions (Continued) Bits Name Description 23 WP Write protect. Can restrict write accesses within the address range of a BR. An attempt to write to this address range while WP = 1 can cause TEA to be asserted by the bus monitor logic (if enabled) which terminates the cycle. 0 Read and write accesses are allowed. 1 Only read accesses are allowed. The memory controller does not assert CSx and PSDVAL on write cycles to this memory bank.
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Part III. The Hardware Interface 10.3.2 Option Registers (ORx) The ORx registers deÞne the sizes of memory banks and access attributes. The ORx attributes bits support the following three modes of operation as deÞned by BR[MS]. ¥ ¥ ¥ SDRAM mode GPCM mode UPM mode Figure 10-7 shows the ORx as it is formatted for SDRAM mode. Bit 0 1 2 3 4 Field 5 6 7 8 9 10 11 12 SDAM 13 14 15 LSDAM...
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Part III. The Hardware Interface Table 10-4. ORx Field Descriptions (SDRAM Mode) (Continued) Bits Name Description 5Ð11 SDAM SDRAM address mask. Provides masking for corresponding bits in the associated BRx. By masking address bits independently, SDRAM devices of different size address ranges can be used. Any clear bit masks the corresponding address bit. Any set bit causes the corresponding address bit to be compared with the address pins.
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Part III. The Hardware Interface Table 10-4. ORx Field Descriptions (SDRAM Mode) (Continued) Bits Name Description 27 IBID Internal bank interleaving within same device disable. Setting this bit disables bank interleaving between internal banks of a SDRAM device connected to the chip-select line. IBID should be set in 60x-compatible mode if the SDRAM device is not connected to the BANKSEL pins. 28Ð31 Ñ Reserved, should be cleared. Figure 10-8 shows ORx as it is formatted for GPCM mode.
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Part III. The Hardware Interface Table 10-5. ORxÑGPCM Mode Field Descriptions (Continued) Bits Name 21Ð22 ACS Description Address to chip select setup. Can be used when the external memory access is handled by the GPCM. It allows the delay of the CS assertion relative to the address change.
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Part III. The Hardware Interface Figure 10-9 shows ORx as it is formatted for UPM mode.
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Part III. The Hardware Interface 10.3.3 60x SDRAM Mode Register (PSDMR) The 60x SDRAM mode register (PSDMR), shown in Figure 10-10, is used to conÞgure operations pertaining to SDRAM.
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Part III. The Hardware Interface Table 10-7. PSDMR Field Descriptions (Continued) Bits Name Description 8Ð10 BSMA Bank select multiplexed address line. Selects the address pins to serve as bank-select address for the 60x SDRAM. The bank select address can also be output on the BANKSEL pins (optional). See Section 10.4.5.1, ÒSDRAM Address Multiplexing (SDAM and BSMA).Ó 000 A12ÐA14 001 A13ÐA15 010 A14ÐA16 011 A15ÐA17 100 A16ÐA18 101 A17ÐA19 110 A18ÐA20 111 A19ÐA21 11Ð13 SDA10 ÒA10Ó control.
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Part III. The Hardware Interface Table 10-7. PSDMR Field Descriptions (Continued) Bits Name 23 BL Description Burst length 0 SDRAM burst length is 4. Use this value if the device port size is 64 or 16 1 SDRAM burst length is 8. Use this value if the device port size is 32 or 8 24Ð25 LDOTOPRE Last data out to precharge. DeÞnes the earliest timing for PRECHARGE command after the last data was read from the SDRAM. See Section 10.4.6.4, ÒLast Data Out to Precharge.
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Part III. The Hardware Interface 10.3.4 Local Bus SDRAM Mode Register (LSDMR) The LSDMR, shown in Figure 10-10, has the same Þelds as the PSDMR. Table 10-8 describes LSDMR Þelds. Table 10-8. LSDMR Field Descriptions Bits Name Description 0 PBI Page-based interleaving. Selects the address multiplexing method. PBI works in conjunction with ORx[SDA10]. See Section 10.4.5, ÒBank Interleaving.Ó 0 Bank-based interleaving 1 Page-based interleaving (normal operation) 1 RFEN 2Ð4 OP SDRAM operation.
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Part III. The Hardware Interface Table 10-8. LSDMR Field Descriptions (Continued) Bits Name Description SDRAM DeviceÐSpeciÞc Parameters: 14Ð16 RFRC Refresh recovery. DeÞnes the earliest timing for an activate command after a REFRESH command. Sets the refresh recovery interval in clock cycles. See Section 10.4.6.6, ÒRefresh Recovery Interval (RFRC),Ó for how to set this Þeld.
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Part III. The Hardware Interface Table 10-8. LSDMR Field Descriptions (Continued) Bits Name Description 28 EAMUX External address multiplexing enable/disable. 0 No external address multiplexing. Fastest timing. 1 The memory controller asserts SDAMUX for an extra cycle before issuing an ACTIVATE command to the SDRAM. This is useful when external address multiplexing can cause a delay on the address lines. Note that if EAMUX is set, ACTTORW should be at least 2.
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Part III. The Hardware Interface Table 10-9 describes MxMR bits. Table 10-9. Machine x Mode Registers (MxMR) Bits Name Description 0 BSEL Bus select. Assigns banks that select UPMx to the 60x or local bus. 0 Banks that select UPMx are assigned to the 60x bus. 1 Banks that select UPMx are assigned to the local bus.
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Part III. The Hardware Interface Table 10-9. Machine x Mode Registers (MxMR) (Continued) Bits Name Description 10Ð12 G0CLx General line 0 control. Determines which address line can be output to the GPL0 pin when the UPMx is selected to control the memory access. 000 A12 001 A11 010 A10 011 A9 100 A8 101 A7 110 A6 111 A5 13 GPL_x4DIS GPL_A4 output line disable. Determines if the UPWAIT/GTA/GPL_4 pin behaves as an output line controlled by the corresponding bits in the UPMx array (GPL4x).
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Part III. The Hardware Interface Bit 0 1 2 3 4 5 6 7 8 9 10 Field MD Reset 0000_0000_0000_0000 R/W R/W Addr 0x10188 Bit 16 17 18 19 20 21 22 23 24 25 26 Field MD Reset 0000_0000_0000_0000 R/W R/W Addr 0x1018A 11 12 13 14 15 27 28 29 30 31 Figure 10-12. Memory Data Register (MDR) Table 10-10 describes MDR Þelds. Table 10-10. MDR Field Descriptions Bits Name 0Ð31 MD Description Memory data.
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Part III. The Hardware Interface Table 10-11 describes MAR Þelds. Table 10-11. MAR Field Description Bits Name Description 0Ð31 A Memory address. The memory address register can be output to the address lines under control of the AMX bits in the UPM 10.3.8 60x Bus-Assigned UPM Refresh Timer (PURT) The 60x bus assigned UPM refresh timer register (PURT) is shown in Figure 10-14. Bit 0 1 2 3 4 Field PURT Reset 0000_0000 R/W R/W Addr 0x10198 5 6 7 Figure 10-14.
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Part III. The Hardware Interface Table 10-13 describes LURT Þelds. Table 10-13. Local Bus-Assigned UPM Refresh Timer (LURT) Bits Name 0Ð7 LURT Description Refresh timer period. Determines the timer period according to the following equation: LURT TimerPeriod = æ -----------------ö è F MPTCø This timer generates a refresh request for all valid banks that selected a UPM machine assigned to the local bus (MxMR[BSEL] =1) and is refresh-enabled (MxMR[RFEN] =1).
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Part III. The Hardware Interface 10.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT) The local bus-assigned SDRAM refresh timer register (LSRT) is shown in Figure 10-17. Bit 0 1 2 3 4 Field LSRT Reset 0000_0000 R/W R/W Addr 0x101A4 5 6 7 Figure 10-17. Local Bus-Assigned SDRAM Refresh Timer (LSRT) Table 10-15 describes LSRT Þelds. Table 10-15. LSRT Field Descriptions Bits Name 0Ð7 LSRT Description Refresh timer period.
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Part III. The Hardware Interface 10.3.13 60x Bus Error Status and Control Registers (TESCRx) These registers indicate the source of an error that caused TEA or MCP to be asserted on the 60x bus. See Section 4.3.2.10, Ò60x Bus Transfer Error Status and Control Register 1 (TESCR1),Ó and Section 4.3.2.11, Ò60x Bus Transfer Error Status and Control Register 2 (TESCR2).Ó 10.3.
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Part III. The Hardware Interface y MPC8260 DQM7 DQM6 DQM5 DQM4 DQM3 DQM2 A[17] DQM1 DQM0 PSDDQM[0Ð7] PSDA10 12-bit A[19Ð28] D[0Ð63] CS[0Ð7] PSDRAS PSDWE PSDCAS CS7 CAS CS RAS WE 2x1M x8 CKE SDRAM CLK DQM ADDR[0Ð11] DQ[0Ð7] CS7 x8 DATA[0Ð7] DATA[56Ð63] x8 CS0 CAS CS RAS WE 2x1M x8 CKE SDRAM CLK DQM ADDR[0Ð11] DQ[0Ð7] CAS CS RAS WE 2x1M x8 CKE SDRAM CLK DQM ADDR[0Ð11] DQ[0Ð7] x8 CS0 x8 DATA[0Ð7] CAS CS RAS WE 2x1M x8 CKE SDRAM CLK DQM ADDR[0Ð11] DQ[0Ð7] DATA[56Ð63] Figure 10-19.
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Part III. The Hardware Interface 10.4.1 Supported SDRAM ConÞgurations The MPC8260 memory controller supports any SDRAM conÞguration under the restrictions that all SDRAM devices that reside on the same bus (60x or local) should have the same port size and timing parameters. 10.4.2 SDRAM Power-On Initialization At system reset, initialization software must set up the programmable parameters in the memory controller banks registers (ORx, BRx, P/LSDMR).
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Part III. The Hardware Interface Table 10-18. SDRAM Interface Commands (Continued) Command PRECHARGE (SINGLE BANK/ ALL BANKS) Description Restores data from the sense ampliÞers to the appropriate row. Also initializes the sense ampliÞers to prepare for reading another row in the SDRAM array. A PRECHARGE command must be issued after a read or write if the row address changes on the next access. Note that the MPC8260 uses the SDA10 pin to distinguish the PRECHARGE-ALL-BANKS command.
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Part III. The Hardware Interface The following two methods are used for internal bank interleaving: ¥ Page-based interleavingÑPage-based interleaving yields the best performance and is the preferred interleaving method. This method uses low address bits as the Bank-Select for the SDRAM, thus allowing interleaving on every page boundary. It is activated by setting xSDMR[PBI]=1. See Ò0xSDRAM ConÞguration Example (Page-Based Interleaving)Ó.
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Part III. The Hardware Interface Table 10-20 shows SDRAM address multiplexing for A16ÐA31. Table 10-20.
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Part III. The Hardware Interface CLK ALE CS SDRAS SDCAS MA11 MA10 RAy MA[0Ð9] RAy WE DQM PRETOACT = 2 PRECHARGE ACTIVATE Command Bank A Command Bank A Figure 10-20. PRETOACT = 2 (2 Clock Cycles) 10.4.6.2 Activate to Read/Write Interval This parameter, controlled by P/LSDMR[ACTTORW], deÞnes the earliest timing for READ/WRITE command after an ACTIVATE command. CLK ALE CS SDRAS SDCAS MA[0Ð11] Cbz Rbz WE DQM DATA D0 D1 D2 D3 ACTTORW = 2 ACTIVATE WRITE Command Command Figure 10-21.
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Part III. The Hardware Interface 10.4.6.3 Column Address to First Data OutÑCAS Latency This parameter, controlled by P/LSDMR[CL], deÞnes the timing for Þrst read data after a column address is sampled by the SDRAM. Activate Read First data out CLK ALE CL = 2 CSn SDRAS SDCAS WE MA[0Ð11] Row Column DQMn D0 Data D1 D2 D3 Figure 10-22. CL = 2 (2 Clock Cycles) 10.4.6.
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Part III. The Hardware Interface 10.4.6.5 Last Data In to PrechargeÑWrite Recovery This parameter, controlled by P/LSDMR[WRC], deÞnes the earliest timing for PRECHARGE command after the last data was written to the SDRAM. Activate WRITE Last data in Deactivate CLK ALE WRC = 2 CS SDRAS SDCAS WE MA[0Ð11] Column Row DQM D0 Data D1 D2 D3 Figure 10-24. WRC = 2 (2 Clock Cycles) 10.4.6.
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Part III. The Hardware Interface should be set. Setting this bit causes the memory controller to add another cycle for each address phase. Note that EAMUX can also be set in any case of delays on the address lines, such as address buffers. CLK ALE SDAMUX CMD MA[0Ð11] NOP Act NOP Row Read NOP Column Address setup cycle Figure 10-26. EAMUX = 1 10.4.6.
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Part III. The Hardware Interface CLK ALE CS SDRAS SDCAS Row MA[0Ð11] Column WE DQM D0 Data Figure 10-28. SDRAM Single-Beat Read, Page Closed, CL = 3 CLK ALE CS SDRAS SDCAS Z MA[0Ð11] Column WE DQM D0 Data Figure 10-29. SDRAM Single-Beat Read, Page Hit, CL = 3 CLK ALE CS SDRAS SDCAS MA[0Ð11] Row Column WE DQM Data D0 D1 Figure 10-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3 MOTOROLA Chapter 10.
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Part III. The Hardware Interface Deactivate Activate CLK ALE CS SDRAS SDCAS MA[0Ð11] Z * BS A10 = 1 Row Col WE DQM D0 Data D1 D2 D4 * BSÑBank select according to SDRAM organization. A10 = 1 means not all banks will be precharged. CAS Latency = 3 Figure 10-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3 CLK ALE CS SDRAS SDCAS Column MA[0Ð11] WE DQM D0 Data Figure 10-32. SDRAM Single-Beat Write, Page Hit CLK ALE CS SDRAS SDCAS MA[0Ð11] Row Column WE DQM Data D0 D1 D2 Figure 10-33.
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Part III. The Hardware Interface CLK ALE CS SDRAS SDCAS Z MA[0Ð11] Column1 Column2 WE DQM D0 Data D1 D0 D1 DQM latency (affects negation only) = 2 Figure 10-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3 CLK ALE CS SDRAS SDCAS Column1 MA[0Ð11] Column2 WE DQM D0 Data D1 D2 D3 D0 D1 D2 D3 Figure 10-35. SDRAM Write-after-Write Pipelined, Page Hit CLK ALE CS SDRAS SDCAS MA[0Ð11] Column1 Z Column2 WE DQM Data D0 D1 D2 D3 D0 D1 D2 D3 Figure 10-36.
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Part III. The Hardware Interface 10.4.8 SDRAM Read/Write Transactions The SDRAM interface supports the following read/write transactions: ¥ Single-beat reads/writes up to double word size ¥ Bursts of two, three, or four double words SDRAM devices perform bursts for each transaction, the burst length depends on the port size. For 64-bit port size, it is a burst of 4. For 32-bit port size, it is a burst of 8. For reads that require less than the full burst length, extraneous data in the burst is ignored.
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Part III. The Hardware Interface Bit number 0 1 2 3 4 5 6 CL 7 8 0 9 10 11 lsb BL burst length: 4(010) for 16- and 64-bit port sizes 8(011) for 8- and 32-bit port sizes latency modeÑcan be 1(001), 2(010), or 3(011). Figure 10-38. Mode Data Bit Settings 10.4.10 SDRAM Refresh The memory controller supplies auto (CBR) refreshes to SDRAM according to the interval speciÞed in PSRT or LSRT. This represents the time period required between refreshes.
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Part III. The Hardware Interface CBR CBR CBR CBR Activate RFRC CLK ALE CS0 CS1 CS2 CS3 SDRAS SDCAS WE MA[0Ð11] DQM Z Data Figure 10-39. SDRAM Bank-Staggered CBR Refresh Timing 10.4.12 SDRAM ConÞguration Examples The following sections provide SDRAM conÞguration examples for page- and bank-based interleaving. 10.4.12.1 SDRAM ConÞguration Example (Page-Based Interleaving) Consider the following SDRAM organization: ¥ ¥ 64-bit port size organized as 8 x 8 x 64 Mbit.
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Part III. The Hardware Interface Now, from the SDRAM device point of view, during an ACTIVATE command, its address port should look like Table 10-22. Table 10-22. SDRAM Device Address Port during ACTIVATE Command ÒA[0Ð14]Ó A[15Ð16] A[17Ð28] A[29Ð31] Ñ Internal bank select (A[18Ð19]) Row (A[6Ð17]) n.c.
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Part III. The Hardware Interface 10.4.13 SDRAM ConÞguration Example (Bank-Based Interleaving) Consider the following SDRAM organization: ¥ 64-bit port size organized as 8 x 8 x 64 Mbit. ¥ Each device has four internal banks, 12 rows, and 9 columns For bank-based Interleaving, this means that the address bus should be partitioned as shown in Table 10-25. Table 10-25.
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Part III. The Hardware Interface Table 10-28.
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Part III. The Hardware Interface MPC8260 32-Bit Wide SRAM CSx CE WE[0–3] 128K WE[0–3] OE GPL_x1/OE Address A[15–29] Data D[0–31] Figure 10-40. GPCM-to-SRAM ConÞguration 10.5.1 Timing ConÞguration If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx. These attributes include the CSNT, ACS[0Ð1], SCY[0Ð3], TRLX, EHTR, and SETA Þelds. Table 10-30 shows signal behavior and system response. Table 10-30.
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Part III. The Hardware Interface 10.5.1.1 Chip-Select Assertion Timing From 0 to 30 wait states can be programmed for PSDVAL generation. Byte-write enable signals (WE) are available for each byte written to memory. Also, the output enable signal (OE) is provided to eliminate external glue logic. The memory banks selected to work with the GPCM have unique features. On system reset, a global (boot) chip-select is available that provides a boot ROM chip-select prior to the system being fully conÞgured.
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Part III. The Hardware Interface 10.5.1.2 Chip-Select and Write Enable Deassertion Timing Figure 10-43 shows a basic connection between the MPC8260 and a static memory device. Here, CS is connected directly to CE of the memory device. The WE signals are connected to the respective W signal in the memory device where each WE corresponds to a different data byte. MEMORY MPC8260 Address Address CS CE OE OE WE W Data Data Figure 10-43.
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Part III. The Hardware Interface Clock Address PSDVAL ACS = 11 ACS = 10 CS CSNT = 1 WE Data Figure 10-45. GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1, TRLX = 0) 10.5.1.3 Relaxed Timing ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. When TRLX = 1 and ACS ¹ 00, an additional cycle between the address and strobes is inserted by the MPC8260 memory controller. See Figure 10-46 and Figure 10-47.
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Part III. The Hardware Interface Clock Address PSDVAL ACS = 10 ACS = 11 CS R/W WE OE Data Figure 10-47. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1) When TRLX and CSNT are set in a write-memory access, the strobe lines, WE[0Ð7] are negated one clock earlier than in the normal case. If ACS ¹ 0, CS is also negated one clock earlier, as shown in Figure 10-48 and Figure 10-49.
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Part III. The Hardware Interface Clock Address PSDVAL CS R/W WE OE Data Figure 10-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1) 10.5.1.4 Output Enable (OE) Timing The timing of the OE is affected only by TRLX. It always asserts and negates on the rising edge of the external bus clock. OE always asserts on the rising clock edge after CS is asserted, and therefore its assertion can be delayed (along with the assertion of CS) by programming TRLX = 1.
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Part III. The Hardware Interface Table 10-31. TRLX and EHTR Combinations ORx[TRLX] ORx[EHTR] Number of Hold Time Clock Cycles 0 0 0 0 1 1 1 0 4 1 1 8 Figure 10-50 through Figure 10-53 show timing examples. Clock Address PSDVAL CSx CSy R/W OE Data Figure 10-50.
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Part III. The Hardware Interface Clock Address PSDVAL CSx CSy R/W OE Data Hold Time 1-cycle hold time allowed Figure 10-51. GPCM Read Followed by Read (ORx[29Ð30] = 01) Clock Address PSDVAL CSx CSy R/W OE Data Hold Time Long hold time allowed Figure 10-52. GPCM Read Followed by Write (ORx[29Ð30] = 01) MOTOROLA Chapter 10.
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Part III. The Hardware Interface Clock Address PSDVAL CSx CSy R/W OE Data Hold Time Figure 10-53. GPCM Read Followed by Read (ORx[29Ð30] = 10) 10.5.2 External Access Termination External access termination is supported by the GPCM using GTA, which is synchronized and sampled internally by the MPC8260. If, during a GPCM data phase (second cycle or later), the sampled signal is asserted, it is converted to PSDVAL, which terminates the current GPCM access. GTA should be asserted for one cycle.
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Part III. The Hardware Interface Clock Address R/W CS OE D GTA PSDVAL Figure 10-54. External Termination of GPCM Access 10.5.3 Boot Chip-Select Operation Boot chip-select operation allows address decoding for a boot ROM before system initialization. The CS0 signal is the boot chip-select output; its operation differs from the other external chip-select outputs on system reset.
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Part III. The Hardware Interface Table 10-32. Boot Bank Field Values after Reset Register Setting BR0 BA PS DECC WP MS[0Ð12] EMEMC V From hard reset conÞguration word. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó From hard reset conÞguration word. See Section 5.4.1, ÒHard Reset ConÞguration WordÓ 0 0 000 From hard reset conÞguration word. See Section 5.4.
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Part III. The Hardware Interface Additional control is available in 60x-compatible mode (60x bus only)ÑALEÑExternal address latch enable (not a UPM-controlled signal). Note that in this section, when a signal is named, the reference is to the 60x or local bus signal, according to the bank being accessed. The three user-programmable machines (UPMs) are ßexible interfaces that connect to a wide range of memory devices.
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Part III. The Hardware Interface Note that 60x bus accesses that hit a bank allocated to the local bus are transferred to the local bus. However, local bus accesses that hit a bank allocated to the 60x bus are ignored. 10.6.
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Part III. The Hardware Interface Table 10-34 show the start address of each pattern. Table 10-34. UPM Routines Start Addresses UPM Routine Routine Start Address Read single-beat (RSS) 0x00 Read burst (RBS) 0x08 Write single-beat (WSS) 0x18 Write burst (WBS) 0x20 Refresh timer (PTS) 0x30 Exception condition (EXS) 0x3C 10.6.1.1 Memory Access Requests When an internal device requests a new access to external memory, the address of transfer are compared to each valid bank deÞned in BRx.
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Part III. The Hardware Interface All local bus refreshes are done using the refresh pattern of UPMB. This means that if refresh is required on the local bus, UPMB must be assigned to the local bus and MBMR[RFEN] must be set. It also means that only one refresh routine should be programmed for the local bus, and be placed in UPMB, which serves as the local bus refresh executor. If refresh is not required on the local bus, UPMB can be assigned to any bus.
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Part III. The Hardware Interface 3. Program MPTPR and L/PSRT if refresh is required. 4. Program the machine mode register (MxMR). Patterns are written to the RAM array by setting MxMR[OP] = 01 and accessing the UPM with a single byte transaction. See Figure 10-11. 10.6.3 Clock Timing Fields in the RAM word specify the value of the various external signals at each clock edge. The signal timing generator causes external signals to behave according to the timing speciÞed in the current RAM word.
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Part III. The Hardware Interface CLKIN T1 T2 T3 T4 Figure 10-59. Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1) Clock Ratios The state of the external signals may change (if speciÞed in the RAM array) at any positive edge of T1, T2, T3, or T4 (there is a propagation delay speciÞed in the MPC8260 Hardware SpeciÞcations). Note however that only the CS signal corresponding to the currently accessed bank is manipulated by the UPM pattern when it runs.
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Part III. The Hardware Interface CLKIN T1 T2 T3 T4 CSx CST1 CST2 CST3 CST4 CST1 CST2 CST3 CST4 GPL1 G1T1 G1T3 G1T1 G1T3 GPL2 G2T1 G2T3 G2T1 G2T3 Word 1 Word 2 Figure 10-60. UPM Signals Timing Example 10.6.4 The RAM Array The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in Figure 10-61. The signals at the bottom of Figure 10-61 are UPM outputs. The selected CS is for the bank that matches the current address.
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Part III. The Hardware Interface 32 Bits RAM Array 64 T1, T2, T3, T4 External Signals Timing Generator (60x or Local) TSIZ, PS, A[30,31] Current Bank CS Line Selector CS[0Ð11] Byte Select Packaging BS GPL0 GPL1 GPL2 GPL3 GPL4 GPL5 Figure 10-61. RAM Array and Signal Generation 10.6.4.1 RAM Words The RAM word, shown in Figure 10-62, is a 32-bit microinstruction stored in one of 64 locations in the RAM array. It speciÞes timing for external signals controlled by the UPM.
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Part III. The Hardware Interface Table 10-35 describes RAM word Þelds. Table 10-35. RAM Word Bit Settings Bit Name Description 0 CST1 Chip-select timing 1. DeÞnes the state of CS during clock phase 1. 0 The value of the CS line at the rising edge of T1 will be 0 1 The value of the CS line at the rising edge of T1 will be 1 See Section 10.6.4.1.1, ÒChip-Select Signals (CxTx).Ó 1 CST2 Chip-select timing 2. DeÞnes the state of CS during clock phase 2.
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Part III. The Hardware Interface Table 10-35. RAM Word Bit Settings (Continued) Bit Name Description 12 G1T1 General-purpose line 1 timing 1. DeÞnes the state of GPL1 during phase 1Ð2. 0 The value of the GPL0 line at the rising edge of T1 will be 0 1 The value of the GPL0 line at the rising edge of T1 will be 1 See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó 13 G1T3 General-purpose line 1 timing 3. DeÞnes the state of GPL1 during phase 3Ð4.
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Part III. The Hardware Interface Table 10-35. RAM Word Bit Settings (Continued) Bit Name 20 G5T1 General-purpose line 5 timing 1. DeÞnes the state of GPL5 during phase 1Ð2. 0 The value of the GPL5 line at the rising edge of T1 will be 0 1 The value of the GPL5 line at the rising edge of T1 will be 1 21 G5T3 General-purpose line 5 timing 3. DeÞnes the state of GPL5 during phase 3Ð4.
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Part III. The Hardware Interface Table 10-35. RAM Word Bit Settings (Continued) Bit Name 29 UTA Description UPM transfer acknowledge. Indicates assertion of PSDVAL, sampled by the bus interface in the current cycle. 0 PSDVAL is not asserted in the current cycle. 1 PSDVAL is asserted in the current cycle. 30 TODT Turn-on disable timer. The disable timer associated with each UPM allows a minimum time to be guaranteed between two successive accesses to the same memory bank.
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Part III. The Hardware Interface Bank Selected CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 CS11 Switch UPMA/B/C MS[0–1] in BRx SDRAM MUX GPCM Figure 10-63. CS Signal Selection 10.6.4.1.2 Byte-Select Signals (BxTx) BRx[MS] of the accessed memory bank selects a UPM on the currently requested cycle. The selected UPM affects only the assertion and negation of the appropriate BS signal; its timing as speciÞed in the RAM word.
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Part III. The Hardware Interface 10.6.4.1.3 General-Purpose Signals (GxTx, GOx) The general-purpose signals (GPL[1Ð5]) each have two bits in the RAM word that deÞne the logical value of the signal to be changed at the rising edge of T1 and/or at the rising edge of T3. GPL0 offer enhancements beyond the other GPLx lines. GPL0 can be controlled by an address line speciÞed in MxMR[G0CLx]. To use this feature, set G0H and G0L in the RAM word.
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Part III. The Hardware Interface Figure 10-79 shows an example of REDO use. 10.6.4.2 Address Multiplexing The address lines can be controlled by the pattern the user provides in the UPM. The address multiplex bits can choose between outputting an address requested by the internal master as is and outputting it according to the multiplexing speciÞed by the MxMR[AMx]. The last option is to output the contents of the MAR on the address pins.
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Part III. The Hardware Interface M U L T I P L E X E R To internal data bus Data Bus CLKIN UPMx selected to handle the transfer AND (GPL4xDIS = 1) and RD/WR and DLT2x Figure 10-65. UPM Read Access Data Sampling 10.6.4.4 Signals Negation When the LAST bit is read in a RAM word, the current UPM pattern terminates. On the next cycle all the UPM signals are negated unconditionally (driven to logic Ô1Õ). This negation will not occur only if there is a back-to-back UPM request pending.
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Part III. The Hardware Interface CLKIN T1 T2 T3 T4 CSx GPL1 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 A c12 B c13 c14 C D PSDVAL WAEN UPWAIT Word n Word n+1 Word n+2 Wait Wait Word n+3 Figure 10-66. Wait Mechanism Timing for Internal and External Synchronous Masters 10.6.4.6 Extended Hold Time on Read Accesses Slow memory devices that take a long time to turn off their data bus drivers on read accesses should chose some combination of ORx[EHTR].
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Part III. The Hardware Interface This means that the address bus should be partitioned as shown in Table 10-38. Table 10-38. 60x Address Bus Partition A[0Ð7] A[8Ð19] A[20Ð28] A[29Ð31] msb of start address Row Column lsb From the device perspective, during RAS assertion, its address port should look like Table 10-39: Table 10-39. DRAM Device Address Port during an ACTIVATE command ÒA[0Ð16]Ó A[17Ð28] A[29Ð31] Ñ Row (A[8Ð19]) n.c.
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Part III. The Hardware Interface ¥ Timing of GPL[0Ð5]ÑIn the MPC8xxÕs UPM, the GPL lines could change on the positive edge of T2 or T3. In the MPC8260 these signals can change in the positive edge of T1 or T3 to allow connection to high-speed synchronous devices such as burst SRAM. ¥ UPM controlled signals negated at end of an accessÑIn the MPC8xxÕs UPM, if the user did not negate the UPM signals at end of an access, those signals kept their previous value.
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Part III. The Hardware Interface MPC8260 BS[0–7] 1M x 16 RAS CS1 BCTL0 CAS[0–1] CAS[0–1] W W A[0–9] A[19–28] 1M x 16 RAS A[0–9] D[0–15] D[0–15 16 16 16 16 D[0–63] RAS D[0–15] RAS D[0–15] CAS[0–1] CAS[0–1] W W A[0–9] A[0–9] 1M x 16 1M x 16 Figure 10-67. DRAM Interface Connection to the 60x Bus (64-Bit Port Size) After timings are created, programming the UPM continues with translating these timings into tables representing the RAM array contents for each possible cycle.
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Part III. The Hardware Interface MxMR[OP] = 11. Figure 10-56 shows the Þrst locations addressed by the UPM, according to the different services required by the DRAM.
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Part III. The Hardware Interface CLKIN MA RD/WR D PSDVAL CS1 (RAS) BS (CAS) cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 1 1 1 1 1 1 1 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 Bit 24 Bit 25 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 0 0 0 0 0 0 1 1 EXS Figure 10-74.
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Part III. The Hardware Interface ¥ If GPL_4 is not used as an output, the performance for a page read access can be improved by setting MxMR[GPL_x4DIS]. The following example shows how the burst read access to FPM DRAM (no LOOP) can be modiÞed using this feature. In this case the conÞguration registers are deÞned in the following way. Table 10-42.
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Part III. The Hardware Interface 10.7.0.1 EDO Interface Example Figure 10-76 shows a memory connection to extended data-out type devices. For this connection, GPL1 is connected to the memory deviceÕs OE pins. MPC8260 BS[0Ð7] CS1 R/W RAS RAS CASl/h CASl/h 1M x 16 OE MCM516165 1M x 16 OE MCM516165 W W A[0Ð9] A[19Ð28] A[0Ð9] D[0Ð15] D[0Ð15] 16 16 16 16 D[0Ð63] RAS RAS D[0Ð15] CASl/h GPL1 OE W D[0Ð15] CASl/h 1M x 16 MCM516165 OE W A[0Ð9] 1M x 16 MCM516165 A[0Ð9] Figure 10-76.
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Part III. The Hardware Interface 10.8 Handling Devices with Slow or Variable Access Times The memory controller provides two ways to interface with slave devices that are very slow (access time is greater than the maximum allowed by the user programming model) or cannot guarantee a predeÞned access time (for example some FIFO, hierarchical bus interface, or dual-port memory devices). These mechanisms are as follows: ¥ The wait mechanismÑUsed only in accesses controlled by the UPM.
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Part III. The Hardware Interface 10.9 External Master Support (60x-Compatible Mode) The memory controller supports internal and external bus masters. Accesses from the core or the CPM are considered internal; accesses from an external bus master are external. External bus master support is available only if the MPC8260 is placed in 60x-compatible mode. This is done by setting the BCR[EBM], described in Section 4.3.2.1, ÒBus ConÞguration Register (BCR).
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Part III. The Hardware Interface ¥ PSDVAL as a termination to a partial transaction (such as port-size beat access). ¥ Internal SDRAM bank selects (BNKSEL[0Ð2]) to allow SDRAM bank interleaving, as described in Section 10.9.4, ÒUsing BNKSEL SIgnals in Single-MPC8260 Bus Mode.Ó 10.9.
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Part III. The Hardware Interface The 60x bus is pipelined. The ALE pins control the external latch that latches the address from the 60x bus and keeps the address stable for the memory access. The memory controller asserts ALE only on the start of new memory controller access. Figure 10-84 shows the pipelined bus operation in 60x-compatible mode. CLKIN ADDR + ATTR TS AACK DBG PSDVAL TA D ALE MA CS WE OE BADDR[27–28] 00 01 02 03 Figure 10-84.
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Part III. The Hardware Interface Figure 10-85 shows the 1-cycle delay for external master access. For systems that use the 60x bus with low frequency (33 MHz), the 1-cycle delay for external masters can be eliminated by setting BCR[EXDD]. CLKIN A[0–28] A[27–31] TT TBST TSIZ TS TA CS WE OE Data Address Match and Compare Memory Device Access Figure 10-85. External Master Access (GPCM) 10.9.6.
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Part III. The Hardware Interface BNKSEL,SDWE,SDRAS,SDCAS CS1 SDRAM 64-Bit Port Size DQM[0–7] SDAMUX Multiplexer MA ALE MPC8260 Latch External Master A[0–31] D[0–63] TT[0–4] TS TBST TA TSIZ[1–3] TSIZ[0] PSDVAL TSIZ[0–2] (pull down) (pull up) Arbitration signals Figure 10-86. External Master Configuration with SDRAM Device MOTOROLA Chapter 10.
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Chapter 11 Secondary (L2) Cache Support 110 110 The MPC8260 has features to support an externally controlled secondary (L2) cache such as the Motorola MPC2605 integrated secondary cache for PowerPC microprocessors. This chapter describes the MPC8260Õs L2 cache interfaceÑconÞgurations, operation, programmable parameters, system requirements, and timing. 11.1 L2 Cache ConÞgurations The MPC8260 supports three L2 cache conÞgurationsÑcopy-back mode, write-through mode, and ECC/parity mode.
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Part III. The Hardware Interface (pull up) MPC8260 MPC2605 BR L2BR BG L2BG DBG L2DBG CPU_BR, CPU_BG, CPU_DBG CPU_BR,CPU_BG,CPU_DBG TS, TT[0Ð4], TBST, TSIZ[1Ð3] TS, TT[0Ð4], TBST, TSIZ[0Ð2]] CI, WT, GBL, TA, DBB, TEA CI, WT, GBL, TA, DBB, TEA AACK, ARTRY TSIZ[0] AACK, ARTRY (pull down) L2_HIT L2_CLAIM A[0Ð31] A[0Ð31] D[0Ð63] D[0Ð63] Latch Memory Controller MUX SDRAM Main Memory I/O Devices Figure 11-1. L2 Cache in Copy-Back Mode 11.1.
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Part III. The Hardware Interface are serviced just as they are for copy-back mode. Write-through mode sacriÞces some of the write performance of copy-back mode, but guarantees L2 cache coherency with main memory. Since write-through mode keeps memory coherent with the contents of the L2 cache, there is never any need to perform an L2 copy-back.
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Part III. The Hardware Interface MPC8260 MPC2605 (pull up) (pull up) BR L2BR BG L2BG DBG L2DBG CPU_BR, CPU_BG, CPU_DBG CPU_BR,CPU_BG,CPU_DBG TS, TT[0:4], TBST, TSIZ[1Ð3] TS, TT[0Ð4], TBST, TSIZ[0Ð2] CI, GBL, TA, DBB, TEA CI, GBL, TA, DBB, TEA AACK, ARTRY TSIZ[0] AACK, ARTRY (pull down) (pull down) WT L2_HIT L2_CLAIM A[0Ð31] A[0Ð31] D[0Ð63] D[0Ð63] Latch Memory Controller MUX SDRAM Main Memory I/O Devices Figure 11-2. External L2 Cache in Write-Through Mode 11.1.
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Part III. The Hardware Interface In ECC/parity mode the L2 cache can support memory regions with ECC/Parity under the following restrictions: ¥ All non-write-protected (BRx[WP] = 0) memory banks marked caching-allowed must use either ECC (BRx[DECC] = 0b11) or read-modify-write parity (BRx[DECC] = 0b10). See Section 10.3.1, ÒBase Registers (BRx),Ó for more information about the MPC8260 base register parameters. ¥ Only MPC8260-type masters are supported in systems that use ECC/parity L2 cache mode.
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Part III. The Hardware Interface MPC2605 MPC8260 (pull up) (pull up) BR L2BR BG L2BG DBG L2DBG CPU_BR, CPU_BG, CPU_DBG CPU_BR,CPU_BG,CPU_DBG TS, TT[0Ð4], TBST TS, TT[0Ð4], TBST (pull downs) CI, GBL, TA, DBB, TEA TSIZ[0Ð2] CI, GBL, TA, DBB, TEA AACK, ARTRY AACK, ARTRY TSIZE[0] WT (pull down) (pull down) L2_HIT L2_CLAIM (pull downs) A[0Ð31] A[29Ð31] A[0Ð28] D[0Ð63], DP[0Ð7] D[0Ð63],DP[0Ð7] Latch Memory Controller MUX SDRAM Main Memory I/O Devices Figure 11-3.
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Part III. The Hardware Interface 11.2 L2 Cache Interface Parameters The L2 cache interface parameters in the bus conÞguration register (BCR) control the conÞguration and operation of the MPC8260Õs L2 interface. The parameters should be conÞgured as follows: ¥ BCR[EBM] = 1ÑMPC8260 in 60x-compatible mode. ¥ BCR[L2C] = 1ÑL2 cache is present. ¥ BCR[L2D] = 0ÑL2 response time. In this case, the L2 will claim a bus transaction one clock cycle after TS assertion.
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Part III. The Hardware Interface bus to the external L2 cache by asserting BG and DBG, respectively. If the external L2 cache asserts ARTRY, it should not assert L2_HIT. For more information about the timing and behavior of the MPC2605 integrated L2 cache, refer to the MPC2605 data sheet. 11.5 Timing Example Figure 11-4 shows a read access performed by the MPC8260 with an externally controlled L2 cache.
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Part III. The Hardware Interface CLK BR BG ABB Addr A1 & TBST A0 & TBST& CI TS Memc controls active disabled L2 AACK MPC8260 DBG DBB DATA D00 D01 D02 D03 TA L2D = 0 0 0 L2 HIT Figure 11-4. Read Access with L2 Cache MOTOROLA Chapter 11.
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Chapter 12 IEEE 1149.1 Test Access Port 120 120 The MPC8260 provides a dedicated user-accessible test access port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG).
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Part III. The Hardware Interface Boundary Scan Register M U X TDI Bypass Instruction Apply & Decode Register 3 2 1 0 4ÐBit Instruction Register M U X TDO TRST TMS TAP Controller TCK Figure 12-1. Test Logic Block Diagram The TAP consists of the signals in Table 12-1. Table 12-1. TAP Signals Signal Description TCK A test clock input to synchronize the test logic.
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Part III. The Hardware Interface Test Logic Reset 1 0 RunÑTest/Idle 1 SelectÑDR_SCAN 0 1 SelectÑIR_SCAN 0 0 CaptureÑDR CaptureÑIR 0 0 ShiftÑDR ShiftÑIR 1 1 Exit1ÑDR Exit1ÑIR 0 0 PauseÑDR PauseÑIR 1 1 Exit2ÑDR Exit2ÑIR 1 1 UpdateÑDR 1 0 1 UpdateÑIR 1 0 Figure 12-2. TAP Controller State Machine 12.
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Part III. The Hardware Interface Shift DR 1 Ñ EXTEST | Clamp 0 Ñ Otherwise To Next Cell G1 Data from System Logic 1 To Output Buffer MUX 1 G1 1 D C MUX 1 From Last Cell Clock DR D C Update DR Figure 12-3. Output Pin Cell (O.Pin) To Next Cell Data to System Logic Input Pin G1 D C 1 MUX 1 Shift DR Clock DR From Last Cell Figure 12-4. Observe-Only Input Pin Cell (I.
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Part III. The Hardware Interface 1 Ñ EXTEST | Clamp 0 Ñ Otherwise Shift DR To Next Cell G1 Output Control from System Logic 1 To Output Buffer MUX 1 G1 1 D C MUX 1 From Last Cell Clock DR D C Update DR Figure 12-5. Output Control Cell (IO.CTL) From Last Cell Output Enable from System Logic I/O.CTL Output Data O.PIN Input Data I.OBS EN I/O Pin To Next Pin Pair To Next Cell Figure 12-6.
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Part III. The Hardware Interface type. The third column lists the pin name for all pin-related cells and deÞnes the name of the bidirectional control register bits. The fourth column lists the pin type, and the last column indicates the associated boundary scan register control bit for the bidirectional output pins. Table 12-2. Boundary Scan Bit Definition 12-6 Bit Cell Type Pin/Cell Name Pin Type 0 i.obs pa[4] io Output Control Cell Ñ 1 o.pin pa[4] io g2.ctl 2 IO.ctl g2.ctl Ñ Ñ 3 i.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 35 IO.ctl g277.ctl Ñ Ñ 36 i.obs pb[10] io Ñ 37 o.pin pb[10] io g276.ctl 38 IO.ctl g276.ctl Ñ Ñ 39 i.obs pa[8] io Ñ 40 o.pin pa[8] io g275.ctl 41 IO.ctl g275.ctl Ñ Ñ 42 i.obs pd[12] io Ñ 43 o.pin pd[12] io g274.ctl 44 IO.ctl g274.ctl Ñ Ñ 45 i.obs pc[7] io Ñ 46 o.pin pc[7] io g273.ctl 47 IO.ctl g273.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) 12-8 Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 74 IO.ctl g263.ctl Ñ Ñ 75 i.obs pb[13] io Ñ 76 o.pin pb[13] io g262.ctl 77 IO.ctl g262.ctl Ñ Ñ 78 i.obs pa[12] io Ñ 79 o.pin pa[12] io g261.ctl 80 IO.ctl g261.ctl Ñ Ñ 81 i.obs pd[14] io Ñ 82 o.pin pd[14] io g260.ctl 83 IO.ctl g260.ctl Ñ Ñ 84 i.obs pc[10] io Ñ 85 o.pin pc[10] io g259.ctl 86 IO.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 113 IO.ctl g250.ctl Ñ Ñ 114 i.obs pc[13] io Ñ 115 o.pin pc[13] io g249.ctl 116 IO.ctl g249.ctl Ñ Ñ 117 i.obs pb[16] io Ñ 118 o.pin pb[16] io g248.ctl 119 IO.ctl g248.ctl Ñ Ñ 120 i.obs pa[16] io Ñ 121 o.pin pa[16] io g247.ctl 122 IO.ctl g247.ctl Ñ Ñ 123 i.obs pd[17] io Ñ 124 o.pin pd[17] io g246.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) 12-10 Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 152 IO.ctl g237.ctl Ñ Ñ 153 i.obs pb[23] io Ñ 154 o.pin pb[23] io g236.ctl 155 IO.ctl g236.ctl Ñ Ñ 156 i.obs pa[19] io Ñ 157 o.pin pa[19] io g235.ctl 158 IO.ctl g235.ctl Ñ Ñ 159 i.obs pc[17] io Ñ 160 o.pin pc[17] io g234.ctl 161 IO.ctl g234.ctl Ñ Ñ 162 i.obs pd[20] io Ñ 163 o.pin pd[20] io g233.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 191 IO.ctl g224.ctl Ñ Ñ 192 i.obs pb[20] io Ñ 193 o.pin pb[20] io g223.ctl 194 IO.ctl g223.ctl Ñ Ñ 195 i.obs pa[22] io Ñ 196 o.pin pa[22] io g222.ctl 197 IO.ctl g222.ctl Ñ Ñ 198 i.obs pd[23] io Ñ 199 o.pin pd[23] io g221.ctl 200 IO.ctl g221.ctl Ñ Ñ 201 i.obs pc[21] io Ñ 202 o.pin pc[21] io g220.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) 12-12 Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 230 IO.ctl g212.ctl Ñ Ñ 231 i.obs pc[24] io Ñ 232 o.pin pc[24] io g211.ctl 233 IO.ctl g211.ctl Ñ Ñ 234 i.obs pb[25] io Ñ 235 o.pin pb[25] io g210.ctl 236 IO.ctl g210.ctl Ñ Ñ 237 i.obs pa[25] io Ñ 238 o.pin pa[25] io g209.ctl 239 IO.ctl g209.ctl Ñ Ñ 240 i.obs pd[26] io Ñ 241 o.pin pd[26] io g208.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 269 o.pin 270 IO.ctl sreset_b io g170.ctl g170.ctl Ñ 271 Ñ i.obs clkin i Ñ 272 i.obs pc[27] io Ñ 273 o.pin pc[27] io g166.ctl 274 IO.ctl g166.ctl Ñ Ñ 275 i.obs pd[28] io Ñ 276 o.pin pd[28] io g165.ctl 277 IO.ctl g165.ctl Ñ Ñ 278 i.obs pc[28] io Ñ 279 o.pin pc[28] io g164.ctl 280 IO.ctl g164.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit 12-14 Cell Type Pin/Cell Name Pin Type Output Control Cell 308 i.obs pa[30] io Ñ 309 o.pin pa[30] io g154.ctl 310 IO.ctl g154.ctl Ñ Ñ 311 i.obs pd[31] io Ñ 312 o.pin pd[31] io g153.ctl 313 IO.ctl g153.ctl Ñ Ñ 314 i.obs pc[31] io Ñ 315 o.pin pc[31] io g152.ctl 316 IO.ctl g152.ctl Ñ Ñ 317 i.obs pb[31] io Ñ 318 o.pin pb[31] io g151.ctl 319 IO.ctl g151.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 347 348 IO.ctl g89.ctl Ñ Ñ i.obs psdval_b io Ñ 349 o.pin psdval_b io g130.ctl 350 IO.ctl g130.ctl Ñ Ñ 351 i.obs dbb_b_irq3_b io Ñ 352 o.pin dbb_b_irq3_b io g129.ctl 353 IO.ctl g129.ctl Ñ Ñ 354 i.obs dbg_b io Ñ 355 o.pin dbg_b io g128.ctl 356 IO.ctl g128.ctl Ñ Ñ 357 i.obs spare4 io Ñ 358 o.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) 12-16 Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 386 IO.ctl g111.ctl Ñ Ñ 387 i.obs a[26] io Ñ 388 o.pin a[26] io g111.ctl 389 i.obs a[25] io Ñ 390 o.pin a[25] io g111.ctl 391 i.obs a[24] io Ñ 392 o.pin a[24] io g111.ctl 393 i.obs a[23] io Ñ 394 o.pin a[23] io g110.ctl 395 i.obs a[22] io Ñ 396 o.pin a[22] io g110.ctl 397 i.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 425 i.obs a[8] io Ñ 426 o.pin a[8] io g109.ctl 427 i.obs a[7] io Ñ 428 o.pin a[7] io g108.ctl 429 i.obs a[6] io Ñ 430 o.pin a[6] io g108.ctl 431 i.obs a[5] io Ñ 432 o.pin a[5] io g108.ctl 433 i.obs a[4] io Ñ 434 o.pin a[4] io g108.ctl 435 i.obs a[3] io Ñ 436 o.pin a[3] io g108.ctl 437 IO.ctl g108.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit 12-18 Cell Type Pin/Cell Name Pin Type Output Control Cell 464 i.obs bg_b io Ñ 465 o.pin bg_b io g115.ctl 466 IO.ctl g115.ctl Ñ Ñ 467 i.obs irq7_b_int_out_b_ape_b io Ñ 468 o.pin irq7_b_int_out_b_ape_b io g114.ctl 469 IO.ctl g114.ctl Ñ Ñ 470 i.obs ts_b io Ñ 471 o.pin ts_b io g113.ctl 472 i.obs tsize[3] io Ñ 473 o.pin tsize[3] io g113.ctl 474 i.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 503 i.obs d[54] io Ñ 504 o.pin d[54] io g106.ctl 505 i.obs d[46] io Ñ 506 o.pin d[46] io g106.ctl 507 i.obs d[38] io Ñ 508 o.pin d[38] io g106.ctl 509 i.obs d[30] io Ñ 510 o.pin d[30] io g106.ctl 511 IO.ctl g106.ctl Ñ Ñ 512 i.obs d[22] io Ñ 513 o.pin d[22] io g106.ctl 514 i.obs d[14] io Ñ 515 o.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) 12-20 Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 542 o.pin d[36] io g104.ctl 543 i.obs d[28] io Ñ 544 o.pin d[28] io g104.ctl 545 IO.ctl g104.ctl Ñ Ñ 546 i.obs d[20] io Ñ 547 o.pin d[20] io g104.ctl 548 i.obs d[12] io Ñ 549 o.pin d[12] io g104.ctl 550 i.obs d[4] io Ñ 551 o.pin d[4] io g104.ctl 552 i.obs d[59] io Ñ 553 o.pin d[59] io g103.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 581 o.pin d[18] io g102.ctl 582 i.obs d[10] io Ñ 583 o.pin d[10] io g102.ctl 584 i.obs d[2] io Ñ 585 o.pin d[2] io g102.ctl 586 i.obs d[57] io Ñ 587 o.pin d[57] io g101.ctl 588 i.obs d[49] io Ñ 589 o.pin d[49] io g101.ctl 590 i.obs d[41] io Ñ 591 o.pin d[41] io g101.ctl 592 i.obs d[33] io Ñ 593 o.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit 12-22 Cell Type Pin/Cell Name Pin Type Output Control Cell 620 i.obs dp7_cse1_irq7_b io Ñ 621 o.pin dp7_cse1_irq7_b io g99.ctl 622 IO.ctl g99.ctl Ñ Ñ 623 i.obs dp6_cse0_irq6_b io Ñ 624 o.pin dp6_cse0_irq6_b io g98.ctl 625 IO.ctl g98.ctl Ñ Ñ 626 i.obs dp5_tben_irq5_b io Ñ 627 o.pin dp5_tben_irq5_b io g97.ctl 628 IO.ctl g97.ctl Ñ Ñ 629 i.obs dp4_irq4_b io Ñ 630 o.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 659 o.pin we_dqm_bs_b[3] o Ñ 660 o.pin we_dqm_bs_b[2] o Ñ 661 o.pin we_dqm_bs_b[1] o Ñ 662 o.pin bctl0_b o Ñ 663 o.pin we_dqm_bs_b[0] o Ñ 664 o.pin lsdamux_gpl5 o Ñ 665 i.obs lgta_b_upwait_gpl4_pbs io Ñ 666 o.pin lgta_b_upwait_gpl4_pbs io g66.ctl 667 IO.ctl g66.ctl Ñ Ñ 668 o.pin lsdcas_b_gpl3 o Ñ 669 o.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit 12-24 Cell Type Pin/Cell Name Pin Type 698 i.obs lcl_d_ad[4] io Ñ 699 o.pin lcl_d_ad[4] io g40.ctl 700 i.obs lcl_d_ad[3] io Ñ 701 o.pin lcl_d_ad[3] io g40.ctl 702 i.obs lcl_d_ad[2] io Ñ 703 o.pin lcl_d_ad[2] io g40.ctl 704 i.obs lcl_d_ad[1] io Ñ 705 o.pin lcl_d_ad[1] io g40.ctl 706 i.obs lcl_d_ad[6] io Ñ 707 o.pin lcl_d_ad[6] io g40.ctl 708 IO.ctl g40.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 737 738 IO.ctl g20.ctl Ñ Ñ i.obs lcl_dp_c_be[1] io Ñ 739 o.pin lcl_dp_c_be[1] io g44.ctl 740 IO.ctl g44.ctl Ñ Ñ 741 i.obs lcl_d_ad[15] io Ñ 742 o.pin lcl_d_ad[15] io g47.ctl 743 IO.ctl g47.ctl Ñ Ñ 744 i.obs l_a30_lock_b io Ñ 745 o.pin l_a30_lock_b io g36.ctl 746 IO.ctl g36.ctl Ñ Ñ 747 i.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) 12-26 Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 776 o.pin lcl_d_ad[18] io g42.ctl 777 i.obs lcl_d_ad[19] io Ñ 778 o.pin lcl_d_ad[19] io g42.ctl 779 IO.ctl g42.ctl Ñ Ñ 780 i.obs lcl_d_ad[20] io Ñ 781 o.pin lcl_d_ad[20] io g42.ctl 782 i.obs lcl_d_ad[21] io Ñ 783 o.pin lcl_d_ad[21] io g42.ctl 784 i.obs lcl_d_ad[22] io Ñ 785 o.pin lcl_d_ad[22] io g42.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 815 o.pin 816 IO.ctl l_a25_gnt0_b io g31.ctl g31.ctl Ñ 817 Ñ i.obs l_a27_pclk io Ñ 818 o.pin l_a27_pclk io g33.ctl 819 IO.ctl g33.ctl Ñ Ñ 820 i.obs l_a28_rst_b io Ñ 821 o.pin l_a28_rst_b io g34.ctl 822 IO.ctl g34.ctl Ñ Ñ 823 i.obs l_a29_inta_b io Ñ 824 o.pin l_a29_inta_b io g35.ctl 825 IO.ctl g35.
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Part III. The Hardware Interface Table 12-2. Boundary Scan Bit Definition (Continued) Bit Cell Type Pin/Cell Name Pin Type Output Control Cell 854 o.pin pb[5] io g11.ctl 855 IO.ctl g11.ctl Ñ Ñ 856 i.obs pa[2] io Ñ 857 o.pin pa[2] io g10.ctl 858 IO.ctl g10.ctl Ñ Ñ 859 i.obs pd[6] io Ñ 860 o.pin pd[6] io g9.ctl 861 IO.ctl g9.ctl Ñ Ñ 862 i.obs pc[3] io Ñ 863 o.pin pc[3] io g8.ctl 864 IO.ctl g8.ctl Ñ Ñ 865 i.obs pb[6] io Ñ 866 o.
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Part III. The Hardware Interface Table 12-3. Instruction Decoding Code Instruction Description B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 EXTEST External test. Selects the 475-bit boundary scan register. EXTEST also asserts an internal reset for the MPC8260Õs system logic to force a known beginning internal state while performing external boundary scan operations.
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Part III. The Hardware Interface The parallel output of the instruction register is set to all ones in the test-logic-reset controller state. Notice that this preset state is equivalent to the BYPASS instruction. During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with the CLAMP command code. 12.
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Part IV Communications Processor Module Intended Audience Part IV is intended for system designers who need to implement various communications protocols on the MPC8260. It assumes a basic understanding of the PowerPC exception model, the MPC8260 interrupt structure, as well as a working knowledge of the communications protocols to be used. A complete discussion of these protocols is beyond the scope of this book.
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Part IV. Communications Processor Module ¥ Chapter 19, ÒSerial Communications Controllers (SCCs),Ó describes the four serial communications controllers (SCC), which can be conÞgured independently to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks.
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Part IV. Communications Processor Module ¥ Chapter 33, ÒSerial Peripheral Interface (SPI),Ó describes the serial peripheral interface, which allows the MPC8260 to exchange data between other MPC8260 chips, the MC68360, the MC68302, the M68HC11, and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.
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Part IV. Communications Processor Module ¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide (Motorola order #: MPCPRG/D) is a concise reference that includes the register summary, memory control model, exception vectors, and the PowerPC instruction set. For a current list of PowerPC documentation, refer to the world-wide web at http://www.mot.com/PowerPC.
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Part IV. Communications Processor Module Table vii. Acronyms and Abbreviated Terms Term Meaning AAL ATM adaptation layer ABR Availabe bit rate ACR Allowed cell rate ALU Arithmetic logic unit APC ATM pace control ATM Asynchronous transfer mode BD Buffer descriptor BIST Built-in self test BT Burst tolerance CBR Constant bit rate CEPT Conference des administrations Europeanes des Postes et Telecommunications (European Conference of Postal and Telecommunications Administrations).
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Part IV. Communications Processor Module Table vii.
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Part IV. Communications Processor Module Table vii.
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Part IV.
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Chapter 13 Communications Processor Module Overview 130 130 The MPC8260Õs communications processor module (CPM) is a superset of the MPC860 PowerQUICC CPM, with enhancements in performance and the addition of hardware and microcode routines for supporting high bit-rate protocols like ATM and Fast Ethernet. The support for multiple HDLC channels is enhanced to support up to 256 HDLC channels. 13.
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Part IV. Communications Processor Module ¥ Four full-duplex serial communications controllers (SCCs) support the following protocols: Ñ IEEE802.
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Part IV. Communications Processor Module Local Bus 60x Bus To SIU Interrupt Controller Bus Interface SDMA Internal Bus 4 Timers Communications Processor Dual-Port RAM Parallel I/O Ports ROM Baud Rate Generators Peripheral Bus 2 MCCs 3 FCCs 4 SCCs 2 SMCs SPI I2C Serial Interface (SI) and Time-Slot Assigner (TSA) Figure 13-1. MPC8260 CPM Block Diagram 13.2 MPC8260 Serial ConÞgurations The MPC8260 offers a ßexible set of communications capabilities.
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Part IV. Communications Processor Module 13.3 Communications Processor (CP) The communications processor (CP), also called the RISC microcontroller, is a 32-bit controller for the CPM that resides on a separate bus from the core and, therefore, can perform tasks independent of the PowerPC core. The CP handles lower-layer communications tasks and DMA control, freeing the core to handle higher-layer activities.
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Part IV. Communications Processor Module Figure 13-2 shows the CP block diagram.
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Part IV. Communications Processor Module 13.3.3 PowerPC Core Interface The CP communicates with the PowerPC core in several ways: ¥ Many parameters are exchanged through the dual-port RAM. ¥ ¥ The CP can execute special commands issued by the core. These commands should only be issued in special situations like exceptions or error recovery. The CP generates interrupts through the SIU interrupt controller. ¥ The PowerPC core can read the CPM status/event registers at any time. 13.3.
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Part IV. Communications Processor Module Table 13-2. Peripheral Prioritization (Continued) Priority Request 19 SCC2 transmit 20 SCC3 receive 21 SCC3 transmit 22 SCC4 receive 23 SCC4 transmit 24 IDMA[1Ð4] emulation (option 2)1 25 SMC1 receive 26 SMC1 transmit 27 SMC2 receive 28 SMC2 transmit 29 SPI receive 30 SPI transmit 31 I2C receive 32 I2C transmit 33 RISC timer table 34 IDMA[1Ð4] emulation (option 3)1 1The priority of each IDMA channel is programmed independently.
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Part IV. Communications Processor Module Bits 0 1 Field TIME Ñ 2 3 4 5 6 7 TIMEP 8 9 DR1M DR2M Reset 0000_0000_0000_0000 R/W R/W Addr Bits 10 11 12 13 14 DR1QP EIE SCD 26 28 29 15 DR2QP 0x119C4 16 Field 17 18 ERAM 19 Ñ 20 21 22 23 24 25 EDM1 EDM2 EDM3 EDM4 DR3M DR4M Reset 0000_0000_0000_0000 R/W R/W Addr 0X119C6 27 DR3QP 30 DEM12 DEM34 31 DR4QP Figure 13-3. RISC Controller Configuration Register (RCCR) RCCR bit Þelds are described in Table 13-3.
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Part IV. Communications Processor Module Table 13-3. RISC Controller Configuration Register Field Descriptions (Continued) Bits Name Description 16Ð18 ERAM Enable RAM microcode. ConÞgure as instructed in the download process of a Motorola-supplied RAM microcode package. 000 Disable microcode program execution from the dual-port RAM. 001 Microcode uses the Þrst 2 Kbytes of the dual-port RAM. 010 Microcode uses the Þrst 4 Kbytes of the dual-port RAM.
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Part IV. Communications Processor Module Table 13-4 describes RTSCR Þelds. Table 13-4. RTSCR Field Descriptions Bits Name Description 0Ð4 Ñ Reserved 5 RTE Time stamp enable. 0 Disable time-stamp timer. 1 Enable time-stamp timer. 6Ð15 RTPS Time-stamp timer pre-scale. Must be programmed to generate a 1-µs period input clock to the time-stamp timer. (Time-stamp frequency = (CPM frequency)/(RTPS+2) 13.3.
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Part IV. Communications Processor Module 13.4 Command Set The core issues commands to the CP by writing to the CP command register (CPCR). The CPCR rarely needs to be accessed. For example, to terminate the transmission of an SCCÕs frame without waiting until the end, a STOP TX command must be issued through the CP command register (CPCR). 13.4.
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Part IV. Communications Processor Module Table 13-6. CP Command Register Field Descriptions (Continued) Bit Name Description 6Ð10 SBC Sub-block code. Set by the core to specify the sub-block on which the command is to operate.
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Part IV. Communications Processor Module 13.4.1.1 CP Commands The CP command opcodes are shown in Table 13-7. Table 13-7.
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Part IV. Communications Processor Module The commands in Table 13-7 are described in Table 13-8. Table 13-8. Command Descriptions Command INIT TX AND RX PARAMS INIT RX PARAMS INIT TX PARAMS ENTER HUNT MODE Description Initialize transmit and receive parameters. Initializes the transmit and receive parameters in the parameter RAM to the values that they had after the last reset of the CP. This command is especially useful when switching protocols on a given peripheral controller.
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Part IV. Communications Processor Module 13.4.2 Command Register Example To perform a complete reset of the CP, the value 0x8001_0000 should be written to the CPCR. Following this command, the CPCR returns the value 0x0000_0000 after two clocks. 13.4.3 Command Execution Latency The worst-case command execution latency is 200 clocks and the typical command execution latency is about 40 clocks. 13.5 Dual-Port RAM The CPM has 24 Kbytes of static RAM. Figure 13-7 is a block diagram of the dual-port RAM.
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Part IV.
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Part IV. Communications Processor Module Only the parameters in the parameter RAM and the microcode RAM option require Þxed addresses to be used. The BDs, buffer data, and scratchpad RAM can be located in the dualport system RAM or in any unused parameter RAM, such as, in the area made available when a peripheral controller or sub-block is not being used. Microcode can be executed from the Þrst 12 Kbytes.
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Part IV. Communications Processor Module Table 13-10.
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Part IV. Communications Processor Module timer tables. These timers are clocked from an internal timer that only the CP uses. The following is a list of the RISC timer tables important features. ¥ ¥ Supports up to 16 timers. Two timer modes: one-shot and restart. ¥ Maskable interrupt on timer expiration. ¥ Programmable timer resolution as Þne as 7.7µs at 133 MHz (6.17 µs at 166 MHz). ¥ Maximum timeout period of 31.8 seconds at 133 MHz (25.5 seconds at 166 MHz).
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Part IV. Communications Processor Module The RISC timer table parameter RAM area begins at the RISC timer base address and is used for the general timer parameters; see Table 13-11. Table 13-11. RISC Timer Table Parameter RAM Offset1 0x00 Name Description TM_BASE RISC timer table base address. The actual timers are a small block of memory in the dual-port RAM. TM_BASE is the offset from the beginning of the dual-port RAM where that block resides.
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Part IV. Communications Processor Module TM_CMD Þelds are described in Figure 13-11. Figure 13-11. TM_CMD Field Descriptions Bits Name Description 0 V Valid. This bit should be set to enable the timer and cleared to disable it. 1 R Restart. Should be set for an automatic restart or cleared for a one-shot operation of the timer. 2Ð11 Ñ Reserved. These bits should be written with zeros. 12Ð15 TN Timer number.
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Part IV. Communications Processor Module 13.6.5 SET TIMER Command The SET TIMER command is used to enable, disable, and conÞgure the 16 timers in the RISC timer table and is issued to the CPCR. This means the value 0x29E1008 should be written to CPCR. However, before writing this value, the user should program the TM_CMD Þelds. See Section 13.6.2, ÒRISC Timer Command Register (TM_CMD).Ó 13.6.6 RISC Timer Initialization Sequence The following sequence initializes the RISC timers: 1.
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Part IV. Communications Processor Module 3. (Optional) Write 0x0000 to the TM_CNT Þeld in the RISC timer table parameter RAM to see how many ticks elapsed since the RISC internal timer was enabled. 4. Write 0xFFFF to the RTER to clear any previous events. 5. Write 0x0001 to the RTMR to enable RISC timer 0 to generate an interrupt. 6. Write 0x0002_0000 to the SIU interrupt mask register (SIMR_L) to allow the RISC timers to generate a system interrupt. Initialize the SIU interrupt conÞguration register. 7.
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Part IV. Communications Processor Module 13.6.10 Using the RISC Timers to Track CP Loading The RISC timers can be used to track CP loading. The following sequence provides a way to use the 16 RISC timers to determine if the CP ever exceeds the 96% utilization level during any tick interval. Removing the timers adds a 4% margin to the CP utilization level, but the aggressive user can use this technique to push CP performance to its limit.
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Chapter 14 Serial Interface with Time-Slot Assigner 140 140 Figure 14-1 shows a block diagram of the TSA. Two SI blocks in the MPC8260 (SI1 and SI2), can be programmed to handle eight TDM lines concurrently with the same ßexibility described in this manual. TDM channels on SI1 are referred to as TDMa1, TDMb1, TDMc1, TDMd1; TDM channels on SI2 are TDMa2, TDMb2, TDMc2, TDMd2. MOTOROLA Chapter 14.
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Part IV.
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Part IV. Communications Processor Module 14.1 Features Each SI has the following features: ¥ Can connect to four independent TDM channels.
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Part IV. Communications Processor Module 14.2 Overview The TSA implements both internal route selection and time-division multiplexing (TDM) for multiplexed serial channels. The TSA supports the serial bus rate and format for most standard TDM buses, including T1 and E1 highways, pulse-code modulation (PCM) highway, and the ISDN buses in both basic and primary rates. The two popular ISDN basic rate buses (interchip digital link (IDL) and general-circuit interface (GCI), also known as IOM-2) are supported.
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Part IV.
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Part IV. Communications Processor Module At its most ßexible, the TSA can provide four separate TDM channels, each with independent receive and transmit routing assignments and independent sync pulse and clock inputs. Thus, the TSA can support eight, independent, half-duplex TDM sources, four in reception and four in transmission, using eight sync inputs and eight clock inputs. Figure 14-3 shows a dual-channel example.
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Part IV. Communications Processor Module associated with the dual-port RAM. One SIx RAM is always used to program the transmit routing; the other is always used to program the receive routing. SIx RAMs can be used to deÞne the number of bits/bytes to be routed to the MCC, FCC, SCC, or SMC and determine when external strobes are to be asserted and negated. The size of the SIx RAM available for time-slot programming depends on the userÕs conÞguration.
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Part IV. Communications Processor Module MCCx TDM a channels TDM b channels TDM c channels TDM d channels SIx RAM Time-Slot Assigner FCC1 FCC2 FCC3 SCC1 SCC2 En TDM a Pins En TDM b Pins En TDM c Pins En TDM d Pins FC1 = 0 MII1/UTOPIA 16 FC2 = 0 MII2/UTOPIA 8 FC3 = 0 MII3 SC1 = 0 SCC1 pins SC2 = 0 SCC2 pins SC3 = 0 SCC3 SC4 = 0 SCC4 SMC1 SMC2 SCC3 pins NMSI Mode TDM a,b,c,d Enable = 1 SCC4 pins SMC1 = 0 SMC1 pins SMC2 = 0 SMC2 pins In the CPM mux Figure 14-4.
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Part IV. Communications Processor Module 14.4.1 One Multiplexed Channel with Static Frames The example in Figure 14-5 shows one of many possible settings. With this conÞguration, the SIx RAM has 256 entries for transmit data and strobe routing and 256 entries for receive data and strobe routing. This conÞguration should be chosen only when one TDM is required and the routing on that TDM does not need to be dynamically changed. The number of entries available in the SIx RAM is determined by the user.
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Part IV. Communications Processor Module SIx RAM Address: (16 Bits Wide) Framing Signals 256 0 L1TCLKax L1TSYNCax 128 Entries TXa Route 255 511 1024 1280 L1RCLKax L1RSYNCax 128 Entries RXa Route 1279 1535 Figure 14-6. One TDM Channel with Shadow RAM for Dynamic Route Change This conÞguration should be chosen when only one TDM is needed, but dynamic rerouting may be needed on that TDM.
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Part IV. Communications Processor Module Table 14-1. SIx RAM Entry (MCC = 0) Bits Name Description 0 MCC 1 SWTR Switch Tx and Rx. Valid only in the receive route RAM and ignored in the transmit route RAM. SWTR affects the operation of both L1RXD and L1TXD. SWTR is set only in special situations where the user prefers to receive data from a transmit pin and transmit data on a receive pin. For instance, where devices A and B are connected to the same TDM, each with different time-slots.
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Part IV. Communications Processor Module Table 14-1. SIx RAM Entry (MCC = 0) (Continued) Bits Name Description 11Ð13 CNT Count. Indicates the number of bits/bytes (according to the BYT bit) that the routing and strobe select of this entry controls. 000 = 1 bit/byte; 111= 8 bits/bytes. 14 BYT Byte resolution 0 Bit resolution. The CNT value indicates the number of bits in this group. 1 Byte resolution. The CNT value indicates the number of bytes in this group. 15 LST Last entry in the RAM.
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Part IV. Communications Processor Module When MCC = 1, the SIx RAM entry Þelds function as described in Table 14-2. Table 14-2. SIx RAM Entry (MCC = 1) Bits Name Description 0 MCC If MCC =1, the other SIx RAM entries in this table are valid: 1 LOOP/ ECHO Channel loopback or echo. 0 Normal mode of operation. 1 Operation depends on the following conÞgurations: In the receive SIx RAM, this bit selects loopback mode for this MCC channel.
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Part IV. Communications Processor Module First, divide the frame from the start (the sync) to the end of the frame according to the support that is required: ¥ 8 bits (B1)ÑSCC2 ¥ ¥ 1 bit (D)ÑSCC1 + strobe 1 1 bitÑno support ¥ 4 bits (B2)Ñstrobe 2 ¥ 4 bits (B2)ÑSMC1 ¥ 1 bit (D)ÑSCC1 + strobe 1 Each of these six divisions can be supported by a single SIx RAM entry. Thus, six SIx RAM entries are needed. See Table 14-3. Table 14-3.
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Part IV. Communications Processor Module ¥ Dynamic routing. A TDMÕs routing deÞnition can be modiÞed while FCCs, MCCs, SCCs, or SMCs are connected to the TDM. The number of SIx RAM entries is determined by the banks the user relates to the corresponding TDM channel and is divided into four parts (Rx, Rx shadow, Tx, and Tx shadow). Dynamic changes divide portions of the SIx RAM into current-route and shadow RAM.
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Part IV. Communications Processor Module 1) Initial State RAM Address: 0 The TSA uses the first part of the RAM, and the shadow is the second part of the RAM.
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Part IV. Communications Processor Module 14.5 Serial Interface Registers The serial interface registers are described in the following sections. The MCC conÞguration registers, which deÞne the TDM mapping of the MCC channels, are described in Section 27.8, ÒMCC ConÞguration Registers (MCCFx).Ó Note that the programming of SI registers and SIx RAM must be coherent with the MCCF programming. 14.5.
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Part IV. Communications Processor Module Bits 0 Field Ñ 1 2 SADx 3 4 5 SDMx 6 7 RFSDx 8 9 10 11 12 13 DSCx CRTx SLx CEx FEx GMx Reset 0000_0000_0000_0000 R/W R/W Addr 0x11B20 (SI1AMR), 0x11B22 (SI1BMR), 0x11B24 (SI1CMR), 0x11B26 (SI1DMR)/ 0x11B40 (SI2AMR), 0x11B42 (SI2BMR), 0x11B44 (SI2CMR), 0x11B46 (SI2DMR) 14 15 TFSDx Figure 14-11. SI Mode Registers (SIxMR) Table 14-5 describes SIxMR Þelds. Table 14-5. SIxMR Field Descriptions Bits Name Description 0 Ñ Reserved.
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Part IV. Communications Processor Module Table 14-5. SIxMR Field Descriptions (Continued) Bits Name Description 6Ð7 RFSDx Receive frame sync delay for TDM a, b, c, or d. Determines the number of clock delays between the receive sync and the Þrst bit of the receive frame. Even if CRTx is set, these bits do not control the delay for the transmit frame. 00 No bit delay. The Þrst bit of the frame is transmitted/received on the same clock as the sync; use for GCI. 01 1-bit delay.
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Part IV. Communications Processor Module Table 14-5. SIxMR Field Descriptions (Continued) Bits Name Description 13 GMx Grant mode for TDM a, b, c or d 0 GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is internally supported. The grant is one bit from the receive channel. This bit is marked by programming the channel select bits of the SIx RAM with 0111 to assert an internal strobe on it. See Section 14.7.2.2, ÒSCIT Programming.Ó 1 IDL mode.
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Part IV. Communications Processor Module Figure 14-14 shows the effects of changing FE when CE = 1 with a 1-bit frame sync delay. CE=1 xFSD=01 L1CLK L1SYNC (FE=0) L1SYNC (FE=1) L1TxD (Bit-0) L1ST (On Bit-0) L1ST Driven from Clock High for Both FE Settings Rx Sampled Here Figure 14-14. Falling Edge (FE) Effect When CE = 1 and xFSD = 01 Figure 14-15 shows the effects of changing FE when CE = 0 with a 1-bit frame sync delay.
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Part IV. Communications Processor Module Figure 14-16 shows the effects of changing FE when CE = 1 with no frame sync delay. CE=1 xFSD=00 L1CLK (FE=0) L1SYNC L1TXD (Bit-0) L1ST (On Bit-0) The L1ST is Driven from Sync. Data is Driven from Clock Low. Rx Sampled Here (FE=0) L1SYNC L1TXD (Bit-0) L1ST (On Bit-0) L1ST is Driven from Clock High. L1SYNC (FE=1) L1TXD (Bit-0) L1ST (On Bit-0) Both Data Bit-0 and L1ST are Driven from Sync.
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Part IV. Communications Processor Module Figure 14-17 shows the effects of changing FE when CE = 0 with no frame sync delay. CE=0 xFSD=00 L1CLK (FE=1) L1SYNC L1TXD (Bit-0) L1ST (On Bit-0) The L1ST is Driven from Sync. Data is Driven From Clock High. Rx Sampled Here (FE=1) L1SYNC L1TXD (Bit-0) L1ST (On Bit-0) L1ST is Driven from Clock Low. L1SYNC (FE=0) L1TXD (Bit-0) L1ST (On Bit-0) Both the Data and L1ST from Sync when Asserted during Clock High.
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Part IV. Communications Processor Module Bits 0 1 Field Ñ 2 3 SSADA 4 5 Ñ 6 7 SSADB 8 9 Ñ 10 11 SSADC Reset 0000_0000_0000_0000 R/W R/W Addr 0x11B2E (SI1RSR), 0x11B4E (SI2RSR) 12 13 Ñ 14 15 SSADD Figure 14-18. SIx RAM Shadow Address Registers (SIxRSR) Table 14-6 describes SIxRSR Þelds. Table 14-6. SIxRSR Field Descriptions Bits Name 0, 4, 8, Ñ 12 1Ð3, 5Ð7, 9Ð11, 13Ð15 Description Reserved. Should be cleared.
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Part IV. Communications Processor Module Table 14-7 describes SIxCMDR Þelds. Table 14-7. SIxCMDR Field Description Bits Name Description 0, 2, 4, 6 CSRRx Change shadow RAM for TDM a, b, c, or d receiver. Set CSRRx causes the SI receiver to replace the current route RAM with the shadow RAM. Set by the user and cleared by the SI. 0 The receiver shadow RAM is not valid. The user can write into the shadow RAM to program a new routing. 1 The receiver shadow RAM is valid.
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Part IV. Communications Processor Module In the basic rate of IDL, data on three channels (B1, B2, and D) is transferred in a 20-bit frame, providing a full-duplex bandwidth of 160 Kbps. The MPC8260 is an IDL slave device that is clocked by the IDL bus master (physical layer device) and has separate receive and transmit sections. Although the MPC8260 has eight TDMs, it can support only four independent IDL buses (limited by the number of serials that support IDL) using separate clocks and sync pulses.
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Part IV. Communications Processor Module System Bus (ROM and RAM) PCM CODEC/Filter Monocircuit B1 POTS ASYNC SMC1 SPI MPC8260 SMC2 SCC2 SCC3 SCC1 TSA IDL (Data) B2+D ICL (Control) S/T Transceiver Ethernet 4 wire B1+B2+D Ethernet PHY LAN Figure 14-22. IDL Terminal Adaptor The MPC8260 can identify and support each IDL channel or can output strobe lines for interfacing devices that do not support the IDL bus. The IDL signals for each transmit and receive channel are described in Table 14-9.
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Part IV. Communications Processor Module The basic rate IDL bus has the three following channels: ¥ B1 is a 64-Kbps bearer channel ¥ B2 is a 64-Kbps bearer channel ¥ D is a 16-Kbps signaling channel There are two deÞnitions of the IDL bus frame structureÑ8 and 10 bits. The only difference between them is the channel order within the frame. See Figure 14-23. L1CLK L1SYNC 10-Bit IDL L1RXD B1 D1 B2 D2 L1TXD B1 D1 B2 D2 8-Bit IDL L1RXD B1 B2 D1 D2 L1TXD B1 B2 D1 D2 Notes: 1.
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Part IV. Communications Processor Module of the D channel. If a collision is detected on the D channel, the physical layer device negates L1GRx. The MPC8260 then stops sending and retransmits the frame when L1GRx is reasserted. This procedure is handled automatically for the Þrst two buffers of a frame. For the primary rate IDL, the MPC8260 supports up to four 8-bit channels in the frame, determined by the SIx RAM programming.
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Part IV. Communications Processor Module For example, based on the same 10-bit format as in Section 14.4.4, ÒSIx RAM Programming Example,Ó implement an IDL bus using SCC1, SCC2, and SMC1 connected to TDMa1 as follows: 1. Program both the Tx and Rx sections of the SIx RAM as in Table 14-10. Table 14-10.
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Part IV. Communications Processor Module 19. SI1CMDR is not used. 20. SI1STR does not need to be read. 21. ConÞgure the SCC1 for HDLC operation (to handle the LAPD protocol of the D channel), and conÞgure SCC2 and SMC1 as preferred. 22. SI1GMR = 0x01. Enable TDM A (one static TDM). 23. Enable SCC1, SCC2 and SMC1. 14.7 Serial Interface GCI Support The MPC8260 fully supports the normal mode of the GCI, also known as the ISDNoriented modular revision 2.2 (IOM-2), and the SCIT.
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Part IV. Communications Processor Module L1CLK (2X the data rate) L1SYNC L1RXD B1 B2 M (Monitor) D1 D2 C/I A E L1TXD B1 B2 M (Monitor) D1 D2 C/I A E Notes: Clock is not to scale. L1CLKO is not shown. Figure 14-24.
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Part IV. Communications Processor Module 14.7.1 SI GCI Activation/Deactivation Procedure In the deactivated state, the clock pulse is disabled and the data line is at a logic one. The layer 1 device activates the MPC8260 by enabling the clock pulses and by an indication in the channel 0 C/I channel. The MPC8260 reports to the core (via a maskable interrupt) that a valid indication is in the SMC RxBD. When the core activates the line, the data output of L1TXDn is programmed to zero by setting SIxGMR[STZx].
PAGE 488
Part IV. Communications Processor Module For example, assuming that SCC1 is connected to the D channel, SCC2 to the B1 channel, and SMC2 to the B2 channel, SMC1 is used to handle the C/I channels, and the D-channel grant is on bit 4 of the C/I on SCIT channel 2, the initialization sequence is as follows: 1. Program both the Tx and Rx sections of the SIx RAM as in Table 14-12 beginning at addresses 0 and 1024, respectively. Table 14-12.
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Part IV. Communications Processor Module 14. Clear PSORB[17]. ConÞgures L1CLKO and L1RQa. 15. Set PDIRB[17]. ConÞgures L1CLKO and L1RQa. 16. If the 1x GCI data clock is required, set PBPAR bit 16 and PBDIR bit 16 and clear PSORB 16, which conÞgures L1CLKOa as an output. 17. ConÞgure SCC1 for HDLC operation (to handle the LAPD protocol of the D channel). ConÞgure SMC1 for SCIT operation and conÞgure SCC2 and SMC2 as preferred. 18. SI1GMR = 0x11. Enable TDMa (one static TDM), STZ for TDMa. 19.
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Part IV.
PAGE 491
Chapter 15 CPM Multiplexing 150 150 The CPM multiplexing logic (CMX) connects the physical layerÑUTOPIA, MII, modem lines, TDM lines and proprietary serial lines to the FCCs, SCCs and SMCs. The CMX features the following two modes: ¥ In NMSI mode, the CMX allows all serial devices to be connected to their own set of individual pins. Each serial device that connects to the external world in this way is said to connect to a nonmultiplexed serial interface (NMSI).
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Part IV.
PAGE 493
Part IV. Communications Processor Module The multiple-PHY addressing selection supports the following options for FCC1 and FCC2: ¥ In master mode: Ñ FCC1 connect up to 31 PHYs and FCC2 connect up to 7 PHYs. Ñ FCC1 connect up to 15 PHYs and FCC2 connect up to 15 PHYs. Ñ FCC1 connect up to 7 PHYs and FCC2 connect up to 31 PHYs. ¥ In slave mode: Ñ Ñ Ñ Ñ Ñ Ñ FCC1 connect up to 31 PHYs and FCC2 connect to 0 PHYs. FCC1 connect up to 15 PHYs and FCC2 connect up to 1 PHYs.
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Part IV. Communications Processor Module MCCs TDM a channels TDM b channels TDM c channels TDM d channels TDM a,b,c,d Enable = 1 Time-Slot Assigners FCC1 FCC2 FCC3 SCC1 SCC2 TDM a Pins En TDM b Pins En TDM c Pins En TDM d Pins FC1 = 0 MII1/UTOPIA 8/16/M-phy FC2 = 0 MII2/UTOPIA 8/M-phy FC3 = 0 MII3 SC1 = 0 SCC1 Pins SC2 = 0 SCC2 Pins SC3 = 0 SCC3 SC4 = 0 SCC4 SMC1 SMC2 SCC3 Pins SCC4 Pins SMC1 = 0 SMC1 Pins SMC2 = 0 SMC2 Pins NMSI Mode SI RAMs En Figure 15-2.
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Part IV. Communications Processor Module BRG5 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 Rx BRG1 BRG6 BRG2 BRG7 BRG3 BRG8 BRG4 BRGO5 BRGO6 BRGO7 BRGO8 BRGO1 BRGO2 BRGO3 BRGO4 Tx Rx Tx Rx Tx Rx Tx Rx Tx Bank of Clocks Selection Logic Rx Tx (Partially filled cross-switch logic programmed in the CMX registers.
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Part IV. Communications Processor Module Table 15-1.
PAGE 497
Part IV. Communications Processor Module 15.4.1 CMX UTOPIA Address Register (CMXUAR) The CMX UTOPIA address register (CMXUAR), shown in Figure 15-4, deÞnes the connection of FCC1 and FCC2 UTOPIA multiple-PHY addresses to the twenty UTOPIA address pins of the MPC8260; it also deÞnes the connection of a BRG to the FCCs when an internal rate feature is used. This enables the user to implement a multiple-PHY UTOPIA master or slave on both FCC1 and FCC2 using only twenty pins.
PAGE 498
Part IV. Communications Processor Module Note that each SADx and MADx corresponds to a pair of separate receive and transmit address pins. The MPC8260 has 16 output address pins and 10 input address pins dedicated for the UTOPIA interface. However, it has two FCCs with two parts eachÑreceiver and transmitter that can be ether master or slave concurrently.
PAGE 499
Part IV. Communications Processor Module Pins 5 5 8 FCC1 M S 5 5 These 5 address bits relate to the slave of FCC1 or FCC2 according to the programming. Bit 4 is the msb. 4 3 2 1 0 0 1 2 3 4 5 S 5 5 8 M FCC2 M S 5 5 NOTE: To use FCC2 as shown, connect the FCC2 address bits reversed with respect to the pinout address indexes. PHY address pins with no pin connection should be connected to GND. 5 M S Figure 15-6.
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Part IV.
PAGE 501
Part IV. Communications Processor Module Bits 0 1 2 3 Field RTA1CS RTB1CS RTC1CS RTD1CS 4 5 6 7 TTA1CS TTB1CS TTC1CS TTD1CS Reset 0000_0000 R/W R/W Addr 0x11B00 Figure 15-8. CMX SI1 Clock Route Register (CMXSI1CR) Table 15-3 describes CMXSI1CR Þelds. Table 15-3. CMXSI1CR Field Descriptions Bits Name Description 0 RTA1CS Receive TDM A1 clock source 0 TDM A1 receive clock is CLK1. 1 TDM A1 receive clock is CLK19.
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Part IV. Communications Processor Module Bits 0 1 2 3 Field RTA2CS RTB2CS RTC2CS RTD2CS 4 5 6 7 TTA2CS TTB2CS TTC2CS TTD2CS Reset 0000_0000 R/W R/W Addr 0x11B02 Figure 15-9. CMX SI2 Clock Route Register (CMXSI2CR) Table 15-4 describes CMXSI2CR Þelds. Table 15-4. CMXSI2CR Field Descriptions Bits Name Description 0 RTA2CS Receive TDM A2 clock source 0 TDM A2 receive clock is CLK13. 1 TDM A2 receive clock is CLK5.
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Part IV. Communications Processor Module Bits 0 1 Field Ñ FC1 2 3 4 5 RF1CS 6 7 TF1CS 8 9 Ñ FC2 Reset 0000_0000_0000_0000 R/W R/W Addr 10 11 12 13 RF2CS 14 15 TF2CS 0x11B04 Bits 16 17 Field Ñ FC3 18 19 20 21 RF3CS 22 23 24 25 26 TF3CS 27 28 29 30 31 Ñ Reset 0000_0000_0000_0000 R/W R/W Addr 0x11B06 Figure 15-10. CMX FCC Clock Route Register (CMXFCR) Table 15-5 describes CMXFCR Þelds. Table 15-5.
PAGE 504
Part IV. Communications Processor Module Table 15-5. CMXFCR Field Descriptions (Continued) Bits Name Description 10Ð12 RF2CS Receive FCC2 clock source (NMSI mode). Ignored if FCC2 is connected to the TSA (FC2 = 1). 000 FCC2 receive clock is BRG5. 001 FCC2 receive clock is BRG6. 010 FCC2 receive clock is BRG7. 011 FCC2 receive clock is BRG8. 100 FCC2 receive clock is CLK13. 101 FCC2 receive clock is CLK14. 110 FCC2 receive clock is CLK15. 111 FCC2 receive clock is CLK16.
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Part IV. Communications Processor Module Bits Field 0 1 2 GR1 SC1 3 4 5 RS1CS 6 7 8 TS1CS 9 GR2 SC2 Reset 0000_0000_0000_0000 R/W R/W Addr Bits Field 10 11 12 13 RS2CS 14 15 TS2CS 0x11B08 16 17 GR3 SC3 18 19 20 21 RS3CS 22 TS3CS 23 24 25 GR4 SC4 Reset 0000_0000_0000_0000 R/W R/W Addr 0x11B0A 26 27 28 RS4CS 29 30 31 TS4CS Figure 15-11. CMX SCC Clock Route Register (CMXSCR) Table 15-6 describes CMXSCR Þelds. Table 15-6.
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Part IV. Communications Processor Module Table 15-6. CMXSCR Field Descriptions (Continued) Bits Name Description 8 GR2 Grant support of SCC2 0 SCC2 transmitter does not support the grant mechanism. The grant is always asserted internally. 1 SCC2 transmitter supports the grant mechanism as determined by the GMx bit of a serial device channel. 9 SC2 SCC2 connection 0 SCC2 is not connected to the TSA and is either connected directly to the NMSIx pins or is not used.
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Part IV. Communications Processor Module Table 15-6. CMXSCR Field Descriptions (Continued) Bits Name Description 21Ð23 TS3CS Transmit SCC3 clock source (NMSI mode). Ignored if SCC3 is connected to the TSA (SC3 = 1). 000 SCC3 transmit clock is BRG1. 001 SCC3 transmit clock is BRG2. 010 SCC3 transmit clock is BRG3. 011 SCC3 transmit clock is BRG4. 100 SCC3 transmit clock is CLK5. 101 SCC3 transmit clock is CLK6. 110 SCC3 transmit clock is CLK7. 111 SCC3 transmit clock is CLK8.
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Part IV. Communications Processor Module Bits 0 1 Field SMC1 Ñ 2 3 SMC1CS 4 5 SMC2 Ñ Reset 0000_0000 R/W R/W Addr 0x11B0C 6 7 SMC2CS Figure 15-12. CMX SMC Clock Route Register (CMXSMR) Table 15-7 describes CMXSMR Þelds. Table 15-7. CMXSMR Field Descriptions Name Name Description 0 SMC1 SMC1 connection 0 SMC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not used.
PAGE 509
Chapter 16 Baud-Rate Generators (BRGs) 160 160 The CPM contains eight independent, identical baud-rate generators (BRGs) that can be used with the FCCs, SCCs, and SMCs. The clocks produced by the BRGs are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. In addition, the output of a BRG can be routed to a pin to be used externally.
PAGE 510
Part IV. Communications Processor Module Each BRG clock source can be BRGCLK, or a choice of two external clocks (selected in BRGCx[EXTC]). The BRGCLK is an internal signal generated in the MPC8260 clock synthesizer speciÞcally for the BRGs, the SPI, and the I2C internal BRG. Alternatively, external clock pins can be conÞgured as clock sources. The external source option allows ßexible baud-rate frequency generation, independent of the system frequency.
PAGE 511
Part IV. Communications Processor Module Table 16-1 describes the BRGCx Þelds. Table 16-1. BRGCx Field Descriptions Bits Name Description 0Ð13 Ñ Reserved, should be cleared. 14 RST Reset BRG. Performs a software reset of the BRG identical to that of an external reset. A reset disables the BRG and drives BRGO high. This is externally visible only if BRGO is connected to the corresponding parallel I/O pin. 0 Enable the BRG. 1 Reset the BRG (software reset). 15 EN Enable BRG count.
PAGE 512
Part IV. Communications Processor Module Table 16-2. BRG External Clock Source Options CLK BRG 1 BRG1 BRG2 BRG3 BRG4 BRG5 BRG6 BRG7 BRG8 2 3 V V V V 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 V V V V V V V V V V V V 16.2 Autobaud Operation on a UART During the autobaud process, a UART deduces the baud rate of its received character stream by examining the received pattern and its timing.
PAGE 513
Part IV. Communications Processor Module 16.3 UART Baud Rate Examples For synchronous communication using the internal BRG, the BRGO output clock must not exceed the system frequency divided by 2. So, with a 66-MHz system frequency, the maximum BRGO rate is 33 MHz. Program the UART to 16´ oversampling when using the SCC as a UART. Rates of 8´ and 32´ are also available. Assuming 16´ oversampling is chosen in the UART, the maximum data rate is 66 MHz Ö 16 = 4.125 Mbps.
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Part IV. Communications Processor Module For synchronous communication, the internal clock is identical to the baud-rate output.
PAGE 515
Chapter 17 Timers 170 170 The CPM includes four identical 16-bit general-purpose timers or two 32-bit timers. Each general-purpose timer consists of a timer mode register (TMR), a timer capture register (TCR), a timer counter (TCN), a timer reference register (TRR), a timer event register (TER), and a timer global conÞguration register (TGCR). The TMRs contain the prescaler values programmed by the user. Figure 17-1 shows the timer block diagram.
PAGE 516
Part IV. Communications Processor Module 17.
PAGE 517
Part IV. Communications Processor Module output can also be connected internally to the input of another timer, resulting in a 32-bit timer. In addition, each timer has a 16-bit TCR used to latch the value of the counter when a deÞned transition of TIN1, TIN2, TIN3, or TIN4 is sensed by the corresponding input capture edge detector. The type of transition triggering the capture is selected by the corresponding TMR[CE] bits.
PAGE 518
Part IV. Communications Processor Module Timer1 Timer2 TRR, TCR, TCN connected to D[0Ð15] Clock TRR, TCR, TCN connected to D[16Ð31] Capture Timer3 Clock Timer4 TRR, TCR, TCN connected to D[0Ð15] TRR, TCR, TCN connected to D[16Ð31] Capture Figure 17-2. Timer Cascaded Mode Block Diagram If TGCR[CAS] = 1, the two timers function as a 32-bit timer with a 32-bit TRR, TCR, and TCN. In this case, TMR1 and/or TMR3 are ignored, and the modes are deÞned using TMR2 and/or TMR4.
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Part IV. Communications Processor Module Table 17-1. TGCR1 Field Descriptions (Continued) Bits Name Description 3 RST2 Reset timer. 0 Reset the corresponding timer (a software reset is identical to an external reset). 1 Enable the corresponding timer if the STP bit is cleared. 4 GM1 Gate mode for TGATE1. This bit is valid only if the gate function is enabled in TMR1 or TMR2. 0 Restart gate mode. TGATE1 is used to enable/disable count.
PAGE 520
Part IV. Communications Processor Module Table 17-2. TGCR2 Field Descriptions (Continued) Bit Name Description 4 GM2 5 Ñ 6 STP3 Stop timer. 0 Normal operation. 1 Reduce power consumption of the timer. This bit stops all clocks to the timer, however it is possible to read the values while the clock is stopped. The clocks to the timer remain stopped until the user clears this bit or a hardware reset occurs. 7 RST3 Reset timer.
PAGE 521
Part IV. Communications Processor Module Table 17-3. TMRIÐTMR4 Field Descriptions (Continued) Bits Name Description 10 OM Output mode 0 Active-low pulse on TOUTx for one timer input clock cycle as deÞned by the ICLK bits. Thus, TOUTx may be low for one general system clock period, one general system clock/16 period, or one TINx clock cycle period. TOUTx changes occur on the rising edge of the system clock. 1 Toggle TOUTx. TOUTx changes occur on the rising edge of the system clock.
PAGE 522
Part IV. Communications Processor Module 17.2.5 Timer Capture Registers (TCR1ÐTCR4) Each timer capture register (TCR1ÐTCR4), shown in Figure 17-7, is used to latch the value of the counter according to TMRx[CE]. Bit 0 1 2 3 4 5 6 7 8 9 Field Latched counter value Reset 0x0000 10 11 12 13 R/W R/W Addr 0x10D98 (TCR1), 0x10D9A (TCR2), 0x10DA8 (TCR3), 0x10DAA (TCR4) 14 15 Figure 17-7. Timer Capture Registers (TCR1ÐTCR4) 17.2.
PAGE 523
Part IV. Communications Processor Module Table 17-4 describes TER Þelds. Table 17-4. TER Field Descriptions Bits Name 0Ð13 Ð 14 REF Output reference event. The counter has reached the TRR value. TMR[ORI] is used to enable the interrupt request caused by this event. 15 CAP Capture event. The counter value has been latched into the TCR. TMR[CE] is used to enable generation of this event. MOTOROLA Description Reserved, should be cleared. Chapter 17.
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Part IV.
PAGE 525
Chapter 18 SDMA Channels and IDMA Emulation 180 180 The MPC8260 has two physical serial DMA (SDMA) channels. The CP implements two dedicated virtual SDMA channels for each FCC, MCC, SCC, SMC, SPI, and I2CÑone for each transmitter and receiver. An additional four virtual SDMA channels are assigned to the programmable independent DMA (IDMA) channels. Figure 18-1 shows data ßow paths. Data from the peripheral controllers can be routed to external RAM using the 60x bus (path 1) or the local bus (path 2).
PAGE 526
Part IV. Communications Processor Module On a path 1 access, the SDMA channel must acquire the external system bus. On a path 2 access, the local bus is acquired and the access is not seen on the external system bus. Thus, the local bus transfer occurs at the same time as other operations on the external 60x system bus. The SDMA channel can be assigned abig-endian (Motorola) or little-endian format for accessing buffer data.
PAGE 527
Part IV. Communications Processor Module Other Transaction SDMA Transaction Other Transaction CLK TS TA SDMA Internally Requests the Bus Figure 18-2. SDMA Bus Arbitration (Transaction Steal) 18.2 SDMA Registers The only user-accessible registers associated with the SDMA are the SDMA address registers, read-only register used for diagnostics in case of an SDMA bus error, the SDMA status register and the SDMA mask register. 18.2.
PAGE 528
Part IV. Communications Processor Module 18.2.2 SDMA Mask Register (SDMR) The SDMA mask register (SDMR) is an 8-bit read/write register with the same bit format as the SDMA status register. If an SDMR bit is 1, the corresponding interrupt in SDSR is enabled. If the bit is zero, the corresponding interrupt in the status register is masked. SDMR is cleared at reset. SDMR can be accessed at 0x1101C. 18.2.
PAGE 529
Part IV. Communications Processor Module 18.3 IDMA Emulation The CPM can be conÞgured to provide general-purpose DMA functionality through the SDMA channel. Four general-purpose independent DMA (IDMA) channels are supported. In this special emulation mode, the user can specify any memory-to-memory or peripheral-to/from-memory transfers as if using dedicated DMA hardware. The general-purpose IDMA channels can operate in different user-programmable data transfer modes.
PAGE 530
Part IV. Communications Processor Module Peripheral to/from memory features include the following: ¥ ¥ ¥ External DREQ, DACK, and DONE signals for each channel simpliÞes the peripheral interface for memory-to/from-peripheral transfers Supports 1-, 2-, 4-, and 8-byte peripheral port sizes Supports standard 60x burst accesses (four consecutive 64-bit data phases) to/from peripherals 18.
PAGE 531
Part IV. Communications Processor Module Table 18-3. IDMA Transfer Parameters Parameter Description DMA_WRAP Determines the size of the dedicated IDMA transfer buffer in dual-port RAM. The buffer size is a multiple of a 60x burst size (k*32 bytes). SS_MAX Initialized to (IDMA_transfer_buffer_size - 32) bytes, which is the steady-state maximum transfer size of IDMA transfer.
PAGE 532
Part IV. Communications Processor Module ¥ Last phase. The remaining data is read into the transfer buffer in bursts, with the last 1Ð31 bytes read in single accesses. All data in the transfer buffer is written to the destination bus in bursts, with the last 1Ð31 bytes written in single accesses. The last transfers, read/write or both can be accompanied with DONE assertion, if programmed. Figure 18-6 shows an example of the three IDMA transfer stages.
PAGE 533
Part IV. Communications Processor Module Because at least one of the transfer sizes (STS or DTS) equals SS_MAX, every DREQ assertion causes one transfer to the smaller (in STS/DTS terms) bus. If STS = DTS, asserting DREQ triggers one read transfer automatically followed by one write transfer. NOTE External request mode does not support external DONE signaling from a device and DACK signaling from an IDMA channel. 18.5.1.
PAGE 534
Part IV. Communications Processor Module Data can be transferred between a peripheral and memory in single- or dual-address accesses: ¥ ¥ For dual-address accesses, the data is read from the source, temporarily stored in the IDMA transfer buffer in the dual-port RAM, and then written to the destination. For single-address accesses (ßy-by mode), the data is transferred directly between memory and the peripheral.
PAGE 535
Part IV. Communications Processor Module peripheral. When the transfer buffer has fewer than DTS bytes left, the next DREQ assertion triggers a read of SS_MAX bytes from memory, automatically followed by a write to the peripheral, and the sequence begins again. External requests must be enabled (DCM[ERM] = 1) for dual-address peripheral-tomemory transfers.
PAGE 536
Part IV. Communications Processor Module 18.5.3 Controlling 60x Bus Bandwidth STS, DTS, and SS_MAX can be used to control the 60x bus bandwidth occupied by the IDMA channel. In every mode except ßy-by mode, at least one transfer size parameter (STS/DTS) must be initialized to the SS_MAX value. For memory-to-memory transfers, the other transfer size parameter can be initialized to a smaller value used to control the 60x bus bandwidth.
PAGE 537
Part IV. Communications Processor Module and DMA done (DONE[1Ð4]). DREQx may also be used to control the transfer pace of memory-to-memory transfers. ¥ DREQx is the external DMA request signal. ¥ DACKx is the DMA acknowledge. ¥ DONEx marks the end of an IDMA transfer. The IDMA signals are multiplexed with other internal controller signals at the parallel I/O ports. To enable the IDMA signals, the corresponding bits in the parallel I/O registers should be set. See Chapter 35, ÒParallel I/O Ports.
PAGE 538
Part IV. Communications Processor Module ignored until the request begins to be serviced. The servicing of the request results in one operand being transferred. Each time the IDMA issues a bus transaction to either read or write the device, the IDMA asserts DACK. The device must use TA and TEA for data validation. Thus, DACK is the acknowledgment of the original transaction request given on DREQx. 18.7.2 DONEx This bidirectional open-drain signal is used to indicate the last IDMA transfer.
PAGE 539
Part IV. Communications Processor Module allocation and eliminates the need for core intervention between transfers. BDs contain information describing the data block and special control options for the DMA operation while transferring the data block. 18.8.1 Auto Buffer and Buffer Chaining The core processor should initialize the IDMA BD table with the appropriate buffer handling mode, source address, destination address, and block length. See Figure 18-7.
PAGE 540
Part IV. Communications Processor Module 18.8.2 IDMAx Parameter RAM When an IDMAx channel is conÞgured to auto buffer or buffer chaining mode, the MPC8260 uses the IDMAx parameters listed in the Table 18-4. Parameters should be modiÞed only while the channel is disabled, that is, before the Þrst START_IDMA command or when the event registerÕs stop-completed bit (IDSR[SC]) is set following a STOP_IDMA command.
PAGE 541
Part IV. Communications Processor Module Table 18-4. IDMAx Parameter RAM (Continued) Offset 1 0x0E Name STS Width Description Hword Source transfer size in bytes. All transfers from the source (except the start alignment and the end) are written to the bus using this parameter. In memory-to-peripheral mode, STS should be initialized to SS_MAX. In peripheral-to-memory mode, STS should be initialized to the peripheral port size or peripheral transfer size (if the peripheral accepts bursts).
PAGE 542
Part IV. Communications Processor Module 18.8.2.1 DMA Channel Mode (DCM) The IDMA channel mode (DCM) is a 16-bit Þeld within the IDMA parameter RAM, that controls the operation modes of the IDMA channel. As are all other IDMA parameters, the DCM is undeÞned at reset. bits 0 1 Þeld FB LP 2 3 4 Ñ 5 6 TC2 Ñ 7 8 9 DMA_WRAP Reset Ñ R/W R/W 10 11 12 SINC DINC ERM 13 DT 14 15 S/D Figure 18-8. DCM Parameters Table 18-5 describes DCM bits. Table 18-5.
PAGE 543
Part IV. Communications Processor Module Table 18-5. DCM Field Descriptions (Continued) Bits Name Description 10 SINC Source increment address. 0 Source address pointer (S_PTR) is not incremented in the source read transaction. Should be cleared for peripheral-to-memory transfers if the peripheral has a Þxed address. 1 CP increments the source address pointer (S_PTR) with the number of bytes transferred in the source read transaction. Used for memory-to-memory and memory-to-peripheral transfers.
PAGE 544
Part IV. Communications Processor Module 18.8.2.2 Data Transfer Types as Programmed in DCM Table 18-6 summarizes the types of data transfers according to the DCM programming. Table 18-6. IDMA Channel Data Transfer Operation S/D FB Read From Write To 01 0 Memory (STS = SS_MAX) 10 0 Peripheral Memory (STS = port size or (DTS = 32) SS_MAX) Description (Steady-State Operation) Peripheral Read from memory: Filling internal buffer in one DMA transfer.
PAGE 545
Part IV. Communications Processor Module Table 18-7 describes valid STS/DTS values for memory-to-memory operations. Table 18-7.
PAGE 546
Part IV. Communications Processor Module Table 18-8.
PAGE 547
Part IV. Communications Processor Module Bits 0 1 2 Field 3 Ñ Reset 4 5 6 7 SC OB EDN BC 0000_0000 R/W R Addr R/W 0x11020 (IDSR1), 0x11028 (IDSR2), 0x11030 (IDSR3), 0x11038 (IDSR4)/ 0x11024 (IDMR1), 0x1102C (IDMR2), 0x11034 (IDMR3), 0x1103C (IDMR4) Figure 18-9. IDMA Event/Mask Registers (IDSR/IDMR) Table 18-9 describes IDSR/IDMR Þelds. Table 18-9. IDSR/IDMR Field Descriptions Bits Name Description 0Ð3 Ñ Reserved, should be cleared. 4 SC Stop completed.
PAGE 548
Part IV. Communications Processor Module Table 18-10 describes IDMA BD Þelds. Table 18-10. IDMA BD Field Descriptions Offset Bits Name 0x00 0 V Valid 0 This BD does not contain valid data for transfer. 1 This BD contain valid data for transfer. The CP checks this bit before starting a BD service. If this bit is cleared when the CP accesses the BD, an interrupt IDSR[OB] is issued to the core, the IDMA channel is stopped until a START_IDMA command is issued.
PAGE 549
Part IV. Communications Processor Module Table 18-10. IDMA BD Field Descriptions (Continued) Offset 0x02 Bits Name 11 DGBL 12-13 DBO 14 Ñ 15 DDTB 0-1 Ñ 2 SGBL 3-4 SBO Description Destination global 0 Snooping is not activated. 1 Snooping is activated for write transactions to the destination. In ßy-by mode, should be the same as SGBL. Destination byte ordering: 01 PowerPC little Endian. 1x Big endian (Motorola). 00 Reserved In ßy-by mode, should be the same as SBO.
PAGE 550
Part IV. Communications Processor Module 18.9 IDMA Commands The user has two commands to control each IDMA channel. These commands are executed through the CP command register (CPCR); see Section 13.4, ÒCommand Set.Ó 18.9.1 START_IDMA Command The START_IDMA command is used to start a transfer on an IDMA channel. The user must initialize all parameters relevant for the correct operation of the channel (IDMAx_BASE and IDMA channel parameter table) before issuing this command.
PAGE 551
Part IV. Communications Processor Module In external request mode (ERM = 1), STOP_IDMA command processing has priority over a peripheral asserting DONE. Note: In memory-to-peripheral, peripheral-to-memory, and ßy-by modes, if a STOP_IDMA command is issued with no data in the internal buffer, the BD is immediately closed and the channel is stopped. In this case, a peripheral expecting DONE to be asserted is not notiÞed because the last transfer of the buffer (with BD[DDN or SDN] set) is not performed. 18.
PAGE 552
Part IV. Communications Processor Module 18.11 Programming the Parallel I/O Registers The parallel I/O registers control the use of the external pins of the chip. Each pin can be used for different purposes. See Table 18-12, Table 18-13 and Table 18-14 (optional) for the proper parallel I/O register programming dedicating the proper external ports to the four IDMA channelsÕ external I/O signals. Each port is controlled by Þve I/O registers: PPAR, PSOR, PDIR, PODR, and PDAT.
PAGE 553
Part IV. Communications Processor Module Table 18-14 describes parallel I/O register programming for port D (optional). Table 18-14. Parallel I/O Register ProgrammingÑPort D Channel Signal Pin PPARD PDIRD PODRD PSORD Default IDMA1 DACK1 (O) PD[6] 1 1 0 1 Ñ DONE1 (I/O) PD[5] 1 0 1 1 VDD 18.12 IDMA Programming Examples These programming examples demonstrate the use of most of the different modes and conÞgurations of the IDMA channels. 18.12.
PAGE 554
Part IV. Communications Processor Module Table 18-15. Example: Peripheral-to-Memory ModeÑIDMA2 (Continued) Important Init Values Description Last BD(SDN) = 1 DONE is asserted on the last transfer from peripheral. Last BD(DDN) = 0 DONE is not asserted on the last transfer to memory. Every BD(DL) = k*STS Data length must be STS modular (divided by STS without residue). IDMR2 = 0x0300_0000 IDMA2 Mask register is programmed to enable EDN and BC interrupts only.
PAGE 555
Part IV. Communications Processor Module Table 18-16. Example: Memory-to-Peripheral Fly-By Mode (on 60x)ÐIDMA3 (Continued) Important Init Values Description DCM[ERM] = 1 Transfers from peripheral are initiated by DREQ. DCM[DT] = 1 Assertion of DONE by the peripheral terminates the transfer, interrupt EDN is set to the core, Current BD is closed and the next BD if valid is opened. Additional DREQ assertions cause the new BD to be transferred. DCM[S/D] = 01 Memory-to-peripheral mode.
PAGE 556
Part IV.
PAGE 557
Chapter 19 Serial Communications Controllers (SCCs) 190 190 The MPC8260 has four serial communications controllers (SCCs), which can be conÞgured independently to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks. An SCC has many physical interface options such as interfacing to TDM buses, ISDN buses, and standard modem interfaces.
PAGE 558
Part IV. Communications Processor Module Associated with each SCC is a digital phase-locked loop (DPLL) for external clock recovery, which supports NRZ, NRZI, FM0, FM1, Manchester, and Differential Manchester. If the clock recovery function is not required (that is, synchronous communication), then the DPLL can be disabled, in which case only NRZ and NRZI are supported. An SCC can be connected to its own set of pins on the MPC8260.
PAGE 559
Part IV. Communications Processor Module ¥ DPLL circuitry for clock recovery with NRZ, NRZI, FM0, FM1, Manchester, and Differential Manchester (also known as Differential Bi-phase-L) ¥ Clocks can be derived from a baud rate generator, an external pin, or DPLL ¥ Data rate for asynchronous communication can be as high as 16.
PAGE 560
Part IV. Communications Processor Module Table 19-1 describes GSMR_H Þelds. Table 19-1. GSMR_H Field Descriptions Bit Name Description 0Ð14 Ñ Reserved, should be cleared. 15 GDE Glitch detect enable. Determines whether the SCC searches for glitches on the external Rx and Tx serial clock lines. Regardless of the GDE setting, a Schmitt trigger on the input lines is used to reduce signal noise. 0 No glitch detection.
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Part IV. Communications Processor Module Table 19-1. GSMR_H Field Descriptions (Continued) Bit Name Description 25 TFL Transmit FIFO length. 0 Normal operation. The transmit FIFO is 32 bytes. 1 The Tx FIFO is 1 byte. This option is used with character-oriented protocols, such as UART, to ensure a minimum FIFO latency at the expense of performance. 26 RFW Rx FIFO width. 0 Receive FIFO is 32 bits wide for maximum performance; the Rx FIFO is 32 bytes.
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Part IV. Communications Processor Module Figure 19-3 shows GSMR_L.
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Part IV. Communications Processor Module Table 19-2. GSMR_L Field Descriptions (Continued) Bit Name Description 7 TINV DPLL Tx input invert data. Must be zero in HDLC bus mode. 0 Do not invert. 1 Invert data before sending it to the DPLL for transmission. Used to produce FM1 from FM0 and NRZI space from NRZI mark and to invert the data stream in regular NRZ mode. In T1 applications, setting TINV and TEND creates a continuously inverted HDLC data stream. 8Ð10 TPL Tx preamble length.
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Part IV. Communications Processor Module Table 19-2. GSMR_L Field Descriptions (Continued) Bit Name Description 24Ð25 DIAG Diagnostic mode. 00 Normal operation, CTS and CD are under automatic control. Data is received through RXD and transmitted through TXD. The SCC uses modem signals to enable or disable transmission and reception. These timings are shown in Section 19.3.5, ÒControlling SCC Timing with RTS, CTS, and CD.Ó 01 Local loopback mode.
PAGE 565
Part IV. Communications Processor Module 19.1.2 Protocol-SpeciÞc Mode Register (PSMR) The protocol implemented by an SCC is selected by its GSMR_L[MODE]. Each SCC has an additional protocol-speciÞc mode register (PSMR) that conÞgures it speciÞcally for the chosen protocol. The PSMR Þelds are described in the speciÞc chapters that describe each protocol. PSMRs are cleared at reset. PSMRs reside at the following addresses: 0x11A08 (PSMR1), 0x11A28 (PSMR2), 0x11A48 (PSMR3), and 0x11A68 (PSMR4). 19.1.
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Part IV. Communications Processor Module The CP can be conÞgured to begin processing a new frame/buffer without waiting the normal polling time by setting TODR[TOD] after TxBD[R] is set. Because this feature favors the speciÞed TxBD, it may affect servicing of other SCC FIFOs. Therefore, transmitting on demand should only be used when a high-priority TxBD has been prepared and enough time has passed since the last g transmission. Table 19-3 describes TODR Þelds. Table 19-3.
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Part IV. Communications Processor Module ¥ The word at offset + 0x4 (buffer pointer) points to the beginning of the buffer in memory (internal or external). Ñ For an RxBD, the value must be a multiple of four. (word-aligned) Ñ For a TxBD, this pointer can be even or odd. Shown in Figure 19-6, the format of Tx and Rx BDs is the same in each SCC mode. Only the status and control bits differ for each protocol.
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Part IV. Communications Processor Module External Memory Dual-Port RAM Tx Buffer Descriptors Status and Control SCCx TxBD Table Buffer Length Buffer Pointer Tx Buffer Rx Buffer Descriptors SCCx RxBD Table Status and Control SCCx RxBD Table Pointer Buffer Length Buffer Pointer SCCx TxBD Table Pointer Rx Buffer Figure 19-7. SCC BD and Buffer Memory Structure In all protocols, BDs can point to buffers in the internal dual-port RAM.
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Part IV. Communications Processor Module set by the core (the buffer is empty). After using a descriptor, the CPM clears E (not empty) and does not reuse a BD until it has been processed by the core. However, in continuous mode (CM), E remains set. When the CPM discovers a descriptorÕs W bit set (indicating it is the last BD in the circular BD table), it returns to the beginning of the table when it is time to move to the next buffer. 19.
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Part IV. Communications Processor Module Table 19-4. SCC Parameter RAM Map for All Protocols (Continued) 0x06 MRBLR Hword Maximum receive buffer length. DeÞnes the maximum number of bytes the MPC8260 writes to a receive buffer before it goes to the next buffer. The MPC8260 can write fewer bytes than MRBLR if a condition such as an error or end-of-frame occurs. It never writes more bytes than the MRBLR value. Therefore, user-supplied buffers should be no smaller than MRBLR.
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Part IV. Communications Processor Module 19.3.1 SCC Base Addresses The CPM maintains a section of RAM called the parameter RAM, which contains many parameters for the operation of the FCCs, SCCs, SMCs, SPI, I2C, and IDMA channels. SCC base addresses are described in Table 19-5. The exact deÞnition of the parameter RAM is contained in each protocol subsection describing a device that uses a parameter RAM.
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Part IV. Communications Processor Module Table 19-6 describes RFCRx/TFCRx Þelds. Table 19-6. RFCRx /TFCRx Field Descriptions Bits 0Ð1 2 Name Ñ GBL Description Reserved, should be cleared. Global 0 Snooping disabled. 1 Snooping enabled. 3Ð4 BO Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy, it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the beginning of the next BD. 00 Reserved 01 PowerPC little-endian.
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Part IV. Communications Processor Module Follow these steps to handle an SCC interrupt: 1. When an interrupt occurs, read SCCE to determine the interrupt sources and clear those SCCE bits (in most cases). 2. Process the TxBDs to reuse them if SCCE[TX] or SCCE[TXE] = 1. If the transmit speed is fast or the interrupt delay is long, the SCC may have sent more than one Tx buffer. Thus, it is important to check more than one TxBD during interrupt handling.
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Part IV. Communications Processor Module 19.3.5 Controlling SCC Timing with RTS, CTS, and CD When GSMR_L[DIAG] is programmed to normal operation, CD and CTS are controlled by the SCC. In the following subsections, it is assumed that GSMR_L[TCI] is zero, implying normal transmit clock operation. 19.3.5.1 Synchronous Protocols RTS is asserted when the SCC data is loaded into the Tx FIFO and a falling Tx clock occurs. At this point, the SCC starts sending data once appropriate conditions occur on CTS.
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Part IV. Communications Processor Module TCLK TXD (Output) RTS (Output) CTS (Input) First Bit of Frame Data Last Bit of Frame Data CTS Sampled Low Here NOTE: 1. GSMR_H[CTSS] = 0. CTSP is a donÕt care. TCLK TXD (Output) RTS (Output) First Bit of Frame Data Last Bit of Frame Data CTS (Input) NOTE: 1. GSMR_H[CTSS] = 1. CTSP is a donÕt care. Figure 19-10.
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Part IV. Communications Processor Module TCLK TXD (Output) RTS (Output) CTS (Input) Data Forced High First Bit of Frame Data CTS Sampled Low Here RTS Forced High CTS Sampled High Here CTS Lost Signaled in Frame BD NOTE: 1. GSMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur. TCLK TXD (Output) RTS (Output) Data Forced High First Bit of Frame Data RTS Forced High CTS (Input) CTS Lost Signaled in Frame BD NOTE: 1. GSMR_H[CTSS] = 1. CTSP=0 or no CTS lost can occur. Figure 19-11.
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Part IV. Communications Processor Module RCLK RXD (Input) CD (Input) First Bit of Frame Data CD Sampled Low Here Last Bit of Frame Data CD Sampled High Here NOTE: 1. GSMR_H[CDS] = 0. CDP=0. 2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the frame BD. 3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.
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Part IV. Communications Processor Module 19.3.6 Digital Phase-Locked Loop (DPLL) Operation Each SCC channel includes a digital phase-locked loop (DPLL) for recovering clock information from a received data stream. For applications that provide a direct clock source to the SCC, the DPLL can be bypassed by selecting 1x mode for GSMR_L[RDCR, TDCR]. If the DPLL is bypassed, only NRZ or NRZI encodings are available.
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Part IV. Communications Processor Module TENC Recovered Clock TDCR HSTCLK TEND HSTCLK 0 TCLK 1 DPLL Transmitter S 1x Mode D HSTCLK Encoded Data Q TXEN CLK SCCT Data 0 TINV 1 0 1 D S HSTCLK S Q TXD CLK 1x Mode TENC = NRZI Figure 19-14. DPLL Transmitter Block Diagram The DPLL can be driven by one of the baud rate generator outputs or an external clock, CLKx. In the block diagrams, this clock is labeled HSRCLK/HSTCLK.
PAGE 580
Part IV. Communications Processor Module Table 19-8. Preamble Requirements Decoding Method Preamble Pattern Minimum Preamble Length Required NRZI Mark All zeros 8-bit NRZI Space All ones 8-bit FM0 All ones 8-bit FM1 All zeros 8-bit Manchester 101010...10 8-bit Differential Manchester All ones 8-bit The DPLL can also be used to invert the data stream of a transfer. This feature is available in all encodings, including standard NRZ format.
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Part IV. Communications Processor Module Data 0 1 1 0 0 1 NRZ NRZI Mark NRZI Space FM0 FM1 Manchester Differential Manchester Figure 19-15. DPLL Encoding Examples If the DPLL is not needed, NRZ or NRZI codings can be selected in GSMR_L[RENC, TENC]. Coding deÞnitions are shown in Table 19-9. Table 19-9. DPLL Codings Coding Description NRZ A one is represented by a high level for the duration of the bit and a zero is represented by a low level.
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Part IV. Communications Processor Module 19.3.7 Clock Glitch Detection Clock glitches cause problems for many communications systems, and they may go undetected by the system. Systems that supply an external clock to a serial channel are often susceptible to glitches from noise, connecting or disconnecting the physical cable from the application board, or excessive ringing on a clock line.
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Part IV. Communications Processor Module 4. If an INIT TX PARAMETERS command was not issued in step 3, issue a RESTART TRANSMIT command. 5. Set GSMR_L[ENT]. Transmission begins using the TxBD pointed to by TBPTR, assuming the R bit is set. 19.3.8.2 Reset Sequence for an SCC Transmitter The following steps reinitialize an SCC transmit parameters to the reset state: 1. Clear GSMR_L[ENT]. 2. Make any modiÞcations then issue the INIT TX PARAMETERS command. 3. Set GSMR_L[ENT]. 19.3.8.
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Part IV.
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Chapter 20 SCC UART Mode 200 200 The universal asynchronous receiver transmitter (UART) protocol is commonly used to send low-speed data between devices. The term asynchronous is used because it is not necessary to send clocking information along with the data being sent. UART links are typically 38400 baud or less and are character-based. Asynchronous links are used to connect terminals with other devices.
PAGE 586
Part IV. Communications Processor Module All standards provide handshaking signals, but some systems require only three physical linesÑTx data, Rx data, and ground. Many proprietary standards have been built around the UARTÕs asynchronous character frame, some of which implement a multidrop conÞguration where multiple stations, each with a speciÞc address, can be present on a network. In multidrop mode, frames of characters are broadcast with the Þrst character acting as a destination address.
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Part IV. Communications Processor Module ¥ Frame error, noise error, break, and idle detection ¥ Transmit preamble and break sequences ¥ Freeze transmission option with low-latency stop 20.2 Normal Asynchronous Mode In normal asynchronous mode, the receive shift register receives incoming data on RXDx. Control bits in the UART mode register (PSMR) deÞne the length and format of the UART character. Bits are received in the following order: 1. 2. 3. 4. 5.
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Part IV. Communications Processor Module receive shift register are transferred to the receive FIFO before proceeding to the receive buffer. The CPM ßags UART events, including reception errors, in SCCE and the RxBD status and control Þelds. GSMR_H[RFW] must be set for an 8-bit receive FIFO. The synchronous UART transmit shift register sends outgoing data on TXDx. Data is then clocked synchronously with the transmit clock, which can have an internal or external source. 20.
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Part IV. Communications Processor Module Table 20-1. UART-Specific SCC Parameter RAM Memory Map (Continued) 0x4E TOSEQ 0x50 0x52 CHARACTER1 Hword Control character 1Ð8. These characters deÞne the Rx control characters on which interrupts can be generated. CHARACTER2 Hword 0x54 CHARACTER3 Hword 0x56 CHARACTER4 Hword 0x58 CHARACTER5 Hword 0x5A CHARACTER6 Hword 0x5C CHARACTER7 Hword 0x5E CHARACTER8 Hword 0x60 RCCM Hword Receive control character mask.
PAGE 590
Part IV. Communications Processor Module handling input data, a terminal driver may wait for an end-of-line character or an idle timeout rather than be interrupted when each character is received. Conversely, ASCII Þles can be sent as messages ending with an end-of-line character. When receiving messages, up to eight control characters can be conÞgured to mark the end of a message or generate a maskable interrupt without being stored in the buffer.
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Part IV. Communications Processor Module Receive commands are described in Table 20-3. Table 20-3. Receive Commands Command Description ENTER HUNT Forces the receiver to close the RxBD in use and enter hunt mode. After a hardware or software reset, once an SCC is enabled in the GSMR, the receiver is automatically enabled and uses the Þrst BD in the RxBD table. If a message is in progress, the receiver continues receiving in the next BD.
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Part IV. Communications Processor Module 1 2 3 4 +V Tx Rx Tx Rx Tx Rx Tx Rx R Master Tx Rx Slave 1 Tx Rx Slave 2 Tx Rx Slave 3 Tx +V Rx R UADDR1 PAODR UADDR2 Choose wired-or operation in the port A open-drain register to allow multiple transmit pins to be directly connected Two 8-bit addresses can be automatically recognized in either configuration Figure 20-2. Two UART Multidrop Configurations 20.
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Part IV. Communications Processor Module Offset1 0 1 0x50 E R Ñ CHARACTER1 0x52 E R Ñ CHARACTER2 ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ 0x5E E R Ñ CHARACTER8 0x60 1 1 Ñ RCCM 2 0x62 1 3 4 5 6 7 8 9 10 11 Ñ 12 13 14 15 RCCR From SCCx base address Figure 20-3. Control Character Table Table 20-4 describes the data structure used in control character recognition. Table 20-4.
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Part IV. Communications Processor Module 20.10 Hunt Mode (Receiver) A UART receiver in hunt mode remains deactivated until an idle or address character is recognized, depending on PSMR[UM]. A receiver is forced into hunt mode by issuing an ENTER HUNT MODE command. The receiver aborts any message in progress when ENTER HUNT MODE is issued. When the message is Þnished, the receiver is reenabled by detecting the idle line (one idle character) or by the address bit of the next message, depending on PSMR[UM].
PAGE 595
Part IV. Communications Processor Module Table 20-5. TOSEQ Field Descriptions (Continued) Bit Name Description 5Ð6 Ñ Reserved, should be cleared. 7 A Address. Setting this bit indicates an address character for multidrop mode. 8Ð15 CHARSEND Character send. Contains the character to be sent. Any 5- to 8-bit character value can be sent in accordance with the UART conÞguration. The character should be placed in the lsbs of CHARSEND. This value can be changed only while REA = 0. 20.
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Part IV. Communications Processor Module Table 20-6 describes DSR Þelds. Table 20-6. DSR Fields Descriptions Bit Name Description 0 Ñ 0b0 1Ð4 FSB Fractional stop bits. For 16´ oversampling: 1111 Last transmitted stop bit 16/16. Default value after reset. 1110 Last transmitted stop bit 15/16. É 1000 Last transmitted stop bit 9/16. 0xxx Invalid. Do not use. For 32´ oversampling: 1111 Last transmitted stop bit 32/32. Default value after reset. 1110 Last transmitted stop bit 31/32.
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Part IV. Communications Processor Module Reception errors are described in Table 20-8. Table 20-8. Reception Errors Error Description Overrun Occurs when the channel overwrites the previous character in the Rx FIFO with a new character, losing the previous character. The channel then writes the new character to the buffer, closes it, sets RxBD[OV], and generates an RX interrupt if not masked. In automatic multidrop mode, the receiver enters hunt mode immediately.
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Part IV. Communications Processor Module Bit 0 1 Field FLC SL 2 3 CL 4 5 UM 6 7 8 FRZ RZS SYN DRT Reset 0 R/W R/W Addr 9 10 11 Ñ PEN 12 13 14 RPM 15 TPM 0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4) Figure 20-6. Protocol-Specific Mode Register for UART (PSMR) Table 20-9 describes PSMR UART Þelds. Table 20-9. PSMR UART Field Descriptions Bit Name Description 0 FLC Flow control. 0 Normal operation.
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Part IV. Communications Processor Module Table 20-9. PSMR UART Field Descriptions (Continued) Bit Name Description 7 RZS Receive zero stop bits. 0 The receiver operates normally, but at least one stop bit is needed between characters. A framing error is issued if a stop bit is missing. Break status is set if an all-zero character is received with a zero stop bit. 1 ConÞgures the receiver to receive data without stop bits. Useful in V.
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Part IV. Communications Processor Module ¥ An ENTER HUNT MODE or CLOSE RXBD command is issued. ¥ An address character is received in multidrop mode. The address character is written to the next buffer for a software comparison. Figure 20-7 shows an example of how RxBDs are used in receiving. E Status Rx BD 0 ID MRBLR = 8 Bytes for this SCC Buffer 0 Byte 1 0 Length 0008 Pointer Byte 2 Buffer Full 32-Bit Buffer Pointer 8 Bytes etc.
PAGE 601
Part IV. Communications Processor Module Figure 20-8 shows the SCC UART RxBD. Offset + 0 0 1 2 3 4 5 6 E Ñ W I C A CM 7 8 9 10 11 12 13 14 15 ID AM Ñ BR FR PR Ñ OV CD Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 20-8. SCC UART Receive Buffer Descriptor (RxBD) Table 20-10 describes RxBD status and control Þelds. Table 20-10. SCC UART RxBD Status and Control Field Descriptions Bits Name Description 0 E Empty.
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Part IV. Communications Processor Module Table 20-10. SCC UART RxBD Status and Control Field Descriptions (Continued) Bits Name Description 10 BR Break received. Set when a break sequence is received as data is being received into this buffer. 11 FR Framing error. Set when a character with a framing error (a character without a stop bit) is received and located in the last byte of this buffer. A new Rx buffer is used to receive subsequent data. 12 PR Parity error.
PAGE 603
Part IV. Communications Processor Module Table 20-11. SCC UART TxBD Status and Control Field Descriptions (Continued) Bit Name Description 3 I Interrupt. 0 No interrupt is generated after this buffer is processed. 1 SCCE[TX] is set after this buffer is processed by the CPM, which can cause an interrupt. 4 CR Clear-to-send report. 0 The next buffer is sent with no delay (assuming it is ready), but if a CTS lost condition occurs, TxBD[CT] may not be set in the correct TxBD or may not be set at all.
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Part IV. Communications Processor Module Characters Received by UART 10 Characters Time RXD Line Idle Break Line Idle CD UART SCCE Events CD IDL RX CCR IDL RX IDL BRKS BRKE IDL CD Notes: 1. The first RX event assumes Rx buffers are 6 bytes each. 2. The second IDL event occurs after an all-ones character is received. 3. The second RX event position is programmable based on the MAX_IDL value. 4. The BRKS event occurs after the first break character is received. 5.
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Part IV. Communications Processor Module Table 20-12 describes SCCE Þelds for UART mode. Table 20-12. SCCE/SCCM Field Descriptions for UART Mode Bit Name Description 0Ð2 Ñ Reserved, should be cleared. 3 GLR Glitch on receive. Set when the SCC encounters an Rx clock glitch. 4 GLT Glitch on transmit. Set when the SCC encounters a Tx clock glitch. 5 Ñ Reserved, should be cleared. 6 AB Autobaud. Set when an autobaud lock is detected.
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Part IV. Communications Processor Module Table 20-13 describes UART SCCS Þelds. Table 20-13. UART SCCS Field Descriptions Bits Name Description 0Ð6 Ñ Reserved, should be cleared. 7 ID Idle status. Set when RXD has been a logic one for at least a full character time. 0 The line is not idle. 1 The line is idle. 20.21 SCC UART Programming Example The following initialization sequence is for the 9,600 baud, 8 data bits, no parity, and stop bit of an SCC in UART mode assuming a 66-MHz system frequency.
PAGE 607
Part IV. Communications Processor Module 15. Write CHARACTER1Ð8 with 0x8000. They are not used. 16. Write RCCM with 0xC0FF. It is not used. 17. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to the RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. 18. Initialize the TxBD. Assume the buffer is at 0x0000_2000 in main memory and contains sixteen 8-bit characters.
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Part IV. Communications Processor Module Table 20-14. UART Control Characters for S-Records Example Character Description Line Feed Both the E and R bits should be cleared. When an end-of-line character is received, the current buffer is closed and made available to the core for processing. This buffer contains an entire S record that the processor can now check and copy to memory or disk as required. XOFF E should be cleared; R should be set.
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Chapter 21 SCC HDLC Mode 210 210 High-level data link control (HDLC) is one of the most common protocols in the data link layer, layer 2 of the OSI model. Many other common layer 2 protocols, such as SDLC, SS#7, AppleTalk, LAPB, and LAPD, are based on HDLC and its framing structure in particular. Figure 21-1 shows the HDLC framing structure. HDLC uses a zero insertion/deletion process (bit-stufÞng) to ensure that a data bit pattern matching the delimiter ßag does not occur in a Þeld between ßags.
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Part IV. Communications Processor Module 21.
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Part IV. Communications Processor Module insert a high-priority frame without aborting the current oneÑa graceful-stop-complete event is generated in SCCE[GRA] when the current frame is Þnished. See Section 21.6, ÒSCC HDLC Commands.Ó 21.3 SCC HDLC Channel Frame Reception The HDLC receiver is designed to work with little or no core intervention to perform address recognition, CRC checking, and maximum frame length checking. Received frames can be used to implement any HDLC-based protocol.
PAGE 612
Part IV. Communications Processor Module Table 21-1. HDLC-Specific SCC Parameter RAM Memory Map Offset 1 Name Width Description 0x30 Ñ Word Reserved 0x34 C_MASK Word CRC mask. For the 16-bit CRC-CCITT, initialize with 0x0000_F0B8. For 32-bit CRCCCITT, initialize with 0xDEBB_20E3. 0x38 C_PRES Word CRC preset. For the 16-bit CRC-CCITT, initialize with 0x0000_FFFF. For 32-bit CRCCCITT, initialize with 0xFFFF_FFFF.
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Part IV. Communications Processor Module Figure 21-2 shows 16- and 8-bit address recognition. 16-Bit Address Recognition Flag 0x7E Address 0x68 Address 0xAA HMASK HADDR1 HADDR2 HADDR3 HADDR4 8-Bit Address Recognition Control 0x44 etc. Flag 0x7E 0xFFFF 0xAA68 0xFFFF 0xAA68 0xAA68 Address 0x55 HMASK HADDR1 HADDR2 HADDR3 HADDR4 Recognizes one 16-bit address (HADDR1) and the 16-bit broadcast address (HADDR2) Control 0x44 etc.
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Part IV. Communications Processor Module Receive commands are described in Table 21-3. Table 21-3. Receive Commands Command ENTER HUNT MODE Description After a hardware or software reset, once an SCC is enabled in the GSMR, the receiver is automatically enabled and uses the Þrst BD in the RxBD table. While the SCC is looking for the beginning of a frame, that SCC is in hunt mode.
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Part IV. Communications Processor Module Table 21-5. Receive Errors (Continued) Error Description Abort Sequence Occurs when seven or more consecutive ones are received. When this occurs while receiving a frame, the channel closes the buffer, sets RxBD[AB] and generates a maskable RXF interrupt. The channel also increments the abort sequence counter ABTSC. The CRC and nonoctet error status conditions are not checked on aborted frames. The receiver then enters hunt mode.
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Part IV. Communications Processor Module Table 21-6. PSMR HDLC Field Descriptions (Continued) Bits Name Description 6 RTE Retransmit enable. 0 No retransmission. 1 Automatic frame retransmission is enabled. Particularly useful in the HDLC bus protocol and ISDN applications where multiple HDLC controllers can collide. Note that retransmission occurs only if a lost CTS occurs on the Þrst or second buffer of the frame. 7 Ñ Reserved, should be cleared. 8 FSE Flag sharing enable.
PAGE 617
Part IV. Communications Processor Module Table 21-7 describes HDLC RxBD status and control Þelds. Table 21-7. SCC HDLC RxBD Status and Control Field Descriptions Bits Name Description 0 E Empty. 0 The buffer is full or reception stopped because of an error. The core can read or write to any Þelds of this RxBD. The CP does not use this BD while E = 0. 1 The buffer is not full. The CP controls the BD and buffer. The core should not update the BD. 1 Ñ Reserved, should be cleared.
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Part IV. Communications Processor Module last buffer of a frame contains the total number of frame bytes, including the 2 or 4 bytes for CRC. Figure 21-5 shows an example of how RxBDs are used in receiving.
PAGE 619
Part IV. Communications Processor Module 21.10 SCC HDLC Transmit Buffer Descriptor (TxBD) The CP uses the TxBD, shown in Figure 21-6, to conÞrm transmissions and indicate error conditions. Offset + 0 0 1 2 3 4 5 6 7 R Ñ W I L TC CM 8 9 10 11 12 13 Ñ Offset + 2 Data Length Offset + 4 Tx Buffer Pointer 14 15 UN CT Offset + 6 Figure 21-6. SCC HDLC Transmit Buffer Descriptor (TxBD) Table 21-8 describes HDLC TxBD status and control Þelds. Table 21-8.
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Part IV. Communications Processor Module The data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer Descriptors (BDs).Ó 21.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) The SCC event register (SCCE) is used as the HDLC event register to report events recognized by the HDLC channel and to generate interrupts. When an event is recognized, the SCC sets the corresponding SCCE bit.
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Part IV. Communications Processor Module Table 21-9. SCCE/SCCM Field Descriptions (Continued) Bits Name Description 12 RXF Rx frame. Set when the number of receive frames speciÞed in RFTHR are received on the HDLC channel. It is set no sooner than two clocks after the last bit of the closing ßag is received. This event is not maskable via the RxBD[I] bit. 13 BSY Busy condition. Indicates a frame arrived but was discarded due to a lack of buffers. 14 TXB Transmit buffer.
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Part IV. Communications Processor Module 21.12 SCC HDLC Status Register (SCCS) The SCC status register (SCCS), shown in Figure 21-9, permits monitoring of real-time status conditions on RXD. The real-time status of CTS and CD are part of the port C parallel I/O. Bit Field 0 1 2 3 4 Ñ Reset 5 6 7 FG CS ID 0000_0000 R/W R Addr 0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4) Figure 21-9. SCC HDLC Status Register (SCCS) Table 21-10 describes HDLC SCCS Þelds. Table 21-10.
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Part IV. Communications Processor Module 21.13.1 SCC HDLC Programming Example #1 The following initialization sequence is for an SCC HDLC channel with an external clock. SCC2 is used with RTS2, CTS2, and CD2 active; CLK3 is used for both the HDLC receiver and transmitter. 1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear PDIRD[28] and PSORD[27,28]. 2. ConÞgure ports C and D pins to enable RTS2, CTS2 and CD2.
PAGE 624
Part IV. Communications Processor Module 19. Initialize the TxBD. Assume the Tx data frame is at 0x0000_2000 in main memory and contains Þve 8-bit characters. TxBD[Status and Control] = 0xBC00, TxBD[Data Length] = 0x0005, and TxBD[Buffer Pointer] = 0x0000_2000. 20. Write 0xFFFF to SCCE to clear any previous events. 21. Write 0x001A to SCCM to enable TXE, RXF, and TXB interrupts. 22. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a system interrupt.
PAGE 625
Part IV. Communications Processor Module 21.14 HDLC Bus Mode with Collision Detection The HDLC controller includes an option for hardware collision detection and retransmission on an open-drain connected HDLC bus, referred to as HDLC bus mode. Most HDLC-based controllers provide only point-to-point communications; however, the HDLC bus enhancement allows implementation of an HDLC-based LAN and other pointto-multipoint conÞgurations. The HDLC bus is based on techniques used in the CCITT ISDN I.
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Part IV. Communications Processor Module Figure 21-10 shows the most common HDLC bus LAN conÞguration, a multimaster conÞguration. A station can transfer data to or from any other LAN station. Transmissions are half-duplex, which is typical in LANs. +5V R HDLC Bus LAN RXD TXD CTS RXD TXD CTS RXD TXD CTS HDLC Bus Controller A HDLC Bus Controller B HDLC Bus Controller C RCLK/TCLK RCLK/TCLK RCLK/TCLK Clock Master Master Master NOTES: 1. Transceivers may be used to extend the LAN size. 2.
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Part IV. Communications Processor Module +5V HDLC Bus LAN RXD RXD TXD TXD HDLC Controller A RCLK CTS HDLC Bus Controller B TCLK RCLK TCLK R RXD TXD CTS HDLC Bus Controller C RCLK TCLK Clock1 Clock2 Master Slave Slave NOTES: 1. Transceivers may be used to extend the LAN size. 2. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port. 3. Clock1 is the master RCLK and the slave TCLK. 4. Clock2 is the master TCLK and the slave RCLK. Figure 21-11.
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Part IV. Communications Processor Module transmission stops after that bit and waits for an idle line before attempting retransmission. Since the HDLC bus uses a wired-OR scheme, a transmitted zero has priority over a transmitted 1. Figure 21-12 shows how CTS is used to detect collisions. TCLK TXD (Output) CTS (Input) CTS sampled at halfway point. Collision detected when TXD=1, but CTS=0. Figure 21-12.
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Part IV. Communications Processor Module TCLK TXD (Output) CTS (Input) CTS sampled at three quarter point. Collision detected when TXD=1, but CTS=0. Figure 21-13. Nonsymmetrical Tx Clock Duty Cycle for Increased Performance 21.14.4 Delayed RTS Mode Figure 21-14 shows local HDLC bus controllers using a standard transmission line and a local bus.
PAGE 630
Part IV. Communications Processor Module Collision TCLK TXD 1st Bit 2nd Bit 3rd Bit CTS RTS RTS active for only 2 bit times Figure 21-15. Delayed RTS Mode 21.14.5 Using the Time-Slot Assigner (TSA) HDLC bus controllers can be used with a time-division multiplexed transmission line and a local bus, as shown in Figure 21-16. Local stations use time slots to communicate over the TDM transmission line; stations that share a time slot use the HDLC bus protocol to control access to the local bus.
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Part IV. Communications Processor Module 21.14.6 HDLC Bus Protocol Programming The HDLC bus on the MPC8260 is implemented using the SCC in HDLC mode with busspeciÞc options selected in the PSMR and GSMR, as outlined below. See also Section 21.5, ÒProgramming the SCC in HDLC Mode.Ó 21.14.6.
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Part IV.
PAGE 633
Chapter 22 SCC BISYNC Mode 220 220 The byte-oriented BISYNC protocol was developed by IBM for use in networking products. There are three classes of BISYNC framesÑtransparent, nontransparent with header, and nontransparent without header, shown in Figure 22-1. The transparent frame type in BISYNC is not related to transparent mode, discussed in Chapter 23, ÒSCC Transparent Mode.Ó Transparent BISYNC mode allows full binary data to be sent with any possible character pattern.
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Part IV. Communications Processor Module transmission, an underrun must not occur between the DLE and its following character. This failure mode cannot occur with the MPC8260. An SCC can be conÞgured as a BISYNC controller to handle basic BISYNC protocol in normal and transparent modes. The controller can work with the time-slot assigner (TSA) or nonmultiplexed serial interface (NMSI).
PAGE 635
Part IV. Communications Processor Module If no additional buffers have been sent to the controller for transmission, an in-frame underrun is detected and the controller starts sending syncs or idles. If the controller is in transparent mode, it sends DLE-sync pairs. Characters are included in the block check sequence (BCS) calculation on a per-buffer basis.
PAGE 636
Part IV. Communications Processor Module Table 22-1. SCC BISYNC Parameter RAM Memory Map Offset 1 Name Width Description 0x30 Ñ Word Reserved 0x34 CRCC Word CRC constant temp value. 0x38 PRCRC Hword 0x3A PTCRC Hword Preset receiver/transmitter CRC16/LRC. These values should be preset to all ones or zeros, depending on the BCS used. 0x3C PAREC Hword Receive parity error counter.
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Part IV. Communications Processor Module 22.5 SCC BISYNC Commands Transmit and receive commands are issued to the CP command register (CPCR). Transmit commands are described in Table 22-2. Table 22-2. Transmit Commands Command STOP TRANSMIT GRACEFUL STOP TRANSMIT RESTART TRANSMIT INIT TX PARAMETERS Description After hardware or software is reset and the channel is enabled in the GSMR, the channel is in transmit enable mode and starts polling the Þrst BD every 64 transmit clocks.
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Part IV. Communications Processor Module 22.6 SCC BISYNC Control Character Recognition The BISYNC controller recognizes special control characters that customize the protocol implemented by the BISYNC controller and aid its operation in a DMA-oriented environment. They are used for receive buffers longer than one byte. In single-byte buffers, each byte can be easily inspected so control character recognition should be disabled.
PAGE 639
Part IV. Communications Processor Module Table 22-4 describes control character table and RCCM Þelds. Table 22-4. Control Character Table and RCCM Field Descriptions Offset Bit Name Description 0x42Ð 0 0x50 E End of table. 0 This entry is valid. The lower eight bits are checked against the incoming character. In tables with eight control characters, E should be zero in all eight positions. 1 The entry is not valid. No other valid entries exist beyond this entry. 1 B BCS expected.
PAGE 640
Part IV. Communications Processor Module Table 22-5 describes BSYNC Þelds. Table 22-5. BSYNC Field Descriptions Bits Name Description 0 V Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character is discarded. 1 DIS Disable BSYNC stripping 0 Normal mode. 1 BSYNC stripping disabled (BISYNC transparent mode only). 2Ð7 Ñ All zeroes 8Ð15 SYNC SYNC character 22.
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Part IV. Communications Processor Module Table 22-6 describes BDLE Þelds. Table 22-6. BDLE Field Descriptions Bits Name Description 0 V Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character is discarded. 1 DIS Disable DLE stripping 0 Normal mode. 1 DLE stripping disabled. When DIS is enabled in BDLE and on BSYNC the following cases occur: DLE-DLE sequence. Both characters are written to the memory. The BCS is calculated only on the second DLE.
PAGE 642
Part IV. Communications Processor Module Table 22-8 describes transmit errors. Table 22-8. Transmit Errors Error Description Transmitter Underrun The channel stops sending the buffer, closes it, sets TxBD[UN], and generates aTXE interrupt if it is enabled. The channel resumes transmission after a RESTART TRANSMIT command is received. Underrun cannot occur between frames or during a DLEÐXXX pair in transparent mode.
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Part IV. Communications Processor Module Table 22-10 describes PSMR Þelds. Table 22-10. PSMR Field Descriptions Bits Name Description 0Ð3 NOS Minimum number of SYN1ÐSYN2 pairs (deÞned in DSR) sent between or before messages.If NOS = 0000, one pair is sent. If NOS = 1111, 16 pairs are sent. The entire pair is always sent, regardless of how GSMR[SYNL) is set. NOS can be modiÞed on-the-ßy. 4Ð5 CRC CRC selection. x0 Reserved. 01 CRC16 (BISYNC). X16 + X15 + X2 + 1.
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Part IV. Communications Processor Module Table 22-10. PSMR Field Descriptions (Continued) Bits Name Description 12Ð13 RPM Receiver parity mode. Selects the type of parity check that the receiver performs. RPM can be modiÞed on-the-ßy and is ignored unless CRC = 11 (LRC). Receive parity errors cannot be disabled but can be ignored. 00 Odd parity. The transmitter counts ones in the data word. If the sum is not odd, the parity bit is set to ensure an odd number. An even sum indicates a transmission error.
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Part IV. Communications Processor Module Table 22-11. SCC BISYNC RxBD Status and Control Field Descriptions (Continued) Bits Name Description 1 Ñ Reserved, should be cleared. 2 W Wrap (last BD in table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that RBASE points to. The number of BDs in this table is determined by the W bit and by overall space constraints of the dual-port RAM. 3 I Interrupt.
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Part IV. Communications Processor Module 22.13 SCC BISYNC Transmit BD (TxBD) The CP arranges data to be sent on an SCC channel in buffers referenced by the channel TxBD table. The CP uses BDs to conÞrm transmission or indicate errors so the core knows buffers have been serviced. The user conÞgures status and control bits before transmission, but the CP sets them after the buffer is sent.
PAGE 647
Part IV. Communications Processor Module Table 22-12. SCC BISYNC TxBD Status and Control Field Descriptions (Continued) Bits Name Description 8 TD Transmit DLE. 0 No automatic DLE transmission can occur before the data buffer. 1 The transmitter sends a DLE character before sending the buffer, which saves writing the Þrst DLE to a separate buffer in transparent mode. See TR for information on control characters. 9 TR Transparent mode.
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Part IV. Communications Processor Module Table 22-13 describes SCCE and SCCM Þelds. Table 22-13. SCCE/SCCM Field Descriptions Bits Name Description 0Ð2 Ñ Reserved, should be cleared. 3 GLR Glitch on receive. Set when the SCC Þnds an Rx clock glitch. 4 GLT Glitch on transmit. Set when the SCC Þnds a Tx clock glitch. 5 DCC DPLL CS changed. Set when carrier sense status generated by the DPLL changes. Real-time status can be found in SCCS. This is not the CD status discussed elsewhere.
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Part IV. Communications Processor Module Table 22-14 describes SCCS Þelds. Table 22-14. SCCS Field Descriptions Bit Name Description 0Ð5 Ñ Reserved, should be cleared. 6 CS Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL. 0 The DPLL does not sense a carrier. 1 The DPLL senses a carrier. 7 Ñ Reserved, should be cleared. 22.16 Programming the SCC BISYNC Controller Software has two ways to handle data received by the BISYNC controller.
PAGE 650
Part IV. Communications Processor Module Table 22-15. Control Characters Control Characters E B H ETX 0 1 1 ITB 0 1 0 ETB 0 1 1 ENQ 0 0 0 Next entry 0 X X After ETX, a BCS is expected; then the buffer should be closed. Hunt mode should be entered when a line turnaround occurs. ENQ characters are used to stop sending a block and to designate the end of the block for a receiver, but no CRC is expected.
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Part IV. Communications Processor Module 13. Write BSYNC with 0x8033, assuming a SYNC value of 0x33. 14. Write DSR with 0x3333. 15. Write BDLE with 0x8055, assuming a DLE value of 0x55. 16. Write CHARACTER1 with 0x6077, assuming ETX = 0x77. 17. Write CHARACTER2Ð8 with 0x8000. They are not used. 18. Write RCCM with 0xE0FF. It is not used. 19. Initialize the RxBD and assume the data buffer is at 0x00001000 in main memory.
PAGE 652
Part IV.
PAGE 653
Chapter 23 SCC Transparent Mode 230 230 Transparent mode (also called totally transparent or promiscuous mode) provides a clear channel on which the SCC can send or receive serial data without bit-level manipulation. Software implements protocols run over transparent mode. An SCC in transparent mode functions as a high-speed serial-to-parallel and parallel-to-serial converter.
PAGE 654
Part IV. Communications Processor Module ¥ ¥ Another protocol can be performed on the other half of the SCC MC68360-compatible SYNC options 23.2 SCC Transparent Channel Frame Transmission Process The transparent transmitter is designed to work almost no intervention from the core. When the core enables the SCC transmitter in transparent mode, it starts sending idles, which are logic high or encoded ones, as programmed in GSMR_L[TEND]. The SCC polls the Þrst BD in the TxBD table.
PAGE 655
Part IV. Communications Processor Module After a buffer is full, the SCC clears RxBD[E] and generates a maskable interrupt if RxBD[I] is set. It moves to the next RxBD in the table and begins moving data to its buffer. If the next buffer is not available, SCCE[BSY] signiÞes a busy signal that can generate a maskable interrupt. The receiver reverts to hunt mode when an ENTER HUNT MODE command or an error is received.
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Part IV. Communications Processor Module Note that the transparent controller does not automatically send the synchronization pattern; therefore, the synchronization pattern must be included in the transmit buffer. 23.4.1.2 External Synchronization Signals If GSMR_H[SYNL] is 0b00, the transmitter uses CTS and the receiver uses CD to begin the sequence. These signals share two optionsÑpulsing and sampling.
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Part IV. Communications Processor Module MPC8260 (A) MPC8260 (B) TXD RXD RTS CD CLKx BRGOx RXD TXD CD RTS CLKx BRGOx BRGOx (Output is CLKx Input) TXD (Output is RXD Input) RTS (Output is CD Input) First Bit of Frame Data Last Bit of Frame Data or CRC TxBD[L] = 1 Causes Negation of RTS CD Lost Condition Terminates Reception of Frame Notes: 1. Each MPC8260 generates its own transmit clocks.
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Part IV. Communications Processor Module Note that when using the TSA, a newly-enabled transmitter sends from 10 to 15 frames of idles before sending the actual transparent data due to startup requirements of the TDM. Therefore, when loopback testing through the TDM, expect to receive several bytes of 0xFF before the actual data. 23.4.2.1 Inline Synchronization Pattern The receiver can be programmed to begin receiving data into the receive buffers only after a speciÞed data pattern arrives.
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Part IV. Communications Processor Module Table 23-2. SCC Transparent Parameter RAM Memory Map Offset1 Name Width Description 0x 30 CRC_P Long CRC preset for totally transparent. For the 16-bit CRC-CCITT, initialize with 0x0000_FFFF. For the 32-bit CRC-CCITT, initialize with 0xFFFF_FFFF and for the CRC-16, initialize with ones (0x0000_FFFF) or zeros (0x0000_0000). 0x 34 CRC_C Long CRC constant for totally transparent receiver. For the 16-bit CRC-CCITT, initialize with 0x0000_F0B8.
PAGE 660
Part IV. Communications Processor Module Table 23-4 describes receive commands. Table 23-4. Receive Commands Command ENTER HUNT MODE Description After hardware or software is reset and the channel is enabled, the channel is in receive enable mode and uses the Þrst BD in the table. ENTER HUNT MODE forces the transparent receiver to the current frame and enter hunt mode where the transparent controller waits for the synchronization sequence. After receiving the command, the current buffer is closed.
PAGE 661
Part IV. Communications Processor Module 23.9 Transparent Mode and the PSMR The protocol-speciÞc mode register (PSMR) is not used by the transparent controller because all transparent mode selections are made in the GSMR. If only half of an SCC (transmitter or receiver) is running the transparent protocol, the other half (receiver or transmitter) can support another protocol. In such a case, use the PSMR for the nontransparent protocol. 23.
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Part IV. Communications Processor Module Table 23-7. SCC Transparent RxBD Status and Control Field Descriptions (Continued) Bits Name Description 3 I Interrupt. 0 No interrupt is generated after this buffer is used. 1 When this buffer is closed by the transparent controller, the SCCE[RXB] is set. SCCE[RXB] can cause an interrupt if it is enabled. 4 L Last in frame.
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Part IV. Communications Processor Module Offset + 0 0 1 2 3 4 5 6 7 R Ñ W I L TC CM 8 9 10 11 12 13 Ñ Offset + 2 Data Length Offset + 4 Tx Buffer Pointer 14 15 UN CT Offset + 6 Figure 23-3. SCC Transparent Transmit Buffer Descriptor (TxBD) Table 23-8 describes SCC Transparent TxBD status and control Þelds. Table 23-8. SCC Transparent TxBD Status and Control Field Descriptions Bit Name Description 0 R Ready. 0 The buffer is not ready for transmission.
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Part IV. Communications Processor Module Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer Descriptors (BDs).Ó Although it is never modiÞed by the CP, data length should be greater than zero. The buffer pointer can be even or odd and can reside in internal or external memory. 23.
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Part IV. Communications Processor Module Table 23-9. SCCE/SCCM Field Descriptions (Continued) Bit Name Description 13 BSY Busy condition. Set when a byte or word is received and discarded due to a lack of buffers. The receiver resumes reception after it gets an ENTER HUNT MODE command. 14 TXB Tx buffer. Set no sooner than when the last bit of the last byte of the buffer begins transmission, assuming L is set in the TxBD. If it is not, TXB is set when the last byte is written to the transmit FIFO.
PAGE 666
Part IV. Communications Processor Module 1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear PDIRD[28] and PSORD[27,28]. 2. ConÞgure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26], PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and PSORD[26]. 3. ConÞgure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear PDIRC[29] and PSORC[29]. 4. Connect CLK3 to SCC2 using the CPM mux. Program CMXSCR[R2CS] and CMXSCR[T2CS] to 0b110. 5.
PAGE 667
Part IV. Communications Processor Module Note that after 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the Rx buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MOTOROLA Chapter 23.
PAGE 668
Part IV.
PAGE 669
Chapter 24 SCC Ethernet Mode 240 240 The Ethernet IEEE 802.3 protocol is a widely used LAN protocol based on the carrier sense multiple access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3 protocols are similar and can coexist on the same LAN, both are referred to as Ethernet in this manual, unless otherwise noted. Figure 24-1 shows Ethernet and IEEE 802.3 frame structure.
PAGE 670
Part IV. Communications Processor Module a random period of time, called a backoff, before trying to retransmit. Once the backoff time expires, the station waits for silence on the LAN before retransmitting, which is called a retry. If the frame cannot be sent within 15 retries, an error occurs 10-Mbps Ethernet transmits at 0.8 µs per byte. The preamble plus start frame delimiter is sent in 6.4 µs. The minimum 10-Mbps Ethernet interframe gap is 9.6 µs and the slot time is 52 µs. 24.
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Part IV. Communications Processor Module 24.2 Features The following list summarizes the main features of the SCC in Ethernet mode: ¥ Performs MAC layer functions of Ethernet and IEEE 802.
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Part IV. Communications Processor Module Ñ Number of retries per frame Ñ Deferred frame indication ¥ Ñ Late collision Receiver network management and diagnostics Ñ CRC error indication Ñ Nonoctet alignment error Ñ Frame too short Ñ Frame too long ¥ ¥ Ñ Overrun Ñ Busy (out of buffers) Error counters Ñ Discarded frames (out of buffers or overrun occurred) Ñ CRC errors Ñ Alignment errors Internal and external loopback mode 24.
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Part IV.
PAGE 674
Part IV. Communications Processor Module The Ethernet controller stores the Þrst 5 to 8 bytes of the transmit frame in dual-port RAM so they need not be retrieved from system memory in case of a collision. This improves bus usage and latency when the backoff timer output requires an immediate retransmission. If a collision occurs during frame transmission, the controller returns to the Þrst buffer for a retransmission. The only restriction is that the Þrst buffer must contain at least 9 bytes.
PAGE 675
Part IV. Communications Processor Module address recognition on the frame. The receiver can receive physical (individual), group (multicast), and broadcast addresses. Ethernet receive frame data is not written to memory until the internal address recognition process completes, which improves bus usage with frames not addressed to this station. If a match is found, the Ethernet controller fetches the next RxBD and, if it is empty, starts transferring the incoming frame to the RxBD associated data buffer.
PAGE 676
Part IV. Communications Processor Module 24.7 SCC Ethernet Parameter RAM For Ethernet mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in Table 24-1. Table 24-1. SCC Ethernet Parameter RAM Memory Map Offset 1 Name Width Description 0x30 C_PRES Word Preset CRC. For the 32-bit CRC-CCITT, initialize to 0xFFFFFFFF. 0x34 C_MASK Word Constant mask for CRC. For the 32-bit CRC-CCITT, initialized to 0xDEBB20E3.
PAGE 677
Part IV. Communications Processor Module Table 24-1. SCC Ethernet Parameter RAM Memory Map (Continued) Offset 1 Name Width Description 0x54 MAX_B Hword Maximum BD byte count. 0x58 GADDR1 0x5A GADDR2 0x5C GADDR3 Hword Group address Þlter 1Ð4. Used in the hash table function of the group addressing mode. Write zeros to these values after reset and before the Ethernet channel is enabled to disable all group hash address recognition functions.
PAGE 678
Part IV. Communications Processor Module Table 24-1. SCC Ethernet Parameter RAM Memory Map (Continued) Offset 1 Name 0x9E TADDR_H 0x A0 TADDR_M 0x A2 TADDR_L 1From Width Description Hword Allows addition and deletion of addresses from individual and group hash tables. After placing an address in TADDR, issue a SET GROUP ADDRESS command. TADDR_L (temp address low) is the least-signiÞcant half word and TADDR_H (temp address high) is the most-signiÞcant half word. SCC base address. See Section 19.
PAGE 679
Part IV. Communications Processor Module Table 24-3 describes receive commands. Table 24-3. Receive Commands Command Description ENTER HUNT After hardware or software is reset and the channel is enabled in GSMR_L, the channel is in receive enable mode and uses the Þrst BD in the table. The receiver then enters hunt mode, waiting for an incoming frame.
PAGE 680
Part IV.
PAGE 681
Part IV. Communications Processor Module If the external CAM stores addresses that should be rejected rather than accepted, the use of REJECT by the CAM should be logically inverted. 24.11 Hash Table Algorithm Individual and group hash Þltering operate using certain processes. The Ethernet controller maps any 48-bit address into one of 64 bins, each represented by a bit stored in GADDRx or IADDRx.
PAGE 682
Part IV. Communications Processor Module If a collision occurs while a frame is being received, reception stops. This error is reported only in the BD if the length of the frame exceeds MINFLR or if PSMR[RSH] = 1. 24.14 Internal and External Loopback Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both of the SCC FIFOs are used and the channel actually operates in a full-duplex fashion.
PAGE 683
Part IV. Communications Processor Module Table 24-4. Transmission Errors (Continued) Error Description Heartbeat Some transceivers have a heartbeat (signal-quality error) self-test. To signify a good self-test, the transceiver indicates a collision to the MPC8260 within 20 clocks after the Ethernet controller sends a frame. This heartbeat condition does not imply a collision error, but that the transceiver seems to be functioning properly.
PAGE 684
Part IV. Communications Processor Module Table 24-6 describes PSMR Þelds. Table 24-6. PSMR Field Descriptions Bits Name Description 0 HBC Heartbeat checking. 0 No heartbeat checking is performed. Do not wait for a collision after transmission. 1 Wait 20 transmit clocks or 2 µs for a collision asserted by the transceiver after transmission. The HB bit in the TxBD is set if the heartbeat is not heard within 20 transmit clocks. 1 FC Force collision. 0 Normal operation.
PAGE 685
Part IV. Communications Processor Module Table 24-6. PSMR Field Descriptions Bits Name Description 12Ð14 NIB Number of ignored bits. Determines how soon after RENA assertion the Ethernet controller should begin looking for the start frame delimiter. Typically NIB = 101 (22 bits). 000 Begin searching 13 bits after the assertion of RENA. 001 Begin searching 14 bits after the assertion of RENA. ... 111 Begin searching 24 bits after the assertion of RENA. 15 Full duplex Ethernet.
PAGE 686
Part IV. Communications Processor Module Table 24-7. SCC Ethernet Receive RxBD Status and Control Field Descriptions (Continued) Bits Name Description 4 L Last in frame. The Ethernet controller sets this bit when this buffer is the last one in a frame, which occurs when the end of a frame is reached or an error is received. In the case of error, one or more of the CL, OV, CR, SH, NO, and LG bits are set. The Ethernet controller writes the number of frame octets to the data length Þeld.
PAGE 687
Part IV. Communications Processor Module E Status 0 MRBLR = 64 Bytes for this SCC Buffer Receive BD 0 L F 0 1 Destination Address (6) Length 0x0040 Pointer 32-Bit Buffer Pointer Source Address (6) Buffer Full Type/Length (2) 64 Bytes Data Bytes (50) E Status 0 Receive BD 1 L F 1 Buffer 0 Length 0x0045 Pointer 32-Bit Buffer Pointer CRC Bytes (4) Buffer Closed after CRC Received.
PAGE 688
Part IV. Communications Processor Module conÞrm transmission or indicate errors so the core knows buffers have been serviced. Offset + 0 0 1 2 3 4 5 6 R PAD W I L TC DEF 7 8 9 HB LC RL Offset + 2 Data Length Offset + 4 Tx Data Buffer Pointer 10 11 12 13 RC 14 15 UN CSL Offset + 6 Figure 24-8. SCC Ethernet TxBD Table 24-8 describes TxBD status and control Þelds. Table 24-8.
PAGE 689
Part IV. Communications Processor Module Table 24-8. SCC Ethernet Transmit TxBD Status and Control Field Descriptions (Continued) Bits Name Description 9 RL Retransmission limit. Set when the transmitter fails (Retry Limit + 1) attempts to successfully transmit a message because of repeated collisions on the medium. The Ethernet controller writes this bit after it Þnishes attempting to send the buffer. 10Ð13 RC Retry count.
PAGE 690
Part IV. Communications Processor Module Table 24-9. SCCE/SCCM Field Descriptions (Continued) Bits Name Description 9Ð10 Ñ Reserved, should be cleared. 11 TXE Set when an error occurs on the transmitter channel. 12 RXF Rx frame. Set when a complete frame has been received on the Ethernet channel. 13 BSY Busy condition. Set when a frame is received and discarded due to a lack of buffers. 14 TXB Tx buffer. Set when a buffer has been sent on the Ethernet channel. 15 RXB Rx buffer.
PAGE 691
Part IV. Communications Processor Module Note that the SCC status register (SCCS) cannot be used with the Ethernet protocol. The current state of the RENA and CLSN signals can be found in the parallel I/O ports. 24.21 SCC Ethernet Programming Example The following is an initialization sequence for the SCC2 in Ethernet mode. The CLK3 pin is used for the Ethernet receiver and CLK4 is used for the transmitter. 1. ConÞgure port D pins to enable TXD2 and RXD2.
PAGE 692
Part IV. Communications Processor Module 20. Initialize the TxBD and assume the Tx data frame is at 0x0000_2000 in main memory and contains fourteen 8-bit characters (destination and source addresses plus the type Þeld). Write 0xFC00 to TxBD[Status and Control], add PAD to the frame and generate a CRC. Then write 0x000D to TxBD[Data Length] and 0x0000_2000 to TxBD[Buffer Pointer]. 21. Write 0xFFFF to the SCCE register to clear any previous events. 22.
PAGE 693
Chapter 25 SCC AppleTalk Mode 250 250 AppleTalk is a set of protocols developed by Apple Computer, Inc. to provide a LAN service between Macintosh computers and printers. Although AppleTalk can be implemented over a variety of physical and link layers, including Ethernet, AppleTalk protocols have been most closely associated with the LocalTalk physical and link-layer protocol, an HDLC-based protocol that runs at 230.4 kbps.
PAGE 694
Part IV. Communications Processor Module The control byte within the LocalTalk frame indicates the type of frame. Control byte values from 0x01Ð0x7F are data frames; control byte values from 0x80Ð0xFF are control frames. Four control frames are deÞned: ¥ ¥ ¥ ¥ ENQÑEnquiry ACKÑEnquiry acknowledgment RTSÑRequest to send a data frame CTSÑClear to send a data frame Frames are sent in groups known as dialogs, which are handled by the software.
PAGE 695
Part IV. Communications Processor Module 25.3 Connecting to AppleTalk As shown in Figure , the MPC8260 connects to LocalTalk, and, using TXD, RTS, and RXD, is an interface for the RS-422 transceiver. The RS-422, in turn, is an interface for the LocalTalk connector. Although it is not shown, a passive RC circuit is recommended between the transceiver and connector.
PAGE 696
Part IV. Communications Processor Module 5. Clear TEND for default operation. 6. Set TPP to 0b11 for a preamble pattern of all ones. 7. Set TPL to 0b000 to transmit the next frame with no synchronization sequence and to 001 to transmit the next frame with the LocalTalk synchronization sequence. For example, data frames do not require a preceding synchronization sequence. These bits may be modiÞed on-the-ßy if the AppleTalk protocol is selected. 8. Clear TINV and RINV so data will not be inverted. 9.
PAGE 697
Chapter 26 Serial Management Controllers (SMCs) 260 260 The two serial management controllers (SMCs) are full-duplex ports that can be conÞgured independently to support one of three protocols or modesÑUART, transparent, or generalcircuit interface (GCI). Simple UART operation is used to provide a debug/monitor port in an application, which allows the SCCs to be free for other purposes. The SMC in UART mode is not as complex as that of the SCC in UART mode.
PAGE 698
Part IV. Communications Processor Module 60x Bus Control Registers SYNC Control Logic CLK Peripheral Bus RXD Rx Data Register Tx Data Register Shifter Shifter TXD Figure 26-1. SMC Block Diagram The receive data source can be L1RXD if the SMC is connected to a TDM channel of an SIx, or SMRXD if it is connected to the NMSI. The transmit data source can be L1TXD if the SMC is connected to a TDM or SMTXD if it is connected to the NMSI.
PAGE 699
Part IV. Communications Processor Module ¥ Full-duplex operation ¥ Local loopback and echo capability for testing 26.2 Common SMC Settings and ConÞgurations The following sections describe settings and conÞgurations that are common to the SMCs. 26.2.1 SMC Mode Registers (SMCMR1/SMCMR2) The SMC mode registers (SMCMR1 and SMCMR2), shown in Figure 26-2, selects the SMC mode as well as mode-speciÞc parameters. The functions of SMCMR[8Ð15] are the same for each protocol.
PAGE 700
Part IV. Communications Processor Module Table 26-1 describes SMCMR Þelds. Table 26-1. SMCMR1/SMCMR2 Field Descriptions Bits Name Description 0 Ñ Reserved, should be cleared. 1Ð4 CLEN Character length (UART). Number of bits in the character minus one. The total is the sum of 1 (start bit always present) + number of data bits (5Ð14) + number of parity bits (0 or 1) + number of stop bits (1 or 2).
PAGE 701
Part IV. Communications Processor Module Table 26-1. SMCMR1/SMCMR2 Field Descriptions (Continued) Bits Name Description 10Ð11 SM SMC mode. 00 GCI or SCIT support. 01 Reserved. 10 UART (must be selected for SMC UART operation). 11 Totally transparent operation. 12Ð13 DM Diagnostic mode. 00 Normal operation. 01 Local loopback mode. 10 Echo mode. 11 Reserved. 14 TEN SMC transmit enable. 0 SMC transmitter disabled. 1 SMC transmitter enabled. 15 REN SMC receive enable. 0 SMC receiver disabled.
PAGE 702
Part IV. Communications Processor Module The BD table allows buffers to be deÞned for transmission and reception. Each table forms a circular queue. The CP uses BDs to conÞrm reception and transmission so that the processor knows buffers have been serviced. The data resides in external or internal buffers. When SMCs are conÞgured to operate in GCI mode, their memory structure is predeÞned to be one half-word long for transmit and one half-word long for receive.
PAGE 703
Part IV. Communications Processor Module Table 26-2. SMC UART and Transparent Parameter RAM Memory Map (Continued) Offset 1 Name Width Description count. 2 A 0x12 Ñ Hword Rx internal byte down-count value initialized with the MRBLR value and decremented with every byte the SDMA channels write. 0x14 Ñ Word Rx temp 2 Can be used only by the CP. 0x18 TSTATE Word Tx internal state. 2 Can be used only by the CP. 0x1C Ñ Word Tx internal data pointer.
PAGE 704
Part IV. Communications Processor Module Certain parameter RAM values must be initialized before the SMC is enabled. Other values are initialized or written by the CP. Once values are initialized, software typically does not need to update them because activity centers mostly around transmit and receive BDs rather than parameter RAM. However, note the following: ¥ Parameter RAM can be read at any time.
PAGE 705
Part IV. Communications Processor Module 26.2.4 Disabling SMCs On-the-Fly An SMC can be disabled and reenabled later by ensuring that buffers are closed properly and new data is transferred to or from a new buffer. Such a sequence is required if the parameters to be changed are not dynamic. If the register or bit description states that dynamic changes are allowed, the sequences need not be followed and the register or bits may be changed immediately.
PAGE 706
Part IV. Communications Processor Module 26.2.4.4 SMC Receiver Shortcut Sequence This shorter sequence reinitializes receive parameters to their state after reset. 1. Clear SMCMR[REN]. 2. Issue an INIT RX PARAMETERS command and make any additional changes. 3. Set SMCMR[REN]. 26.2.4.5 Switching Protocols To switch the protocol that the SMC is executing without resetting the board or affecting any other SMC, use one command and follow these steps: 1. Clear SMCMR[REN] and SMCMR[TEN]. 2.
PAGE 707
Part IV. Communications Processor Module However, SMCs allow a data length of up to 14 bits; SCCs support up to 8 bits. SMCLK 16x (not to scale) SMTXD Start Bit 5 to 14 Data Bits with the Least Significant Bit First Parity Bit 1 or 2 Stop Bits (Optional) Figure 26-5. SMC UART Frame Format 26.3.
PAGE 708
Part IV. Communications Processor Module 26.3.3 SMC UART Channel Reception Process When the core enables the SMC receiver, it enters hunt mode and waits for the Þrst character. The CP then checks the Þrst RxBD to see if it is empty and starts storing characters in the buffer. When the buffer is full or the MAX_IDL timer expires (if enabled), the SMC clears the E bit in the BD and generates an interrupt if the I bit in the BD is set.
PAGE 709
Part IV. Communications Processor Module Table 26-5 describes receive commands issued to the CPCR. Table 26-5. Receive Commands Command Description ENTER HUNT MODE Use the CLOSE RXBD command instead ENTER HUNT MODE for an SMC UART channel. CLOSE RXBD Forces the SMC to close the current receive BD if it is currently being used and to use the next BD in the list for any subsequently received data. If the SMC is not receiving data, no action is taken.
PAGE 710
Part IV. Communications Processor Module Table 26-6. SMC UART Errors (Continued) Error Description Framing The SMC received a character with no stop bit. When it occurs, the channel writes the received character to the buffer, closes the buffer, sets FR in the BD, and generates the RXB interrupt if it is enabled. When this error occurs, parity is not checked for the character. Break Sequence The SMC receiver received an all-zero character with a framing error.
PAGE 711
Part IV. Communications Processor Module Table 26-7. SMC UART RxBD Field Descriptions (Continued) Bit Name Description 4Ð5 Ñ Reserved, should be cleared. 6 CM Continuous mode. 0 Normal operation. 1 The CP does not clear the E bit after this BD is closed, allowing the CP to automatically overwrite the buffer when it next accesses the BD. However, E is cleared if an error occurs during reception, regardless of how CM is set. 7 ID Buffer closed on reception of idles.
PAGE 712
Part IV. Communications Processor Module E Status Receive BD 0 ID MRBLR = 8 Bytes for this SMC Buffer 0 Byte 1 0 Length 0008 Pointer 32-Bit Buffer Pointer Byte 2 Buffer Full 8 Bytes etc.
PAGE 713
Part IV. Communications Processor Module Offset + 0 0 1 2 3 R Ñ W I 4 5 Ñ 6 7 CM P 8 9 Offset + 2 Data Length Offset + 4 Tx Data Buffer Pointer 10 11 12 13 14 15 Ñ Offset + 6 Figure 26-8. SMC UART TxBD Table 26-8 describes SMC UART TxBD Þelds. Table 26-8. SMC UART TxBD Field Descriptions Bits Name 0 Description R Ready 0 The buffer is not ready for transmission; BD and its buffer can be altered. The CP clears R after the buffer has been sent or an error occurs.
PAGE 714
Part IV. Communications Processor Module must be even. For instance, the pointer to 8-bit data, 1 start, and 1 stop characters can be even or odd, but the pointer to 9-bit data, 1 start, and 1 stop characters must be even. The buffer can reside in internal or external memory. 26.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM) The SMC event register (SMCE) generates interrupts and report events recognized by the SMC UART channel.
PAGE 715
Part IV. Communications Processor Module Characters Received by SMC UART 10 Characters Time RXD Line Idle Break Line Idle SMC UART SMCE Events RX RX BRK BRKE NOTES: 1. The first RX event assumes receive buffers are 6 bytes each. 2. The second RX event position is programmable based on the MAX_IDL value. 3. The BRK event occurs after the first break character is received. Characters Transmitted by SMC UART TXD SMC UART SMCE Events 7 Characters Line Idle Line Idle TX NOTES: 1.
PAGE 716
Part IV. Communications Processor Module 9. Write MAX_IDL with 0x0000 in the SMC UART-speciÞc parameter RAM to disable the MAX_IDL functionality for this example. 10. Clear BRKLN and BRKEC in the SMC UART-speciÞc parameter RAM. 11. Set BRKCR to 0x0001; if a STOP TRANSMIT COMMAND is issued, one break character is sent. 12. Initialize the RxBD. Assume the Rx data buffer is at 0x0000_1000 in main memory.
PAGE 717
Part IV. Communications Processor Module However, the SMC in transparent mode provides a data character length option of 4 to 16 bits, whereas the SCCs provide 8 or 32 bits, depending on GSMR[RFW]. The SMC in transparent mode is also referred to as the SMC transparent controller. 26.4.
PAGE 718
Part IV. Communications Processor Module 26.4.3 SMC Transparent Channel Reception Process When the core enables the SMC receiver in transparent mode, it waits for synchronization before receiving data. Once synchronization is achieved, the receiver transfers the incoming data into memory according to the Þrst RxBD in the table. Synchronization can be achieved in two ways. First, when the receiver is connected to a TDM channel, it can be synchronized to a time slot.
PAGE 719
Part IV. Communications Processor Module SMCLK SMSYN SMTXD 1s are sent Five 1s are sent SMC1 Transmit Data TEN set here SMSYN detected low here Tx FIFO Five 1s loaded assume approximately character here length equals 5 First bit of first 5-bit transmit character (lsb) Transmission could begin here if Tx FIFO not loaded in time SMCLK SMSYN SMRXD SMC1 Receive Data REN set here or ENTER HUNT MODE command issued SMSYN detected low here First bit of receive data (lsb) NOTES: 1.
PAGE 720
Part IV. Communications Processor Module TDM Tx CLK TDM Tx SYNC SMC1 SMC1 TDM Tx After TEN is set, transmission begins here. If SMC runs out of Tx buffers and new ones are provided later, transmission begins at the beginning of either time slot. TDM Rx CLK TDM Rx SYNC TDM Rx After REN is set or after SMC1 SMC1 ENTER HUNT MODE command, reception begins here. Figure 26-12.
PAGE 721
Part IV. Communications Processor Module always ready and that underruns do not occur. Otherwise, the SMC transmitter should be disabled and reenabled. Section 26.2.4, ÒDisabling SMCs On-the-Fly,Ó describes how to safely disable and reenable the SMC. Simply clearing and setting TEN may not be enough. 26.4.6 SMC Transparent Commands Table 26-10 describes transmit commands issued to the CPCR. Table 26-10.
PAGE 722
Part IV. Communications Processor Module 26.4.8 SMC Transparent RxBD Using BDs, the CP reports information about the received data for each buffer and closes the current buffer, generates a maskable interrupt, and starts to receive data into the next buffer after one of the following events: ¥ ¥ ¥ An overrun error occurs. A full receive buffer is detected. The ENTER HUNT MODE command is issued.
PAGE 723
Part IV. Communications Processor Module Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer Descriptors (BDs).Ó 26.4.9 SMC Transparent TxBD Data is sent to the CP for transmission on an SMC channel by arranging it in buffers referenced by the channel TxBD table. The CP uses BDs to conÞrm transmission or indicate error conditions so the processor knows buffers have been serviced.
PAGE 724
Part IV. Communications Processor Module Data length represents the number of octets the CP should transmit from this buffer. It is never modiÞed by the CP. The data length can be even or odd, but if the number of bits in the transparent character is greater than 8, the data length should be even. For example, to transmit three transparent 8-bit characters, the data length Þeld should be initialized to 3.
PAGE 725
Part IV. Communications Processor Module 26.4.11 SMC Transparent NMSI Programming Example The following example initializes the SMC1 transparent channel over its own set of signals. The CLK9 signal supplies the transmit and receive clocks; the SMSYNx signal is used for synchronization. (The SMC UART programming example uses a BRG conÞguration; see Section 26.3.12, ÒSMC UART Controller Programming Example.Ó) 1. ConÞgure the port D pins to enable SMTXD1, SMRXD1, and SMSYN1. Set PPARD[7,8,9] and PDIRD[9].
PAGE 726
Part IV. Communications Processor Module 26.5 The SMC in GCI Mode The SMC can control the C/I and monitor channels of the GCI frame. When using the SCIT conÞguration of a GCI, one SMC can handle SCIT channel 0 and the other can handle SCIT channel 1.
PAGE 727
Part IV. Communications Processor Module 26.5.2 Handling the GCI Monitor Channel The following sections describe how the GCI monitor channel is handled. 26.5.2.1 SMC GCI Monitor Channel Transmission Process Monitor channel 0 is used to exchange data with a layer 1 device (reading and writing internal registers and transferring of the S and Q bits). Monitor channel 1 is used for programming and controlling voice/data modules such as CODECs. The core writes the byte into the TxBD.
PAGE 728
Part IV. Communications Processor Module 26.5.4 SMC GCI Commands The commands in Table 26-18 are issued to the CPCR. Table 26-18. SMC GCI Commands Command Description Initializes transmit and receive parameters in the parameter RAM to their reset state. It is especially useful when switching protocols on a given serial channel. INIT TX AND RX PARAMETERS TRANSMIT ABORT REQUEST This receiver command can be issued when the MPC8260 implements the monitor channel protocol.
PAGE 729
Part IV. Communications Processor Module Table 26-20 describes SMC monitor channel TxBD Þelds. Table 26-20. SMC Monitor Channel TxBD Field Descriptions Bits Name Description 0 R Ready. 0 Cleared by the CP after transmission. The TxBD is now available to the core. 1 Set by the core when the data byte associated with this BD is ready for transmission. 1 L Last (EOM). Valid only for monitor channel protocol.
PAGE 730
Part IV. Communications Processor Module Table 26-22 describes SMC C/I channel TxBD Þelds. Table 26-22. SMC C/I Channel TxBD Field Descriptions Bits Name Description 0 R Ready. 0 Cleared by the CP after transmission to indicate that the BD is available to the core. 1 Set by the core when data associated with this BD is ready for transmission. 1Ð7 Ñ Reserved, should be cleared. 8Ð13 C/I DATA Command/indication data bits.
PAGE 731
Chapter 27 Multi-Channel Controllers (MCCs) 270 270 The MPC8260Õs two multi-channel controllers (MCC1 and MCC2) each handle up to 128 serial, full-duplex data channels. The 128 channels are divided into four subgroups (of 32 channels each). One or more subgroups can be multiplexed through corresponding SIx TDM channels; MCC1 connects through SI1, and MCC2 uses SI2. Each channel can be programmed separately either to perform HDLC formatting/ deformatting or to act as a transparent channel. 27.
PAGE 732
Part IV. Communications Processor Module 27.2 MCC Data Structure Organization Each MCC uses the following data structures: ¥ Global MCC parameters (common to all the 128 channels) placed in the DPR from the offset (relative to the DPR base address) deÞned in Table 13-10. ¥ Channel-speciÞc parameters. Each channel use 64 bytes of speciÞc parameters placed in the DPR at offset 64*CH_NUM (relative to the DPR base address). CH_NUM is the channel number (0Ð127 for MCC1 and 128Ð255 for MCC2).
PAGE 733
Part IV. Communications Processor Module DPR_base Buffer Descriptor Table Base Address DPR External Memory Channel 0 Parameter Channel 1 Parameter Channel j Extra Parameter Global MCC Parameters RBASE TBASE x8 + Channel j RxBD Table 512 Kbytes MCCBASE x8 + Channel j TxBD Table Figure 27-1. BD Structure for One MCC 27.3 Global MCC Parameters The global MCC parameters are described in Table 27-1. Table 27-1.
PAGE 734
Part IV. Communications Processor Module Table 27-1.
PAGE 735
Part IV. Communications Processor Module 27.4 Channel Extra Parameters Table 27-2 describes extra parameters. This table is indexed by logical channel number. Table 27-2. Channel Extra Parameters Offset1 Name Width Description 0x00 TBASE Hword TxBD base address. Offset of the channelÕs TxBD table relative to the MCCBASE (The base address of the BD table for this channel MCCBASE+8*TBASE) 0x02 TBPTR 0x04 RBASE Hword RxBD base address. Offset of the channelÕs RxBD table relative to the MCCBASE.
PAGE 736
Part IV. Communications Processor Module channels which uses the slot synchronization. Figure 27-5 shows the SI RAM programming for the same transparent or HDLC receiver super channels that do not use slot synchronization.
PAGE 737
Part IV.
PAGE 738
Part IV. Communications Processor Module 27.6 Channel-SpeciÞc HDLC Parameters Table 27-3 describes channel-speciÞc parameters for HDLC. Table 27-3. Channel-Specific Parameters for HDLC Offset1 Name Width Description 0x00 TSTATE Word Tx internal state. To start a transmitter channel the user must write to TSTATE 0xHH80_0000. HH is the TSTATE high byte described in Section 27.6.1, ÒInternal Transmitter State (TSTATE).Ó 0x04 ZISTATE Word Zero-insertion machine state.
PAGE 739
Part IV. Communications Processor Module 27.6.1 Internal Transmitter State (TSTATE) Internal transmitter state (TSTATE) is a 4-byte register provides transaction parameters associated with SDMA channel accesses (like function code registers) and starts the transmitter channel. To start the channel, write 0xHH800000 to TSTATE, where HH is the TSTATE high byte (see Figure 27-6).
PAGE 740
Part IV. Communications Processor Module Bits 0 1 2 3 4 5 6 7 8 9 Interrupt Entry Ñ UN TXB Ñ INTMSK Ñ Mask Bits Ñ 10 NID 11 12 13 14 15 IDL MRF RXF BSY RXB Mask Bits Figure 27-7. INTMSK Mask Bits To enable an interrupt, set the corresponding bit. If a bit is cleared, no interrupt request is generated and no new entry is written in the circular interrupt table. The user must initialize INTMSK prior to operation. Reserved bits are cleared. 27.6.
PAGE 741
Part IV. Communications Processor Module Table 27-5. CHAMR Field Descriptions (Continued) Bits 3 4Ð7 8 Name IDLM Description Idle mode. 0 No idle patterns are sent between frames. After sending NOF+1 ßags, the transmitter starts sending the data of the frame. If the transmission is between frames and the frame buffers are not ready, the transmitter sends ßags until it can start transmitting the data. 1 At least one idle pattern is sent between adjacent frames.
PAGE 742
Part IV. Communications Processor Module Bits 0 Field 1 Ñ 2 GBL 3 4 BO Reset Ñ R/W R/W Addr 0x20 5 6 7 TC2 DTB BDB Figure 27-9. Rx Internal State (RSTATE) High Byte RSTATE high-byte Þelds are described in Table 27-6. Table 27-6. RSTATE High-Byte Field Descriptions Bits 0Ð1 Name Description Ñ Reserved, should be cleared. GBL Global. Setting GLB activates snooping (only the 60X bus can be snooped, this parameter is ignored for local bus transactions). 3Ð4 BO Byte ordering.
PAGE 743
Part IV. Communications Processor Module Table 27-7. Channel-Specific Parameters for Transparent Operation (Continued) Offset1 0x04 Name ZISTATE Width Description Word Zero-insertion machine state.
PAGE 744
Part IV. Communications Processor Module Bits 0 1 2 3 4 5 Field MODE POL 1 1 EP RD 6 7 8 SYNC 9 Ñ Reset Ñ R/W R/W Offset 0x1A 10 11 TS 12 13 14 RQN 15 Ñ Figure 27-10. Channel Mode Register (CHAMR)ÑTransparent Mode CHAMR Þelds are described in Table 27-5, Table 27-8. CHAMR Field DescriptionsÑTransparent Mode Bits Name Description 0 MODE Channel mode. Selects either HDLC or transparent mode. 0 Transparent mode. 1 HDLC mode 1 POL Enable polling.
PAGE 745
Part IV. Communications Processor Module Table 27-8. CHAMR Field DescriptionsÑTransparent Mode (Continued) Bits 10 Name Description TS Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4 (N is any number larger than 0). 11Ð12 RQN Receive queue number. SpeciÞes the receive interrupt queue number. 00 Queue number 0. 01 Queue number 1.
PAGE 746
Part IV. Communications Processor Module Table 27-10. Group Channel Assignments Group Channels Group1 in MCCF1 0Ð31 Group2 in MCCF1 32Ð63 Group3 in MCCF1 64Ð95 Group4 in MCCF1 96Ð127 Group1 in MCCF2 128Ð159 Group2 in MCCF2 160Ð191 Group3 in MCCF2 192Ð223 Group4 in MCCF2 224Ð255 Note that the TDM group channel assignments made in MCCF must be coherent with the SI register programming and SI RAM programming; see Section 14.5, ÒSerial Interface Registers,Ó and Section 14.4.
PAGE 747
Part IV. Communications Processor Module Table 27-12 describes receive commands. Table 27-12. Receive Commands Command Description Forces the receiver of the selected channel to terminate reception. After this command is executed, the CP does not change the receive parameters in the dual-port RAM. The user must initialize the channel receive parameters in order to restart reception. STOP RECEIVE INIT RX PARAMETERS Initializes all receive parameters in this MCC parameter RAM to their reset state.
PAGE 748
Part IV. Communications Processor Module end of the table). When an MCC channel generates an interrupt request, the CP writes a new entry to the table (with V = 1) and increments T/RINTPTR (if W = 1 for the current entry, T/RINTPTR is loaded with T/RINTBASE).
PAGE 749
Part IV. Communications Processor Module Table 27-13 describes MCCE Þelds. Table 27-13. MCCE/MCCM Register Field Descriptions Bits Name 0 QOV0 1 RINT0 2 QOV1 3 RINT1 4 QOV2 5 RINT2 6 QOV3 7 RINT3 8Ð11 Description QOVxÑReceive interrupt queue overßow. IQOV is set (and an interrupt request generated) by the CP whenever an overßow occurs in the transmit circular interrupt table.
PAGE 750
Part IV. Communications Processor Module Bits 0 1 Field V W 2 3 4 5 Ñ 6 7 UN TXB R/W 8 9 Ñ 10 11 12 13 14 15 NID IDL 26 27 28 29 30 31 0 0 0 0 0 0 MRF RXF BSY RXB R/W Bits 16 Field 17 Ñ 18 19 20 21 22 23 24 25 Channel Number R/W R/W Figure 27-14. Interrupt Circular Table Entry Table 27-14 describes interrupt circular table Þelds. Table 27-14. Interrupt Circular Table Entry Field Descriptions Bits Name Description 0 V Valid bit.
PAGE 751
Part IV. Communications Processor Module 27.11 MCC Buffer Descriptors Each MCC channel requires two BD tables (one for transmit and one for receive). Each BD contains key information about the buffer it deÞnes. The BDs are accessed by the MCC as needed; BDs can be added dynamically to the BDs chain. The RxBDs chain must include at least two BDs; the TxBD chain must include at least one BDs. The MCC BDs are located in the external memory. 27.11.
PAGE 752
Part IV. Communications Processor Module Table 27-15. RxBD Field Descriptions (Continued) Bits Name Description 5 F First in frame. The HDLC controller sets F = 1 for the Þrst buffer in a frame. In transparent mode, F indicates that there was a synchronization before receiving data in this BD. 0 This is not the Þrst buffer in a frame. 1 This is the Þrst buffer in a frame. 6 CM Continuous mode 0 Normal operation (The empty bit (bit 0) is cleared by the CP after this BD is closed).
PAGE 753
Part IV. Communications Processor Module The data length and buffer pointer are described as follows: ¥ Data length. Data length is the number of octets written by the CP into this BDÕs data buffer. It is written by the CP when the BD is closed. When this is the last BD in the frame (L = 1), the data length contains the total number of frame octets (including two or four bytes for CRC).
PAGE 754
Part IV. Communications Processor Module Table 27-16. TxBD Field Descriptions (Continued) Bits Name Description 5 F Tx CRC. Valid only when L = 1. Otherwise it must be ignored. 0 Transmit the closing ßag after the last data byte. This setting can be used for testing purposes to send an erroneous CRC after the data. 1 Transmit the CRC sequence after the last data byte. 6 CM Continuous mode 0 Normal operation.
PAGE 755
Part IV. Communications Processor Module 27.12.1 Single-Channel Initialization The following sequence must be followed to initialize and start a single channel (after reset or after a fatal error): 1. Program the SI. The entries the MCC channels uses must point to the null channel (set in the SI RAM entry MCC = 0, CSEL = 0 and the correct size - 1 byte); entries used by other controllers (not MCC) can be activated at this time. 2. Initialize the MCC parameters (in DPR and external memory). 3.
PAGE 756
Part IV. Communications Processor Module 27.12.2 Super Channel Initialization The following steps initialize and start a super channel (after reset of after a fatal error): 1. Program the SI as required for a super channel but do not enable the TDM. 2. Issue a STOP command as described in Section 27.9, ÒMCC Commands.Ó 3. Enable the TDM. 4. Initialize the MCC parameters (in DPR and external memory). 5. Enable the MCC channel(s) as described in Section 27.6.
PAGE 757
Part IV. Communications Processor Module If multiple synchronized channels are used (as an example 8 T1 with common clock/sync) it is recommended to start the channels out of phase in order to load uniformly the bus. This avoids bus activity peaks when all the channels have to transfer data to/from the memory simultaneously. MOTOROLA Chapter 27.
PAGE 758
Part IV.
PAGE 759
Chapter 28 Fast Communications Controllers (FCCs) 280 280 The MPC8260Õs fast communications controllers (FCCs) are serial communications controllers (SCCs) optimized for synchronous high-rate protocols. FCC key features include the following: ¥ ¥ ¥ Supports HDLC/SDLC and totally transparent protocols FCC clocks can be derived from a baud-rate generator or an external signal.
PAGE 760
Part IV. Communications Processor Module 28.1 Overview MPC8260 FCCs can be conÞgured independently to implement different protocols. Together, they can be used to implement bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks.
PAGE 761
Part IV. Communications Processor Module 60x Bus Control Registers TCLK Clock Generator Peripheral Bus RCLK Internal Clocks RXD Modem Lines Receive Control Unit Decoder Delimiter Receive Data FIFO Transmit Data FIFO Shifter Shifter Transmit Control Unit Modem Lines Delimiter Encoder TXD Figure 28-1. FCC Block Diagram 28.2 General FCC Mode Registers (GFMRx) Each FCC contains a general FCC mode register (GFMRx) that deÞnes all options common to every FCC, regardless of the protocol.
PAGE 762
Part IV. Communications Processor Module Table 28-1 describes GFMR Þelds. Table 28-1. GFMR Register Field Descriptions Field 0Ð1 Name Description DIAG Diagnostic mode. 00 Normal operationÑReceive data enters through RXD, and transmit data is shifted out through TXD. The FCC uses the modem signals (CD and CTS) to automatically enable and disable transmission and reception. Timings are shown in Section 28.11, ÒFCC Timing Control.
PAGE 763
Part IV. Communications Processor Module Table 28-1. GFMR Register Field Descriptions (Continued) Field Name Description 5 CDP CD pulse (transparent mode only) 0 Normal operation (envelope mode). CD should envelope the frame; to negate CD while receiving causes a CD lost error. 1 Pulse mode. Once CD is asserted (high to low transition), synchronization has been achieved, and further transitions of CD do not affect reception. This bit must be set if this FCC is used in the TSA.
PAGE 764
Part IV. Communications Processor Module Table 28-1. GFMR Register Field Descriptions (Continued) Field Name Description 22Ð23 TENC Transmitter encoding method. The user should set TENC = RENC in most applications. 00 NRZ 01 NRZI (one bit mode HDLC or transparent only) 1x Reserved 24-25 TCRC Transparent CRC (totally transparent channel only). Selects the type of frame checking provided on the transparent channels of the FCC (either the receiver, transmitter, or both, as deÞned by TTX and TRX).
PAGE 765
Part IV. Communications Processor Module 28.3 FCC Protocol-SpeciÞc Mode Registers (FPSMRx) The functionality of the FCC varies according to the protocol selected by GFMR[MODE]. Each FCC has an additional 32-bit, memory-mapped, read/write protocol-speciÞc mode register (FPSMR) that conÞgures them speciÞcally for a chosen mode. The section for each speciÞc protocol describes the FPSMR bits. 28.
PAGE 766
Part IV. Communications Processor Module Bits 0 Field TOD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ñ Reset 0000_0000_0000_0000 R/W R/W Address 0x11308 (FTODR1), 0x11328 (FTODR2), 0x11328 (FTODR3) Table 28-3. FCC Transmit-on-Demand Register (TODR) Fields in the TODR are described in Table 28-4 Table 28-4. TODR Field Descriptions Field Name 0 TOD 1Ð15 Ñ Description Transmit on demand 0 Normal polling.
PAGE 767
Part IV. Communications Processor Module Dual-Port RAM External Memory Tx Buffer Descriptors Status and Control Data Length FCCx TxBD Table Buffer Pointer Tx Buffer Rx Buffer Descriptors FCCx RxBD Table Status and Control Data Length FCCx RxBD Table Pointer (RBASE) Buffer Pointer FCCx TxBD Table Pointer (TBASE) Rx Buffer Figure 28-3. FCC Memory Structure The format of transmit and receive BDs, shown in Figure 28-4, is the same for every FCC mode of operation except ATM mode; see Section 29.10.
PAGE 768
Part IV. Communications Processor Module The BDs and data buffers can be anywhere in the system memory. The CP processes the TxBDs in a straightforward fashion. Once the transmit side of an FCC is enabled, it starts with the Þrst BD in that FCCÕs TxBD table. When the CP detects that TxBD[R] is set, it begins processing the buffer. The CP detects that the BD is ready either by polling the R bit periodically or by the user writing to the TODR.
PAGE 769
Part IV. Communications Processor Module Some parameter RAM values must be initialized before the FCC is enabled; other values are initialized/written by the CP. Once initialized, most parameter RAM values do not need to be accessed by user software because most activity centers around the TxBDs and RxBDs rather than the parameter RAM. However, if the parameter RAM is accessed, note the following: ¥ ¥ ¥ ¥ Parameter RAM can be read at any time.
PAGE 770
Part IV. Communications Processor Module Table 28-5. FCC Parameter RAM Common to All Protocols (Continued) Offset1 Name Width Description 0x0C RBASE Word RxBD base address (must be divisible by eight). DeÞnes the starting location in the memory map for the FCC RxBDs. This provides great ßexibility in how FCC RxBDs are partitioned.
PAGE 771
Part IV. Communications Processor Module 28.7.1 FCC Function Code Registers (FCRx) The function code registers contain the transaction speciÞcation associated with SDMA channel accesses to external memory. Figure 28-5 shows the format of the transmit and receive function code registers, which reside at TSTATE[0Ð7] and RSTATE[0Ð7] in the FCC parameter RAM (see Table 28-5). Bits 0 Field 1 Ñ 2 3 GBL 4 BO 5 6 7 TC2 DTB BDB Figure 28-5.
PAGE 772
Part IV. Communications Processor Module Events that can cause the FCC to interrupt the processor vary slightly among protocols and are described with each protocol. These events are handled independently for each channel by the FCC event and mask registers (FCCE and FCCM). 28.8.1 FCC Event Registers (FCCEx) Each FCC has a 24-bit FCC event register (FCCE) used to report events. On recognition of an event, the FCC sets its corresponding FCCE bit regardless of the corresponding mask bit.
PAGE 773
Part IV. Communications Processor Module 6. Write the FDSR. 7. Initialize the required values for this FCC in its parameter RAM. 8. Clear out any current events in FCCE, as needed. 9. Write the FCCM register to enable the interrupts in the FCCE register. 10. Write the SCPRR_H to conÞgure the FCC interrupt priority. 11. Clear out any current interrupts in the SIPNR_L, if preferred. 12. Write the SIMR_L to enable interrupts to the CP interrupt controller. 13.
PAGE 774
Part IV. Communications Processor Module RTS is asserted when FCC has data to transmit in the transmit FIFO and a falling transmit clock occurs. At this point, the FCC begins sending the data, once the appropriate conditions occur on CTS. In all cases, the Þrst bit of data is the start of the opening ßag, or sync pattern. Figure 28-6 shows that the delay between RTS and data is 0 bit times, regardless of the setting of GFMR[CTSS].
PAGE 775
Part IV. Communications Processor Module TCLK TXD (Output) RTS (Output) CTS (Input) First Bit Of Frame Data Last Bit of Frame Data CTS Sampled Low Note: 1. GFMR_H[CTSS] = 0. CTSP is a donÕt care. TCLK TXD (Output) RTS (Output) First Bit of Frame Data Last Bit of Frame Data CTS (Input) Note: 1. GFMR_H[CTSS] = 1. CTSP is a donÕt care. Figure 28-7. Output Delay from CTS Asserted If it is programmed to envelope the data, CTS must remain asserted during frame transmission or a CTS lost error occurs.
PAGE 776
Part IV. Communications Processor Module TCLK TXD (Output) RTS (Output) CTS (Input) Data Forced High First Bit of Frame Data CTS Sampled Low RTS Forced High CTS Sampled High CTS Lost Signaled in BD Note: 1. GFMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur. TCLK TXD (Output) RTS (Output) Data Forced High First Bit of Frame Data RTS Forced High CTS (Input) CTS Lost Signaled in BD Note: 1. GFMR_H[CTSS] = 1. CTSP=0 or no CTS lost can occur. Figure 28-8.
PAGE 777
Part IV. Communications Processor Module RCLK RXD (Input) CD (Input) First Bit of Frame Data CD Sampled Low Last Bit of Frame Data CD Sampled High Notes: 1. GFMR_H[CDS] = 0. CDP=0. 2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the BD. 3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.
PAGE 778
Part IV. Communications Processor Module 28.12.1 FCC Transmitter Full Sequence For the FCC transmitter, the full disable and enable sequence is as follows. 1. Issue the STOP TRANSMIT command. This is recommended if the FCC is currently transmitting data because it stops transmission in an orderly way. If the FCC is not transmitting (no TxBDs are ready or the GRACEFUL STOP TRANSMIT command has been issued and completed), then the STOP TRANSMIT command is not required.
PAGE 779
Part IV. Communications Processor Module 28.12.4 FCC Receiver Shortcut Sequence A shorter sequence is possible if the user prefers to reinitialize the receive parameters to the state they had after reset. This sequence is as follows: 1. Clear GFMR[ENR]. 2. Issue the INIT RX PARAMETERS command. Any additional changes can be made now. 3. Set GFMR[ENR]. 28.12.
PAGE 780
Part IV.
PAGE 781
Chapter 29 ATM Controller 290 290 The ATM controller provides the ATM and AAL layers of the ATM protocol using the universal test and operations physical layer (PHY) interface for ATM (UTOPIA level II) for both master and slave modes. It performs segmentation and reassembly (SAR) functions of AAL5, AAL1, and AAL0, and most of the common parts of the convergence sublayer (CPCS) of these protocols.
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Part IV. Communications Processor Module 29.1 Features The ATM controller has the following features: ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ Full duplex segmentation and reassembly at 155 Mbps UTOPIA level II master and slave modes 8/16 bit AAL5, AAL1, AAL0 protocols Up to 255 active VCs internally, and up to 64K VCs using external memory TM 4.0 CBR, VBR, UBR, UBR+ trafÞc types VBR type 1 and 2 trafÞc using leaky buckets (GCRA) TM 4.
PAGE 783
Part IV.
PAGE 784
Part IV. Communications Processor Module ¥ ¥ ¥ ¥ ¥ Available bit rate (ABR) Ñ Performs ATMF UNI 4.
PAGE 785
Part IV. Communications Processor Module 29.2.1 Transmitter Overview Before the transmitter is enabled, the host must initialize the MPC8260 and create the transmit data structure, described in Section 29.10, ÒATM Memory Structure.Ó When data is ready for transmission, the host arranges the BD table and writes the pointer of the Þrst BD in the transmit connection table (TCT). The host issues an ATM TRANSMIT command, which inserts the current channel to the ATM pace control (APC) unit.
PAGE 786
Part IV. Communications Processor Module generated and inserted into the cell. The MPC8260 supports synchronous residual time stamp (SRTS) generation using external PLL. If this mode is enabled, the MPC8260 reads the SRTS code from the external logic and inserts it into four outgoing cells. See Section 29.15, ÒSRTS Generation and Clock Recovery Using External Logic.Ó For the structured format, the transmitter reads 47 or 46 bytes from the external buffer and inserts them into the AAL1 user data Þeld.
PAGE 787
Part IV. Communications Processor Module Reception starts when the PHY asserts the receive cell available signal (RxCLAV) to indicate that the PHY has a complete cell in its receive FIFO. The receiver reads a complete cell from the UTOPIA interface and translates the header address (VP/VC) to a channel code by performing an address look-up. If no matches are found, the cell is discarded and the user-network interface (UNI) statistics tables are updated.
PAGE 788
Part IV. Communications Processor Module Þrst byte of the new buffer. If an SN mismatch is detected, the ATM receiver closes the current RxBD, sets RxBD[SNE], and returns to the hunt state. The receiver then waits for a cell with a valid structured pointer to regain synchronization. The MPC8260 supports partially Þlled cells conÞgured on a per-VC basis. In this mode, the ATM controller copies only the valid octets from the cell user data Þeld to the buffer. 29.2.2.
PAGE 789
Part IV. Communications Processor Module Table 29-1. ATM Service Types Service Type Cell Rate Pacing Real-Time/ Non-Real-Time Relative Priority CBR PCR RT 1 (highest) VBR-RT PCR, SCR (peak-and-sustain) RT 2 VBR-NRT PCR, SCR (peak-and-sustain) NRT 3 ABR1 PCR NRT 4 UBR+ PCR, MCR (peak-and-minimum) NRT 5 UBR PCR NRT 6 (lowest) 1When ABR ßow control is active, the CP automatically adapts the APC parameters PCR, PCR_FRACTION.
PAGE 790
Part IV. Communications Processor Module Cells per Slot 9 5 6 1 4 3 7 8 2 Number of Slots Current Slot Cell Rescheduling Figure 29-1. APC Scheduling Table Mechanism Each 2-byte time-slot entry points to one ATM channel. Additional channels scheduled to transmit in the same slot are linked to each other using the APC linked-channel Þeld in the TCT.
PAGE 791
Part IV. Communications Processor Module 29.3.3.2 Determining the Number of Slots in a Scheduling Table The number of time slots in a scheduling table is determined by the channel with the minimum bit rate; see equation B. The minimum bit rate is achieved when the channel reschedules only once in a whole table scan. (The maximum schedule advance allowed is equal to number_of_slots-1.) For example, if the line rate is 155.
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Part IV. Communications Processor Module The resulting number of slots is written into TCT[PCR] and TCT[PCR_FRACTION]. Because PCR_FRACTION is in units of 1/256 slots, the fraction must be converted as follows: 1.241 = 1+0.241 ´ 256/256 =1+ 61.79/256 ~ 1 + 62/256 PCR = 1 PCR_FRACTION = 62 29.3.5.3 Peak and Sustain TrafÞc Type (VBR) Variable bit rate (VBR) trafÞc can burst at the peak cell rate as long as the long-term average rate does not exceed the sustainable cell rate.
PAGE 793
Part IV. Communications Processor Module PCR [slots] = (155.52 Mbps)/(6 Mbps ´ 8) = 3.24 3.24 = 3 + 0.24 ´ 256/256 = 3 + 61.44/256 ~ 3 + 62/256 PCR = 3 PCR_FRACTION = 62 SCR [slots] = (155.52 Mbps)/(2 Mbps ´ 8) = 9.72 9.72 = 9 + (0.72 ´ 256/256) = 9 + 184.32/256 ~ 9 + 185/256 SCR = 9 SCR_FRACTION = 185 Equation D yields the number of slots the user writes to the channelÕs TCT[BT].
PAGE 794
Part IV. Communications Processor Module 29.4 VCI/VPI Address Lookup Mechanism The MPC8260 supports two ways to look up addresses for incoming cells: ¥ External CAM lookup ¥ Address compression Writing to GMODE[ALM] (address-lookup-mechanism bit) in the parameter RAM selects the mechanism. Both mechanisms are described in the following sections. 29.4.1 External CAM Lookup An external CAM is usually used when the range of VCI/VPI values varies widely or is unknown.
PAGE 795
Part IV. Communications Processor Module The external CAM Þelds are described in Table 29-2 Table 29-2. External CAM Input and Output Field Descriptions Field Description PHY Addr In multiple PHY mode, this Þeld contains the 4 least-signiÞcant bits of the current channelÕs physical address. Because this CAM comparison Þeld is limited to 4 bits, two CAM devices are needed if using more than 16 PHYs.The msb of the PHY address lines (bit 4) selects between the two devices.
PAGE 796
Part IV. Communications Processor Module 4 bit 12 bit VPI PHY Addr 0000 VPT_BASE 0000 00011111 0 VP-level addressing table (in dual-port RAM recommended) VP_MASK 16 bit 0b00011 VPpointer 31 32-bit entries VC_MASK 16 bit VCOFFSET VC-level addressing tables (in external memory) 16 bit 32-bit entries VCI VCT_BASE 00000111 11110000 VCpointer 1 bit 15 bit MS Ñ 0 16 bit Ch Code[15Ð0] 31 Figure 29-5.
PAGE 797
Part IV. Communications Processor Module 29.4.2.1 VP-Level Address Compression Table (VPLT) The size of the VP-level table depends on the number of mask bits in VP_MASK. For example, if only one PHY is available (PHY address = 0) and VPMASK = 0b11_1111_1111, VP pointer contains ten bits and the table is 4 Kbytes. Because each VPLT entry is 4 bytes, the address of an entry is VPT_BASE + VP pointer ´ 4.
PAGE 798
Part IV. Communications Processor Module Figure 29-7 shows the VP pointer address compression from Table 29-5. PHY+VPI 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 VP_MASK 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 0 1 VP Pointer Figure 29-7. VP Pointer Address Compression 29.4.2.2 VC-Level Address Compression Tables (VCLTs) Each VPLT entry points to a single VCLT. Like the VPLT, the size of each VCLT depends on VC_MASK.
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Part IV. Communications Processor Module 29.4.4 Receive Raw Cell Queue Channel one in the RCT is reserved as a raw cell queue. The user should program channel one to operate in AAL0 protocol. The receive raw cell queue is used for removing management cells from the regular cell ßow to the host. When a management cell is sent to the receive raw cell queue, the CP sets RxBD[OAM]. The ALL0 BD speciÞes the channel code associated with the current OAM cell.
PAGE 800
Part IV. Communications Processor Module 29.5 Available Bit Rate (ABR) Flow Control While CBR service provides a Þxed bandwidth and is useful for real-time applications with strictly bounded end-to-end cell transfer delay and cell-delay variation, ABR service is intended for data applications that can adapt to time-varying bandwidth and can tolerate signiÞcant cell transfer delay and cell delay variation. The MPC8260 implements the two following mechanisms deÞned by the ATM Forum TM 4.
PAGE 801
Part IV. Communications Processor Module The MPC8260 ABR ßow control implements both source and destination behavior. The MPC8260Õs ABR ßowchart is described in Section 29.5.1.3, ÒABR Flowcharts.Ó 29.5.1.1 ABR Flow Control Source End-System Behavior The MPC8260Õs implementation of ABR ßow control for end-system sources is described in the following steps: 1. An ABR channelÕs allowed cell rate (ACR) lies between the minimum cell rate (MCR) and the peak cell rate (PCR). 2.
PAGE 802
Part IV. Communications Processor Module 3. The CCR and MCR Þelds are taken from the F-RM and is not changed. 4. The CI bit of the B-RM cell is set if the previous data cell arrived with EFCI = 1 (congestion bit in the ATM cell header). 5. The ER Þeld of the turn around B-RM cells is limited by TCTE[ER-BRM]. 6. If a F-RM cell arrives before the previous F-RM cell was turned around (for the same connection), the new RM cell overwrites the old RM cell. 29.5.1.
PAGE 803
Part IV. Communications Processor Module RM/DATA In Rate Cell Tx Source End-Sys 3 B-RM/DATA In Rate Cell Tx No Count >= Nrm or (Count > Mrm and Now ³ (Last_RM+Trm)) Count=Number of data cells from last F-RM. Nrm=Number of data cells between every RM cell Mrm=Fixed number=2 Trm=Max time between every F-RM Cells. F-RM In Rate Cell Tx Checking ÒTime-Out FactorÓ Max time allowed between RM Cells before a rate Decrease is required.
PAGE 804
Part IV. Communications Processor Module B-RM/DATA In Rate Cell Tx No Turn-around and (First-turn or not data-in-queue) Destination End-Sys 1,2,3,4 B-RM In Rate Cell Tx Yes CI-TA = CI-TA || CI-VC Send RM cell (DIR = backwards, CCR-TA, ER-TA, MCR-TA, CI-TA, NI-TA, CLP=0) CI-VC = 0 Turn-around = first-turn = FALSE Count = Count+1 EXIT Data Cell Tx Send Data Cell CLP = EFCI = 0 Count = Count+1 Schedule:Time_to_send = Now+1/ACR EXIT Figure 29-13.
PAGE 805
Part IV. Communications Processor Module B-RM Cells Rx No CI = 1 Yes Source End-Sys 5 ACR = ACR-ACR´RDF No NI = 0 Yes Source End-Sys 1, 6 ACR = ACR+RIF´PCR ACR = min(ACR,PCR) ACR = min(ACR,ER) ACR = max(ACR,MCR) Source End-Sys 5, 6 No BN = 0 Yes The source generate this RM Unack = 0 Unack = Number of F-RM in absence of B-RM = 0 EXIT Figure 29-14. ABR Receive Flow 29.5.2 RM Cell Structure Table 29-7 describes the structure of the RM cell supported by the MPC8260.
PAGE 806
Part IV. Communications Processor Module Table 29-7. Fields and their Positions in RM Cells Fields Octet Bits Description Header 1Ð5 All ATM cell header RM-VCC PTI=6 ID 6 All Protocol ID 1 DIR 7 0 Direction of RM cell (0 = forward, 1 = backward) BN 7 1 Backward notiÞcation (BN = 0, the cell was generated by the source; BN=1, the cell was generated by the network or by the destination) CI 7 2 Congestion indication. (1 = congestion, 0 = otherwise) NI 7 3 No increase indication.
PAGE 807
Part IV. Communications Processor Module 29.5.3 ABR Flow Control Setup Follow these steps to setup ABR ßow control: 1. Initialize the ABR data structure: RCT, TCT, RCT-ABR protocol-speciÞc, TCTEABR protocol-speciÞc. 2. Initialize ABR global parameters in the parameter RAM. See Section 29.10.1, ÒParameter RAM.Ó 3. Program the AAL-type in the RCT and TCT to AAL5 and set TCT[ABRF]. Note that the ABR ßow control is available only with AAL5. 4.
PAGE 808
Part IV. Communications Processor Module Table 29-9 lists pre-assigned header values at the network-node interface (NNI). Table 29-9.
PAGE 809
Part IV. Communications Processor Module 29.6.5 Transmitting OAM F4 or F5 Cells OAM F4/F5 ßow cells are sent using the usual AAL0 transmit ßow. For OAM F4/F5 cell transmission, program channel one in the TCT to operate in AAL0 mode. Enable the CR10 (CRC-10 insertion) mode as described in Section 29.10.2.3.3, ÒAAL0 Protocol-SpeciÞc TCT.Ó Prepare the OAM F4/F5 ßow cell and insert it in an AAL0 TxBD. Finally, issue a ATM TRANSMIT command to send the OAM cell.
PAGE 810
Part IV. Communications Processor Module Table 29-10 describes performance monitoring cell Þelds. Table 29-10. Performance Monitoring Cell Fields Field Description BRC FMC MCSN Monitoring cell sequence number. The sequence number of the performance monitoring cell (modulo 256). Yes Yes TUC0+1 Total user cell 0+1 count. Counts all user cells (modulo 65,536) sent before the FMC was inserted. Yes Yes TUC0 Total user cell 0 count.
PAGE 811
Part IV. Communications Processor Module BEDC is calculated. When an FMC is received, the CP adds the BRC Þelds into the cell payload (TRCC0, TRCC0+1, BLER) and transfers the cell to the receive raw cell queue. The user can monitor the BRC cell results and transfer the cell to the transmit raw cell queue. Before the BRC is transferred to the transmit raw cell queue, the PM function type should be changed to backward reporting and additional checking should be done regarding the BLER Þeld.
PAGE 812
Part IV. Communications Processor Module 512 User Cells 3 512 User Cells 1 2 FMC Cell TUC0 TUC0+1 BEDC TSTP Data Cell Data Cell FMC Cell Data Cell Data Cell TUC0 TUC0+1 BEDC TSTP Destination BRCÕs Transmit Stream FMC Cell Source Cells Stream TUC0 TUC0+1 BEDC TSTP 1 2 3 BRC Cell BRC Cell BRC Cell TUC0 TUC0+1 TRCC0 TRCC0+1 BLER TSTP TUC0 TUC0+1 TRCC0 TRCC0+1 BLER TSTP TUC0 TUC0+1 TRCC0 TRCC0+1 BLER TSTP Figure 29-18. FMC, BRC Insertion 29.6.6.
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Part IV. Communications Processor Module Extra Header (1Ð12 Bytes) ATM Cell Header (4 Bytes) + HEC (optional) Payload (48 Bytes) Figure 29-19. Format of User-Defined Cells For AAL5 and AAL1 the extra header is taken from the Rx and Tx BDs. The transmitter reads the extra header from the UDC TxBD and adds it to each ATM cell associated with the current buffer. At the receive side, the extra header of the last cell in the current buffer is written to the UDC RxBD.
PAGE 814
Part IV. Communications Processor Module Counters are implemented in the dual-port RAM for each PHY device. The counters of each PHY are located in the UNI statistics table, described in Section 29.10.7, ÒUNI Statistics Table.Ó 29.9 ATM-to-TDM Interworking The MPC8260 supports ATM and TDM interworking. The MCCs and their corresponding SIs handle the TDM data processing. (See Chapter 27, ÒMulti-Channel Controllers (MCCs),Ó and Chapter 14, ÒSerial Interface with Time-Slot Assigner.
PAGE 815
Part IV. Communications Processor Module BD Table TDM Interface Buffer 1 MCC Transmitter MCC Tx ptr ATM Rx ptr UTOPIA Interface ATM* Receiver 0 1 1 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 Buffer 2 Buffer 3 Buffer 4 Buffer 5 BD Table UTOPIA Interface Buffer 1 ATM Transmitter ATM Tx ptr MCC Rx ptr TDM Interface MCC* Receiver 0 1 1 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 Buffer 2 Buffer 3 Buffer 4 Buffer 5 * The MCC and ATM receivers should be programmed to operate in opposite polarity E (empty) bit. Figure 29-21.
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Part IV. Communications Processor Module cope with the ATM networkÕs CDV), set ATM RxBD[I]. When the receive buffer is full, the RxBD is closed, RxBD[E] is set (because it is operating in opposite E-bit polarity), and the core is interrupted. The core then starts the MCC transmitter. 29.9.3 Timing Issues Use of the TDM interface assumes that all communicating entities are synchronized (that is, that they are using a synchronized serial clock).
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Part IV. Communications Processor Module core then moves the buffer pointer to the MCC. The bufferÕs data length should not include the CAS octets. To optimize the process, the framer may interrupt the core only when the CAS information changes. (CAS information changes slowly.) The core can keep the CAS block in memory and connect to the framer only when the CAS changes. The core can use regular read and write cycles when connecting to the framer through a parallel interface.
PAGE 818
Part IV. Communications Processor Module Table 29-11. ATM Parameter RAM Map Offset1 Name Width 0x00Ð 0x3F Ñ Ñ 0x40 RCELL_TMP_ BASE 0x42 Description Reserved, should be cleared. Hword Rx cell temporary base address. Points to a total of 52 bytes reserved dualport RAM area used by the CP. Should be 64 byte aligned. User-deÞned offset from dual-port RAM base. (Recommended address space: 0x3000-0x4000 or 0xB000Ð0xC000) TCELL_TMP_BASE Hword Tx cell temporary base address.
PAGE 819
Part IV. Communications Processor Module Table 29-11. ATM Parameter RAM Map (Continued) Offset1 Name Width 0x6C BD_BASE_EXT Word BD table base address extension. BD_BASE_EXT[0Ð7] holds the 8 mostsigniÞcant bits of the Rx/Tx BD table base address. BD_BASE_EXT[8Ð31] should be zero. User-deÞned. 0x70 VPT_BASE / EXT_CAM_BASE Word Base address of the address compression VP table/external CAM. UserdeÞned. 0x74 VCT_BASE Word Base address of the address compression VC table. User-deÞned.
PAGE 820
Part IV. Communications Processor Module Table 29-11. ATM Parameter RAM Map (Continued) Offset1 Name 0xAC Nrm Hword (ABR only) Controls the maximum cells the source may send for each F-RM cell. Set to 32 cells. 0xAE Mrm Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data cell. Set to 2 cells. 0xB0 TCR Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR channels. An ABR channel whose ACR is less than TCR sends only out-of-rate F-RM cells at TCR.
PAGE 821
Part IV. Communications Processor Module 29.10.1.3 Global Mode Entry (GMODE) Figure 29-23 shows the layout of the global mode entry (GMODE). Bits 0 1 2 3 4 5 Field 0 0 0 0 0 0 6 7 8 ALB CTB REM 9 10 0 0 11 12 13 UEAD CUAB EVPT 14 15 0 ALM Figure 29-23. Global Mode Entry (GMODE) Table 29-14 describes GMODE Þelds. Table 29-14. GMODE Field Descriptions Bits Name Description 0Ð5 Ñ 6 ALB Address look up bus for CAM or address compression tables 0 Reside on the 60x bus.
PAGE 822
Part IV. Communications Processor Module use ABR, VBR or UBR+ services. Each connection table entry resides in a 32-byte space. Table 29-15 lists sizes for RCT, TCT, and TCTE. Table 29-15.
PAGE 823
Part IV. Communications Processor Module Dual-Port RAM External Memory EXT_RCT_BASE INT_RCT_BASE Reserved RCT256 Raw Cell (AAL0) RCT257 RCT2 RCT258 RCT3 RCT259 RCT63 RCT1217 Figure 29-24.
PAGE 824
Part IV.
PAGE 825
Part IV. Communications Processor Module Table 29-16 describes RCT Þelds. Table 29-16. RCT Field Descriptions Offset 0x00 0x02 Bits 0Ð1 Ñ Description Reserved, should be cleared. 2 GBL Global. Asserting GBL enables snooping of data buffers, BD, interrupt queues and free buffer pool. 3Ð4 BO Byte orderingÑused for data buffers. 00 Reserved 01 PowerPC little endian 1x Big endian 5 Ñ Reserved, should be cleared. 6 DTB Data buffers bus 0 Data buffers reside on the 60x bus.
PAGE 826
Part IV. Communications Processor Module Table 29-16. RCT Field Descriptions (Continued) Offset Bits Name Description 0x04 Ñ RxDBPTR Receive data buffer pointer. Holds real address of current position in the Rx buffer. 0x08 Ñ Cell Time Stamp Used for reassembly time-out. Whenever a cell is received, the MPC8260 time stamp timer is sampled and written to this Þeld. See Section 13.3.7, ÒRISC Time-Stamp Control Register (RTSCR).Ó 0x0C Ñ RBD_Offset RxBD offset from RBD_BASE.
PAGE 827
Part IV. Communications Processor Module Table 29-17 describes AAL5 protocol speciÞc RCT Þelds. Table 29-17. RCT Settings (AAL5 Protocol-Specific) Offset Bits Name 0x0E Ñ TML 0x10 Ñ RxCRC 0x14 Ñ 0x16 Ñ 0x18 0Ð7 Description Total message length. This Þeld is used by the CP. CRC32 temporary result. RBDCNT RxBD count. Indicates how may bytes remain in the current Rx buffer. RBDCNT is initialized with MRBLR whenever the CP opens a new buffer. Ñ Reserved, should be cleared.
PAGE 828
Part IV. Communications Processor Module Table 29-18 describes AAL5-ABR protocol-speciÞc RCT Þelds. Table 29-18. ABR Protocol-Specific RCT Field Descriptions Offset Bits Name Description 0x0E Ñ Ñ 0x16 Ñ PCR Peak cell rate. The peak number of cells per second of the current ABR channel. The ACR (allowed cell rate) never exceeds this value. PCR uses the ATMF TM 4.0 ßoating-point format. 0x18 0Ð3 RDF Rate decrease factor for the current ABR channel.
PAGE 829
Part IV. Communications Processor Module Table 29-19. AAL1 Protocol-Specific RCT Field Descriptions Offset 0x0E Bits 0Ð7 0x12 Ñ Description Reserved, should be cleared. 8 PFM Partially Þlled mode. 0 Partially Þlled cells mode is not used. 1 Partially Þlled cells mode is used. The receiver copies only valid octets from the AAL1 cell to the Rx buffer. The number of the valid octets from the beginning of the AAL1 user data Þeld is speciÞed in the VOS (valid octet size) Þeld.
PAGE 830
Part IV. Communications Processor Module Table 29-19. AAL1 Protocol-Specific RCT Field Descriptions (Continued) Offset 0x18 Bits Name 0Ð3 Ñ 4 Reserved, should be cleared. SNEM 5Ð7 Ñ 8 Sequence number error ßag interrupt mask 0 This mode is disabled. 1 When an out-of-sequence error occurs, an RXB interrupt is sent to the interrupt queue even if RCT[RXBM] is cleared.
PAGE 831
Part IV. Communications Processor Module Table 29-20. AAL0-Specific RCT Field Descriptions (Continued) Offset 0x18 Bits Name 0Ð7 Ñ 8 RXBM 9Ð15 Ñ Description Reserved, should be cleared. Receive buffer interrupt mask 0 The receive buffer event of this channel is masked. (The RXB event is not sent to the interrupt queue when receive buffers are closed.) 1 The receive buffer event of this channel is enabled. Reserved, should be cleared. 29.10.2.
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Part IV. Communications Processor Module Table 29-21. TCT Field Descriptions Offset 0x00 Bits 0Ð1 Ñ Description Reserved, should be cleared. 2 GBL Global. Asserting GBL enables snooping of data buffers, BDs, interrupt queues and free buffer pool. 3Ð4 BO Byte ordering. This Þeld is used for data buffers. 00 Reserved 01 Power PC little endian 1x Big endian 5 Ñ Reserved, should be cleared. 6 DTB Data buffer bus 0 Reside on the 60x bus. 1 Reside on the local bus.
PAGE 833
Part IV. Communications Processor Module Table 29-21. TCT Field Descriptions (Continued) Offset 0x02 Bits Name 0 Ñ 1 INF 2Ð11 12 13Ð15 Description Internal use only. Initialize to 0. Used for AAL5 Only. Indicates the transmitter state. Initialize to 0 0 In idle state. 1 In AAL5 frame transmission state. Ñ Internal use only. Initialize to 0. ABRF Used for AAL5 Only. 0 ABR Flow control is disabled. 1 ABR Flow control is enabled. AAL AAL type 000 AAL0ÑSegmentation without any adaptation layer.
PAGE 834
Part IV. Communications Processor Module Table 29-21. TCT Field Descriptions (Continued) Offset 0x1E Bits Name Description 14 IMK Interrupt mask. Can be changed on-the-ßy. 0 The transmit buffer event of this channel is masked. (TXB event is not sent to the interrupt queue.) 1 The transmit buffer event of this channel is enabled. 15 PM Performance monitoring. Can be changed on-the-ßy. 0 No performance monitoring for this VC. 1 Performance is monitored for this VC.
PAGE 835
Part IV. Communications Processor Module Table 29-23 describes AAL1 protocol-speciÞc TCT Þelds. Table 29-23. AAL1-Specific TCT Field Descriptions Offset 0x10 0x12 0x14 Bits Name Description 0-1 Ñ 2Ð7 VOS Valid octet size. Partially Þlled cell mode only. SpeciÞes the number of valid octets from the beginning of the AAL1 user data Þeld. For unstructured service, values 1-47 are valid; for structured service, values 1-46 are valid. 8 PFM Partially Þlled mode.
PAGE 836
Part IV. Communications Processor Module Table 29-24 describes AAL0 protocol-speciÞc TCT Þelds. Table 29-24. AAL0-Specific TCT Field Descriptions Offset Bits 0x10 0x12Ð 0x14 Name Description 0Ð7 Ñ Reserved, should be cleared. 8 0 Must be 0. 9 CR10 10 Ñ 11 ACHC CRC-10 0 CRC10 insertion is disabled. 1 CRC10 insertion is enabled. Reserved, should be cleared. ATM cell header change 0 Normal operation ATM cell header is taken from AAL0 buffer. 1 VPI/VCI (28 bits) are taken from TCT.
PAGE 837
Part IV. Communications Processor Module Table 29-25. VBR-Specific TCTE Field Descriptions (Continued) Offset Bits 0x06 0Ð7 8Ð15 0x08 Ñ 0x0C 0 Name Description SRR Sustain rate remainder. Holds the sustain rate remainder after adding the pace fraction Þeld to the additive channel sustain rate. Used by the APC to calculate the channel GCRA (leaky bucket) state. Initialized to 0. SCRF Holds the sustain cell rate fraction of this channel in units of 1/256 slot. SR Sustain rate.
PAGE 838
Part IV. Communications Processor Module 29.10.2.3.6 ABR Protocol-SpeciÞc TCTE Figure 29-36 shows the ABR protocol-speciÞc TCTE.
PAGE 839
Part IV. Communications Processor Module Table 29-27. ABR-Specific TCTE Field Descriptions (Continued) Offset Bits 4Ð6 7 Name Ñ CP-TA 8Ð9 Ñ 10 CI-VC 11Ð15 Ñ 0x08 Ñ 0x0A Ñ 0x0C Ñ ACR 0x0E 0 ACRC 1Ð15 MCR Description Reserved, should be cleared. Cell loss priorityÐturn-around cell. Holds the CLP of the last received F-RM cell. If another F-RM cell arrives before the previous one was turned around, CP-TA is overwritten by the new RM cellÕs CLP. Reserved, should be cleared.
PAGE 840
Part IV. Communications Processor Module 29.10.3 OAM Performance Monitoring Tables The OAM performance monitoring tables include performance monitoring block test parameters, as shown in Figure 29-37. Each block test needs a 32-byte performance monitoring table in the dual-port RAM. In the connectionÕs RCT and TCT, the user allocates an OAM performance table to a VCC or VPC. See Section 29.6.6, ÒPerformance Monitoring.Ó PMT_BASE in the parameter RAM points to the base address of the tables.
PAGE 841
Part IV. Communications Processor Module Table 29-28. OAMÑPerformance Monitoring Table Field Descriptions Offset Bits Name 0x00 0 FMCE Enables FMC transmission. Initialize to 1. 1 TSTE FMC time stamp enable 0 The time stamp Þeld of the FMC is coded with all 1Õs. 1 The value of the time stamp timer is inserted into the time stamp Þeld of the FMC. 0x02 0x04 2Ð4 Ñ 5Ð15 TCC 0Ð4 Ñ 5Ð15 BLCKSIZE Ñ Description Reserved, should be cleared. TX cell count.
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Part IV.
PAGE 843
Part IV. Communications Processor Module Table 29-29. APC Parameter Table (Continued) Offset1 0x0A Name Width Description LINE_RATE_AB Hword ABR only. The PHY line rate in cells/sec, represented in TM 4.0 ßoating-point R format. User-deÞned. 0xC REAL_TSTP Word Real-time stamp pointer used internally by the APC. Initialize to 0. 0x10 APC_STATE Word Used internally by the APC. Initialize to 0. 1Offset values are to APCP_BASE+PHY# ´ 32.
PAGE 844
Part IV. Communications Processor Module Table 29-31 describes control slot Þelds. Table 29-31. Control Slot Field Description Bits 0 Name Description TCTE Used for external channels only. 0 Channels in this scheduling table do not use external TCTE. (No external VBR, ABR, UBR+ channels) 1 Channels in this scheduling table use external TCTE. (External VBR, ABR, UBR+ channels) 1Ð15 Ñ Reserved, should be cleared. 29.10.
PAGE 845
Part IV.
PAGE 846
Part IV.
PAGE 847
Part IV. Communications Processor Module Ch1 RxBD Table RBD_BASE RBD_Offset 0 1 1 1 1 Free Buffer Pool 1 FBP1_BASE FBP1_PTR Pointer 1 Pointer 2 Pointer 3 Pointer 4 Pointer 5 Pointer 6 BD 1 BD 2 BD 3 BD 4 BD 5 Buffer 1 of FBP1 Buffer 2 of FBP1 Ch4 RxBD Table Buffer 4 RBD_BASE, RBD_Offset Buffer 5 1 1 1 1 Buffer 6 BD 1 BD 2 BD 3 BD 4 Buffer 3 of FBP1 Notes: Buffers 2 and 3 are receiving data. After buffer 1 is processed, it can be returned to the pool. Figure 29-43.
PAGE 848
Part IV. Communications Processor Module Offset + 0x00 0 1 2 3 V Ñ W I 4 5 6 7 8 9 10 11 12 13 14 15 Buffer Pointer (BP) Offset + 0x02 Buffer Pointer (BP) Figure 29-45. Free Buffer Pool Entry Table 29-32 describes free buffer pool entry Þelds. Table 29-32. Free Buffer Pool Entry Field Descriptions Offset Bits 0x00 0 V Valid buffer entry. 0 This free buffer pool entry contains an invalid buffer pointer. 1 This free buffer pool entry contains a valid buffer pointer.
PAGE 849
Part IV. Communications Processor Module Table 29-33. Free Buffer Pool Parameter Table (Continued) Offset 1 Bits 8 Name Description EPD Early packet discard. 0 Normal operation. 1 AAL5 frames in progress are received, but new AAL5 frames associated with this pool are discarded. Can be used to implement EPD under core control. 9Ð15 0x0C 1Offset Ñ Ñ Reserved, should be cleared. FBP_ENTRY Free buffer pool entry. Initialize with the Þrst entry of the free buffer pool.
PAGE 850
Part IV. Communications Processor Module Table 29-35 describes AAL5 RxBD Þelds. Table 29-35. AAL5 RxBD Field Descriptions Offset Bits 0x00 29-70 Name Description 0 E Empty. 0 The buffer associated with this RxBD is full or data reception was aborted due to an error. The core can read or write any Þelds of this RxBD. The CP does not use this BD again while E remains zero. 1 The buffer associated with this RxBD is empty or reception is in progress.
PAGE 851
Part IV. Communications Processor Module Table 29-35. AAL5 RxBD Field Descriptions (Continued) Offset Bits 0x02 0x04 Ñ Name Description DL Data length. The number of octets written by the CP into this BDÕs buffer. It is written by the CP once the BD is closed. In the last BD of a frame, DL contains the total frame length. RXDBPTR Rx data buffer pointer. Points to the Þrst location of the associated buffer; may reside in internal or external memory. This pointer must be burst-aligned. 29.10.5.
PAGE 852
Part IV. Communications Processor Module Table 29-36 describes AAL1 RxBD Þelds. Table 29-36. AAL1 RxBD Field Descriptions Offset Name Description 0 E Empty 0 The buffer associated with this RxBD is Þlled with received data or data reception was aborted due to an error. The core can read or write any Þelds of this RxBD. The CP cannot use this BD again while E = 0. 1 The buffer is not full. This RxBD and its associated receive buffer are owned by the CP.
PAGE 853
Part IV. Communications Processor Module Table 29-37 describes AAL0 RxBD Þelds. Table 29-37. AAL0 RxBD Field Descriptions Offset 0x00 Bits Name Description 0 E Empty 0 The buffer associated with this RxBD is Þlled with received data, or data reception was aborted due to an error. The core can examine or write to any Þelds of this RxBD. The CP does not use this BD again while E remains zero. 1 The Rx buffer is empty or reception is in progress.
PAGE 854
Part IV. Communications Processor Module Offset + 0x08 Extra Cell Header. Used to store the user-deÞned cellÕs extra cell header. The extra cell header can be 1Ð12 bytes long. Offset + 0x14 Reserved (12 bytes) Figure 29-49. User-Defined CellÑRxBD Extension 29.10.5.8 AAL5 TxBDs Figure 29-50 shows the AAL5 TxBD.
PAGE 855
Part IV. Communications Processor Module Table 29-38 describes AAL5 TxBD Þelds. Table 29-38. AAL5 TxBD Field Descriptions Offset 0x00 Bits Name Description 0 R Ready 0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated buffer. The CP clears R after the buffer is sent or after an error condition is encountered. 1 The user-prepared buffer has not been sent or is currently being sent.
PAGE 856
Part IV. Communications Processor Module 29.10.5.9 AAL1 TxBDs Figure 29-51 shows the AAL1 TxBD. Offset + 0x00 0 1 2 3 R Ñ W I 4 5 Ñ 6 7 8 9 10 CM 11 12 13 14 15 Ñ Offset + 0x02 Data Length (DL) Offset + 0x04 Tx Data Buffer Pointer (TXDBPTR) Offset + 0x06 Figure 29-51. AAL1 TxBD Table 29-39 describes AAL1 TxBD Þelds. Table 29-39. AAL1 TxBD Field Descriptions Offset 0x00 Bits Name Description 0 R Ready 0 The buffer associated with this BD is not ready for transmission.
PAGE 857
Part IV. Communications Processor Module 29.10.5.10 AAL0 TxBDs Figure 29-52 shows AAL0 TxBDs. Note that the data length Þeld is calculated internally as 52 bytes, plus the extra header length (deÞned in FPSMR[TEHS]) when in UDC mode. Offset + 0x00 0 1 2 3 R Ñ W I 4 5 Ñ 6 7 8 CM 9 10 Ñ Offset + 0x02 Ñ Offset + 0x04 Tx Data Buffer Pointer (TXDBPTR) 11 OAM 12 13 14 15 Ñ Offset + 0x06 Figure 29-52. AAL0 TxBDs Table 29-40 describes AAL0 TxBD Þelds. Table 29-40.
PAGE 858
Part IV. Communications Processor Module 29.10.5.11 AAL5, AAL1 User-DeÞned CellÑTxBD Extension In user-deÞned cell mode, the AAL5 and AAL1 TxBDs are extended to 32 bytes; see Figure 29-53. Note that for AAL0 a complete cell, including the UDC header, is stored in the buffer; the AAL0 BD size is always 8 bytes. Offset + 0x08 Extra Cell Header. Used to store the user-deÞned cellÕs extra cell header. The extra cell header can be 1Ð12 bytes long. Offset + 0x14 Reserved (12 bytes) Figure 29-53.
PAGE 859
Part IV. Communications Processor Module Table 29-41. UNI Statistics Table Offset1 Name Width Description 0x00 UTOPIAE Hword Counts cells dropped as a result of UTOPIA parity error or state machine errors (short or long cells). 0x02 MIC_COUNT Hword Counts misinserted cells dropped as a result of address look-up failure. 0x04 0x06 1Offset CRC10E_COUNT Hword Ñ Hword Counts cells dropped as a result of CRC10 failure. AAL5-ABR only. Reserved, should be cleared. from UNI_STATT_BASE+PHY# ´ 8 29.
PAGE 860
Part IV. Communications Processor Module Word INTQ_BASE Software (Core) Pointer INTQ_PTR V=0 W=0 Invalid V=0 W=0 Invalid V=0 W=0 Invalid V=1 W=0 Interrupt Entry V=1 W=0 Interrupt Entry V=1 W=0 Interrupt Entry V=0 W=0 Invalid V=0 W=0 Invalid V=0 W=1 Invalid Figure 29-55. Interrupt Queue Structure 29.11.2 Interrupt Queue Entry Each one-word interrupt queue entry provides detailed interrupt information to the host. Figure 29-56 shows an entry.
PAGE 861
Part IV. Communications Processor Module Table 29-42 describes interrupt queue entry Þelds. Table 29-42. Interrupt Queue Entry Field Description Offset Bits Name Description 0x00 0 V Valid interrupt entry 0 This interrupt queue entry is free and can be use by the CP. 1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit. 1 Ñ Reserved, should be cleared. 2 W Wrap bit. When set, this is the last interrupt circular table entry.
PAGE 862
Part IV. Communications Processor Module Table 29-43. Interrupt Queue Parameter Table (Continued) Offset 1 0x0C 1Offset Name Width INTQ_ENTRY Word Description Interrupt queue entry. Must be zero. Note that when an overrun occurs, this entry must be cleared again. from INTT_BASE+RCT/TCT[INTQ] ´ 16 29.12 The UTOPIA Interface The ATM controller interfaces with a PHY device through the UTOPIA interface. The MPC8260 supports UTOPIA level 2 for both master and slave modes. 29.12.
PAGE 863
Part IV. Communications Processor Module Table 29-44. UTOPIA Master Mode Signal Descriptions (Continued) Signal Description RxDATA[0Ð15] Carries receive data from the PHY to the ATM controller. RxDATA[15]/[7] is the msb when using /[0Ð7] UTOPIA 16/8, RxDATA[0] is the lsb. RxSOC Receive start of cell. Asserted by the PHY device as the Þrst byte of a cell is received on RxDATA. RxENB Receive enable.
PAGE 864
Part IV. Communications Processor Module Table 29-45 describes UTOPIA slave mode signals. Table 29-45. UTOPIA Slave Mode Signals Signal Description TxDATA[0Ð15] /[0Ð7] Transmit data bus. Carries transmit data from the ATM controller to the master device. TxDATA[15]/ [7] is the msb, TxDATA[0] is the lsb. TxSOC Transmit start of cell. Asserted by an ATM controller as the Þrst byte of a cell is sent on the TxDATA lines. TxENB Transmit enable. An input to the ATM controller.
PAGE 865
Part IV. Communications Processor Module 29.12.2.3 UTOPIA Loop-Back Modes The UTOPIA interface supports loop-back mode. In this mode, the Rx and Tx UTOPIA signals are shorted internally. Output pins are driven; input pins are ignored. Note that in loop-back mode, the transmitter and receiver must operate in complementary modes. For example, if the transmitter is master, the receiver must be a slave (FPSMR[TUMS] = 0, FPSMR[RUMS] = 1). Modes are selected through GFMR[DIAG], as shown in Table 29-46.
PAGE 866
Part IV. Communications Processor Module Bits Field 0 1 2 3 4 TEHS 5 6 7 REHS 8 9 ICD 11 TUMS RUMS Reset 0000_0000_0000_0000 R/W R/W Address 10 12 13 14 15 LAST PHY/PHY ID 0x11304 (FPSMR1), 0x11324 (FPSMR1), 0x11324 (FPSMR1) Bits 16 17 18 Field Ñ 19 20 21 TUDC RUDC RXP 22 23 TUMP Ñ 24 25 26 27 28 29 TSIZE RSIZE UPRM UPLM RUMP HECI Reset 0000_0000_0000_0000 R/W R/W Address 0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3) 30 31 Ñ Figure 29-59.
PAGE 867
Part IV. Communications Processor Module Table 29-47. FCC ATM Mode Register (FPSMR) (Continued) Bits Name Description 21 RxP 22 TUMP 23 Ñ 24 TSIZE Transmit UTOPIA data bus size 0 UTOPIA 8-bit data bus size. 1 UTOPIA 16-bit data bus size. 25 RSIZE Receive UTOPIA data bus size 0 UTOPIA 8-bit data bus size. 1 UTOPIA 16-bit data bus size. 26 UPRM UTOPIA priority mode. 0 Round robin. Polling is done from PHY zero to the PHY speciÞed in LAST PHY.
PAGE 868
Part IV. Communications Processor Module Bits 0 1 Field 2 Ñ 3 4 5 6 7 8 9 10 11 12 13 14 15 TIRU GRLI GBPB GINT3 GINT2 GINT1 GINT0 INTO3 INTO2 INTO1 INTO0 Reset 0000_0000_0000_0000 R/W R/W Address 0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/ 0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3) Figure 29-60. ATM Event Register (FCCE)/FCC Mask Register (FCCM) Table 29-48 describes FCCE Þelds. Table 29-48.
PAGE 869
Part IV. Communications Processor Module Bits 0 Field TRM 1 2 3 4 5 6 7 Initial Value Reset 0000_0000 R/W R/W Address FCC1: 0x1131F (FTIRR1_PHY0), 0x1131D (FTIRR1_PHY1), 0x1131E (FTIRR1_PHY2), 0x1131F (FTIRR1_PHY3) FCC2: 0x1133F (FTIRR2_PHY0), 0x1133D (FTIRR2_PHY1), 0x1133E (FTIRR2_PHY2), 0x1133F (FTIRR2_PHY3) Figure 29-61. FCC Transmit Internal Rate Registers (FTIRRx) Table 29-49 describes FTIRRx Þelds. Table 29-49.
PAGE 870
Part IV. Communications Processor Module See also Section 29.16.1, ÒUsing Transmit Internal Rate Mode.Ó 29.14 ATM Transmit Command The CPM command set includes an ATM TRANSMIT that can be sent to the CP command register (CPCR), described in Section 13.4.1. The ATM TRANSMIT command (CPCR[opcode] = 0b1010, CPCR[SBC[code]] = 0b01110, CPCR[SBC[page]] = 0b00100 or 0b00101 (FCC1 or FCC2), CPCR[MCN] = 0b0000_1010) turns a passive channel into an active channel by inserting it into the APC scheduling table.
PAGE 871
Part IV. Communications Processor Module 29.15 SRTS Generation and Clock Recovery Using External Logic The MPC8260 supports SRTS generation using external logic. If SRTS generation is enabled (TCT[SRT] = 1), the MPC8260 reads SRTS[0Ð3] from the external SRTS logic and inserts it into 4 cells whose SN Þelds equal 1, 3, 5, and 7, as shown in Figure 29-64. External SRTS Logic (N=3008 bits = 8 SAR PDU) fs Counter divided by N SRTS Latch 2.43 MHz (E1/T1) 155.
PAGE 872
Part IV. Communications Processor Module External SRTS Logic (N=3008 bits = 8 SAR PDU) fs SRTS Counter divided by N Latch 2.43 MHz (E1/T1) 155.52 MHz 1/64 p = 4 bit counter VCO SRTS Diff + Latch DMA writes new SRTS code SN=1 SN=3 SN=5 SN=7 Figure 29-65. AAL1 SRTS Clock Recovery Using External Logic On every eighth cell, the MPC8260 writes a new SRTS code to the external logic using the bus selected in RCT[BIB]. The CP writes the SRTS code using a DMA write cycle of 1byte data size.
PAGE 873
Part IV. Communications Processor Module For example, suppose a system uses a 155.52-Mbps OC-3 device as PHY0, but the maximum required data rate is only 100 Mbps. In transmit internal rate mode, the user can conÞgure the internal rate mechanism to clock the ATM transmitter at a cell rate of 100 Mbps.
PAGE 874
Part IV.
PAGE 875
Chapter 30 Fast Ethernet Controller 300 300 The Ethernet IEEE 802.3 protocol is a widely-used LAN based on the carrier-sense multiple access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3 protocols are similar and can coexist on the same LAN, both are referred to as Ethernet in this manual, unless otherwise noted. Ethernet/IEEE 802.3 frames are based on the frame structure shown in Figure 30-1.
PAGE 876
Part IV. Communications Processor Module on the LAN. If a collision is detected, the station forces a jam signal (all ones) on its frame and stops transmitting. Collisions usually occur close to the beginning of a frame. The station then waits a random time period (backoff) before attempting to send again. When the backoff completes, the station waits for silence on the LAN and then begins retransmission on the LAN. This process is called a retry.
PAGE 877
Part IV. Communications Processor Module Control Registers Random No. 60x-Bus Slot Time And Defer Counter Clock Generator Peripheral Bus RX_CLK TX_CLK Internal Clocks RX_ER RX_DV COL CRS Receiver Control UNIT RXD[3Ð0] Receive Data FIFO Transmit Data FIFO Shifter Shifter TX_ER TX_EN COL CRS Transmitter Control Unit TXD[3Ð0] Figure 30-2. Ethernet Block Diagram 30.
PAGE 878
Part IV. Communications Processor Module ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ Multibuffer data structure Supports 48-bit addresses in three modes Ñ Physical. One 48-bit address recognized or 64-bin hash table for physical addresses Ñ Logical. 64-bin group address hash table plus broadcast address checking Ñ Promiscuous.
PAGE 879
Part IV.
PAGE 880
Part IV. Communications Processor Module frame delimiter, and frame information are sent in that order; see Figure 30-1. In fullduplex mode, since collisions are ignored, frame transmission maintains only the interframe gap (96 serial clocks) regardless of CRS. There is one internal buffer for out-of-sequence ßow control frames (in full-duplex Fast Ethernet). When the Fast Ethernet controller is between frames, this buffer is polled if ßow control is enabled. This buffer must contain the whole frame.
PAGE 881
Part IV. Communications Processor Module 30.5 Ethernet Channel Frame Reception The Ethernet receiver is designed to work with almost no core intervention and can perform address recognition, CRC checking, short frame checking, maximum DMA transfer checking, and maximum frame-length checking. When the core enables the Ethernet receiver, it enters hunt mode when RX_DV is asserted as long as COL remains negated (full-duplex mode ignores COL).
PAGE 882
Part IV. Communications Processor Module Ethernet controller then waits for a new frame. The Ethernet controller receives serial data least-signiÞcant nibble Þrst. 30.6 Flow Control Because collisions cannot occur in full-duplex mode, Fast Ethernet can operate at the maximum rate. When the rate becomes too fast for a stationÕs receiver, the stationÕs transmitter can send ßow-control frames to reduce the rate. Flow-control instructions are transferred by special frames of minimum frame size.
PAGE 883
Part IV. Communications Processor Module 30.8 Ethernet Parameter RAM For Ethernet mode, the protocol-speciÞc area of the FCC parameter RAM is mapped as in Table 30-2. Table 30-2. Ethernet-Specific Parameter RAM Offset1 Name Width 0x3C STAT_BUF Word Buffer of internal usage 0x40 CAM_PTR Word CAM address 0x44 C_MASK Word Constant MASK for CRC (initialize to 0xDEBB_20E3). For the 32-bit CRC-CCITT. 0x48 C_PRES Word Preset CRC (initialize to 0xFFFF_FFFF). For the 32-bit CRC-CCITT.
PAGE 884
Part IV. Communications Processor Module Table 30-2. Ethernet-Specific Parameter RAM (Continued) Offset1 0x72 Name Width PADDR1_H Hword The 48-bit individual address of this station. PADDR1_L is the lowest order halfword, and PADDR1_H is the highest order half-word.
PAGE 885
Part IV. Communications Processor Module Table 30-2. Ethernet-Specific Parameter RAM (Continued) Offset1 Name 0xBA MAXD2 0xBC MAXD 0xBE DMA_CNT 0xC0 OCTC 2 Word (RMON mode only) The total number of octets of data (including those in bad packets) received on the network (excluding framing bits but including FCS octets). 0xC4 COLC 2 Word (RMON mode only) The best estimate of the total number of collisions on this Ethernet segment.
PAGE 886
Part IV. Communications Processor Module Table 30-2. Ethernet-Specific Parameter RAM (Continued) Offset1 Name Width 0xE8 P128C 2 Word (RMON mode only) The total number of packets (including bad packets) received that were between 128 and 255 octets long inclusive (excluding framing bits but including FCS octets).
PAGE 887
Part IV. Communications Processor Module Table 30-3. Transmit Commands (Continued) Command Description COMMANDS:FA Used to smoothly stop transmission after the current frame Þnishes sending or undergoes a collision ST (immediately if there is no frame being sent). FCCE[GRA] is set once transmission stops. Then the COMMUNICATI Ethernet transmit parameters (including BDs) can be modiÞed by the user. The TBPTR points to the ONS next TxBD in the table.
PAGE 888
Part IV. Communications Processor Module 30.11 RMON Support The Fast Ethernet controller can automatically gather network statistics required for RMON without the need to receive all addresses using promiscuous mode. Setting FPSMRx[MON] enables RMON support. The RMON statistics and their corresponding counters in the parameter RAM are described in Table 30-5. Table 30-5.
PAGE 889
Part IV. Communications Processor Module Table 30-5. RMON Statistics and Counters (Continued) Statistic Description Counter etherStatsFragments The total number of packets received that were less than 64 octets long (excluding framing bits but including FCS octets) and had either a bad FCS with an integral number of octets (FCS error) or a bad FCS with a non-integral number of octets (alignment error).
PAGE 890
Part IV. Communications Processor Module Check Address G I I/G Address F Broadcast Addr T Broadcast Enabled F Hash Search Hash Search Use Group Table Use Individual Table T T T Receive Frame F Individual Addr Match? Match? F F T Promiscuous? T Use CAM? F T Discard Frame Rejected by CAM? F Start Receive Figure 30-4.
PAGE 891
Part IV. Communications Processor Module In the physical type of address recognition, the Ethernet controller compares the destination address Þeld of the received frame with the physical address that the user programs in the PADDR. If it fails, the controller performs address recognition on multiple individual addresses using the IADDR_H/L hash table.
PAGE 892
Part IV. Communications Processor Module NOTE The hash tables cannot be used to reject frames that match a set of selected addresses because unintended addresses can map to the same bit in the hash table. Thus, an external CAM must be used to implement this function. 30.14 Interpacket Gap Time The minimum interpacket gap time for back-to-back transmission is 96 serial clocks. The receiver receives back-to-back frames with this minimum spacing.
PAGE 893
Part IV. Communications Processor Module 30.17 Ethernet Error-Handling Procedure The Ethernet controller reports frame reception and transmission error conditions using the channel BDs, the error counters, and the FCC event register. Transmission errors are described in Table 30-6. Table 30-6. Transmission Errors Error Response Transmitter underrun The controller sends 32 bits that ensure a CRC error, terminates buffer transmission, closes the buffer, sets TxBD[UN] and FCCE[TXE].
PAGE 894
Part IV. Communications Processor Module 30.18.1 FCC Ethernet Mode Register (FPSMR) In Ethernet mode, the FCC protocol-speciÞc mode register, shown in Figure 30-5, functions as the Ethernet mode register.
PAGE 895
Part IV. Communications Processor Module Table 30-8. FPSMR Ethernet Field Descriptions (Continued) Bits Name Description 5 FDE Full duplex Ethernet 0 Disable full-duplex. 1 Enable full-duplex. Must be set if FSMR[LPB] is set or external loopback is performed. 6 MON RMON mode 0 Disable RMON mode. 1 Enable RMON mode. 7Ð8 Ñ Reserved, should be cleared. 9 PRO Promiscuous 0 Check the destination address of incoming frames. 1 Receive the frame regardless of its address.
PAGE 896
Part IV. Communications Processor Module affect bit values. Unmasked FCCE bits must be cleared before the CP clears the internal interrupt request. Bits 0 Field 1 2 3 4 5 6 7 8 Ñ 9 10 GRA RXC TXC 11 12 13 14 15 TXE RXF BSY TXB RXB Reset 0000_0000_0000_0000 R/W R/W Addr 0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/ 0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3) Figure 30-6. Ethernet Event Register (FCCE)/Mask Register (FCCM) Table 30-9 describes FCCE/FCCM Þelds.
PAGE 897
Part IV. Communications Processor Module Frame Received in Ethernet Stored in Rx Buffer Time RXD P SFD DA SA T/L Line Idle D CR Line Idle RX_DV Ethernet FCCE Events RXB RXF Notes: 1. RXB event assumes receive buffers are 64 bytes each. 2. The RXF interrupt may occur later than RX_DV due to receive FIFO latency. Frame Transmitted by Ethernet TXD Stored in Tx Buffer Line Idle P SFD DA SA T/L D CR Line Idle TX_EN COL Ethernet FCCE Events TXB TXB, GRA Notes: 1.
PAGE 898
Part IV. Communications Processor Module Offset + 0 0 1 2 3 4 5 6 E Ñ W I L F Ñ 7 8 9 10 11 12 13 14 15 M BC MC LG NO SH CR OV CL Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer Offset + 6 Figure 30-8. Fast Ethernet Receive Buffer (RxBD) Table 30-10 describes Ethernet RxBD Þelds. Table 30-10. RxBD Field Descriptions Bits Name Description 0 E Empty 0 The buffer associated with this RxBD is full or reception terminated due to an error.
PAGE 899
Part IV. Communications Processor Module Table 30-10. RxBD Field Descriptions (Continued) Bits Name Description 10 LG Rx frame length violation. A frame length greater than the MFLR (maximum frame length) deÞned for this FCC is recognized. 11 NO Rx nonoctet aligned frame. A frame that contained a number of bits not divisible by eight is received and the CRC check at the preceding byte boundary generated an error. 12 SH Short frame.
PAGE 900
Part IV. Communications Processor Module E Status 0 MRBLR = 64 Bytes for this FCC Buffer Receive BD 0 L F 0 1 Length 0x0040 Pointer 32-Bit Buffer Pointer Destination Address (6) Source Address (6) Buffer Full Type/Length (2) 64 Bytes Data Bytes (50) E Status 0 Receive BD 1 L F 1 Buffer 0 Length 0x0045 Pointer 32-Bit Buffer Pointer CRC Bytes (4) Buffer Closed after CRC Received.
PAGE 901
Part IV. Communications Processor Module Offset + 0 0 1 2 3 4 5 6 R PAD W I L TC DEF 7 8 9 HB LC RL Offset + 2 Data length Offset + 4 Tx data Buffer Pointer 10 11 12 RC 13 14 15 UN CSL Offset + 6 Figure 30-10. Fast Ethernet Transmit Buffer (TxBD) Table 30-11 describes Ethernet TxBD Þelds. Table 30-11.
PAGE 902
Part IV. Communications Processor Module Table 30-11. Ethernet TxBD Field Definitions (Continued) Field Name Description 10Ð13 RC Retry count. Indicates the number of retries required for this frame to be successfully sent. If RC = 0, the frame is sent correctly the Þrst time. If RC = 15 and RET_LIM = 15 in the parameter RAM, 15 retries were needed. If RC = 15 and RET_LIM > 15, 15 or more retries were needed. The Ethernet controller updates RC after sending the buffer. 14 UN Underrun.
PAGE 903
Chapter 31 FCC HDLC Controller 310 310 Layer 2 of the seven-layer OSI model is the data link layer (DLL), in which HDLC is one of the most common protocols. The framing structure of HDLC is shown in Figure 31-1. HDLC uses a zero insertion/deletion process (commonly known as bit stufÞng) to ensure that the bit pattern of the delimiter ßag does not occur in the Þelds between ßags.
PAGE 904
Part IV. Communications Processor Module 31.
PAGE 905
Part IV. Communications Processor Module To rearrange the transmit queue before the CP has sent all buffers, issue the STOP TRANSMIT command. This can be useful for sending expedited data before previously linked buffers or for error situations. When receiving the STOP TRANSMIT command, the HDLC controller aborts the current frame transmission and starts transmitting idles or ßags. When the HDLC controller is given the RESTART TRANSMIT command, it resumes transmission.
PAGE 906
Part IV. Communications Processor Module 31.4 HDLC Parameter RAM When an FCC operates in HDLC mode, the protocol-speciÞc area of the FCC parameter RAM is mapped with the HDLC-speciÞc parameters in Table 31-1. Table 31-1. FCC HDLC-Specific Parameter RAM Memory Map Offset1 Name 0x38 Ñ 0x44 C_MASK Word CRC constant. For the 16-bit CRC-CCITT, initialize C_MASK to 0x0000_F0B8. For the 32-bit CRC-CCITT, initialize C_MASK to 0xDEBB_20E3. 0x48 C_PRES Word CRC preset.
PAGE 907
Part IV. Communications Processor Module Figure 31-2 shows an example of using HMASK and HADDR[1Ð4]. 16-Bit Address Recognition Flag 0x7E Address 0x68 Address 0xAA Control 0x44 HMASK HADDR1 0xFFFF 0xAA68 HADDR2 HADDR3 HADDR4 8-Bit Address Recognition etc. Flag 0x7E Address 0x55 HADDR1 0x00FF 0xXX55 0xFFFF 0xAA68 HADDR2 0xXX55 HADDR3 0xXX55 0xAA68 HADDR4 0xXX55 Recognizes one 16-bit address (HADDR1) and the 16-bit broadcast address (HADDR2) HMASK Control 0x44 etc.
PAGE 908
Part IV. Communications Processor Module Table 31-2. Transmit Commands (Continued) Command RESTART TRANSMIT INIT TX PARAMETERS Description Enables character transmission on the transmit channel. This command is expected by the HDLC controller after a STOP TRANSMIT command, after a STOP TRANSMIT command is issued and the channel in its FCC mode register is disabled, after a GRACEFUL STOP TRANSMIT command, or after a transmitter error (underrun or CTS lost with no automatic frame retransmission).
PAGE 909
Part IV. Communications Processor Module Table 31-5 describes HDLC reception errors, which are reported through the RxBD. Table 31-5. HDLC Reception Errors Error Description Overrun Error The HDLC controller maintains an internal FIFO buffer for receiving data. The CP begins programming the SDMA channel and updating the CRC whenever data is received in the FIFO buffer.
PAGE 910
Part IV. Communications Processor Module Bits 0 Field 1 2 3 NOF 4 5 FSE MFF 6 7 8 9 Ñ 11 12 TS Reset 0000_0000_0000_0000 R/W R/W Addr 10 13 14 15 29 30 31 Ñ 0x11304 (FPSMR1), 0x11324 (FPSMR2), 0x11324 (FPSMR3) Bits 16 Field NBL 17 18 19 20 21 22 23 24 Ñ 25 26 27 28 CRC Reset 0000_0000_0000_0000 R/W R/W Addr 0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3) Ñ Figure 31-3. HDLC Mode Register (FPSMR) The FPSMR Þelds are described in Table 31-6.
PAGE 911
Part IV. Communications Processor Module Table 31-6. FPSMR Field Descriptions (Continued) Bits 24-25 26Ð31 Name Description CRC CRC selection 00 16-bit CCITT-CRC (HDLC). X16 + X12 + X5 + 1 01 Reserved 10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1 11 Reserved Ñ Reserved, should be cleared. 31.7 HDLC Receive Buffer Descriptor (RxBD) The HDLC controller uses the RxBD to report on data received for each buffer.
PAGE 912
Part IV.
PAGE 913
Part IV. Communications Processor Module Figure 31-5 shows the FCC HDLC RxBD. Offset + 0 0 1 2 3 4 5 6 E Ñ W I L F CM 7 8 9 Ñ Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer 10 11 12 13 14 15 LG NO AB CR OV CD Offset + 6 Figure 31-5. FCC HDLC Receive Buffer Descriptor (RxBD) Table 31-7 describes RxBD Þelds. Table 31-7. RxBD field Descriptions Bits Name 0 E Empty 0 The buffer is full with received data or data reception stopped because of an error.
PAGE 914
Part IV. Communications Processor Module Table 31-7. RxBD field Descriptions (Continued) Bits Name Description 11 NO Rx nonoctet-aligned frame. Set when a received frame contains a number of bits not divisible by eight. 12 AB Rx abort sequence. At least seven consecutive 1s are received during frame reception. 13 CR Rx CRC error. This frame contains a CRC error. Received CRC bytes are written to the receive buffer. 14 OV Overrun. A receiver overrun occurs during frame reception.
PAGE 915
Part IV. Communications Processor Module Table 31-8 describes HDLC TxBD Þelds. Table 31-8. HDLC TxBD Field Descriptions Bits Name Description 0 R Ready 0 The buffer associated with this BD is not ready for transmission. The user can manipulate this BD or its associated buffer. The CP clears R after the buffer has been sent or an error occurs. 1 The buffer is ready to be sent. The transmission may have begun, but it has not completed. The user cannot set Þelds in this BD once R is set.
PAGE 916
Part IV. Communications Processor Module The remaining TxBD parameters are as follows: ¥ Data length is the number of bytes the HDLC controller should transmit from this data buffer; it is never modiÞed by the CP. The value of this Þeld should be greater than zero. ¥ Tx data buffer pointer. The transmit buffer pointer, which contains the address of the associated data buffer, can be even or odd. The buffer can reside in internal or external memory. This value is never modiÞed by the CP. 31.
PAGE 917
Part IV. Communications Processor Module Table 31-9. FCCE/FCCM Field Descriptions Bits Name 0Ð7 Ñ 8 GRA 9Ð10 Ñ Description Reserved, should be cleared. Graceful stop complete. A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT command, is now complete. GRA is set as soon as the transmitter Þnishes transmitting any frame that is in progress when the command was issued. It is set immediately if no frame is in progress when the command is issued. Reserved, should be cleared.
PAGE 918
Part IV. Communications Processor Module Frame Received by HDLC Stored in Rx Buffer Time RXD Line Idle F F A A C I I I CR CR F Line Idle CD HDLC FCCE Events CD IDL FLG FLG RXB RXF FLG IDL FLG CD Notes: 1. RXB event assumes receive buffers are 6 bytes each. 2. The second IDL event occurs after 15 ones are received in a row. 3. The FLG interrupts show the beginning and end of flag reception. 4.
PAGE 919
Part IV. Communications Processor Module Table 31-10 describes FCCS bits. Table 31-10. FCCS Register Field Descriptions Bits Name Description 0Ð4 Ñ Reserved, should be cleared. 5 FG Flags. While FG is cleared, each time a new bit is received the most recently received 8 bits are examined to see if a ßag is present. FG is set as soon as an HDLC ßag (0x7E) is received on the line. Once FG is set, it remains set at least 8 bit times while the next 8 bits of input data are examined.
PAGE 920
Part IV.
PAGE 921
Chapter 32 FCC Transparent Controller 320 320 The FCC transparent controller functions as a high-speed serial-to-parallel and parallel-toserial converter. Transparent mode provides a clear channel on which the FCC performs no bit-level manipulationÑimplementing higher-level protocols would require software. Transparent mode is also referred to as a totally transparent or promiscuous operation.
PAGE 922
Part IV. Communications Processor Module 32.1 Features The following is a list of the transparent controllerÕs important features: ¥ Flexible data buffers ¥ Automatic SYNC detection on receive Ñ 16-bit pattern Ñ 8-bit pattern Ñ Automatic sync (always synchronized) Ñ External sync signal support ¥ ¥ ¥ ¥ CRCs can optionally be transmitted and received Reverse data mode Another protocol can be performed on the FCCÕs other half (transmitter or receiver) during transparent mode External BD table 32.
PAGE 923
Part IV. Communications Processor Module 32.3.1 In-Line Synchronization Pattern The transparent channel can be programmed to transmit and receive a synchronization pattern if GFMR[SYNL] ¹ 0; see Section 28.2, ÒGeneral FCC Mode Registers (GFMRx).Ó The pattern is deÞned in the FDSR; see Section 28.4, ÒFCC Data Synchronization Registers (FDSRx).Ó GFMR[SYNL] deÞnes the SYNC pattern length. The synchronization pattern is shown in Figure 32-1.
PAGE 924
Part IV. Communications Processor Module 32.3.3 Transparent Synchronization Example Figure 32-2 shows an example of synchronization using external signals. MPC8260 A MPC8260 B TXD RXD RTS CD CLKx BRGOx RXD TXD CD RTS CLKx BRGOx BRGOx (Output is CLKx Input) TXD (Output is RXD Input) RTS (Output is CD Input) First Bit of Frame Data Last Bit of Frame Data or CRC TxBD[L] = 1 Causes Negation of RTS CD Lost Condition Terminates Reception of Frame Notes: 1.
PAGE 925
Chapter 33 Serial Peripheral Interface (SPI) 330 330 The serial peripheral interface (SPI) allows the MPC8260 to exchange data between other MPC8260 chips, the MPC860, the MC68360, the MC68302, the M68HC11 and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (receive, transmit, clock and slave select).
PAGE 926
Part IV. Communications Processor Module 33.
PAGE 927
Part IV. Communications Processor Module ¥ When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and transmitted data out through SPIMISO. SPISEL is the enable input to the SPI slave. In a multimaster environment, SPISEL (always an input) is used to detect an error when more than one master is operating. As described in Chapter 35, ÒParallel I/O Ports,Ó SPIMISO, SPIMOSI, SPICLK, and SPISEL are multiplexed with port B[28Ð31] signals, respectively.
PAGE 928
Part IV. Communications Processor Module To start exchanging data, the core writes the data to be sent into a buffer, conÞgures a TxBD with TxBD[R] set, and conÞgures one or more RxBDs. The core then sets SPCOM[STR] in the SPI command register to start sending data, which starts once the SDMA channel loads the Tx FIFO with data. The SPI then generates programmable clock pulses on SPICLK for each character and simultaneously shifts Tx data out on SPIMOSI and Rx data in on SPIMISO.
PAGE 929
Part IV. Communications Processor Module MPC8260 SPISEL0 SPISEL1 SPISEL2 SPISEL3 drivers of SPI signals. The core must clear SPMODE[EN] before the SPI is used again. After correcting the problems, clear SPIE[MME] and reenable the SPI.
PAGE 930
Part IV. Communications Processor Module The maximum sustained data rate that the SPI supports is SYSTEMCLK/50. However, the SPI can transfer a single character at much higher ratesÑSYSTEMCLK/4 in master mode and SYSTEMCLK/2 in slave mode. Gaps should be inserted between multiple characters to keep from exceeding the maximum sustained data rate. 33.4 Programming the SPI Registers The following sections describe the registers used in conÞguring and operating the SPI. 33.4.
PAGE 931
Part IV. Communications Processor Module Table 33-1. SPMODE Field Descriptions (Continued) Bits Name Description 7 EN Enable SPI. Do not change other SPMODE bits when EN is set. 0 The SPI is disabled. The SPI is in a reset state and consumes minimal power. The SPI BRG is not functioning and the input clock is disabled. 1 The SPI is enabled. ConÞgure SPIMOSI, SPIMISO, SPICLK, and SPISEL to connect to the SPI as described in Section 35.2, ÒPort Registers.
PAGE 932
Part IV. Communications Processor Module 33.4.1.1 SPI Examples with Different SPMODE[LEN] Values The examples below show how SPMODE[LEN] is used to determine character length. To help map the process, the conventions shown in Table 33-2 are used in the examples. Table 33-2. Example Conventions Convention Description gÐv Binary symbols x __ _ 1 Deleted bit 1 Original byte boundary 1 Original 4-bit boundary. Both __ and _ are used to aid readability.
PAGE 933
Part IV. Communications Processor Module the data string selected is: msb r_stuv__ghij_klmn lsb with REV=0, the string transmitted, a byte at a time with lsb first is: first vuts_r__nmlk_jihg last with REV=1, the string is half-word reversed: msb nmlk_jihg__vuts_r and transmitted a byte at a time with lsb first: first ghij_klmn__r_stuv lsb last 33.4.2 SPI Event/Mask Registers (SPIE/SPIM) The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI.
PAGE 934
Part IV. Communications Processor Module Bit 0 Field STR 1 2 3 4 5 6 7 Ñ Reset 0000_0000 R/W Write Only Addr 0x11AAD Figure 33-8. SPCOMÑSPI Command Register Table 33-4 describes the SPCOM Þelds. Table 33-4. SPCOM Field Descriptions Bits Name Description 0 STR Start transmit. For an SPI master, setting STR causes the SPI to start transferring data to and from the Tx/Rx buffers if they are prepared.
PAGE 935
Part IV. Communications Processor Module Table 33-5. SPI Parameter RAM Memory Map (Continued) Offset 1 1 2 Name Width Description 0x06 MRBLR Hword Maximum receive buffer length. The SPI has one MRBLR entry to deÞne the maximum number of bytes the MPC8260 writes to a Rx buffer before moving to the next buffer. The MPC8260 can write fewer bytes than MRBLR if an error or end-of-frame occurs, but never exceeds the MRBLR value. User-supplied buffers should be no smaller than MRBLR.
PAGE 936
Part IV. Communications Processor Module 33.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR) Figure 33-9 shows the Þelds in the receive/transmit function code registers (RFCR/TFCR) Bit 0 Field 1 Ñ 2 3 4 GBL Reset BO 5 6 7 TC2 DTB Ñ 0000_0000 R/W R/W Addr SPI Base + 04 (RFCR)/SPI Base + 05 (TFCR) Figure 33-9. RFCR/TFCRÑFunction Code Registers Table 33-6 describes the RFCR/TFCR Þelds. Table 33-6.
PAGE 937
Part IV. Communications Processor Module Table 33-7. SPI Commands (Continued) Command INIT RX PARAMETERS Description Initializes all receive parameters in the parameter RAM to their reset state. Should be issued only when the receiver is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset both the Tx and Rx parameters. 33.7 The SPI Buffer Descriptor (BD) Table As shown in Figure 33-10, BDs are organized into separate RxBD and TxBD tables in dualport RAM.
PAGE 938
Part IV. Communications Processor Module than 8 bits, the data length should be even. For example, to send three characters of 8-bit data, 1 start, and 1 stop, the data length Þeld should be initialized to 3. However, to send three characters of 9-bit data, the data length Þeld should be initialized to 6 since the three 9-bit data Þelds occupy three half-words in memory. The CP never modiÞes this Þeld. ¥ The word at offset + 4 points to the beginning of the buffer.
PAGE 939
Part IV. Communications Processor Module Table 33-8. SPI RxBD Status and Control Field Descriptions (Continued) Bits Name Description 4 L Last. Updated by the SPI when the buffer is closed because SPISEL was negated (slave mode only). Otherwise, RxBD[ME] is set. The SPI updates L after received data is placed in the buffer. 0 This buffer does not contain the last character of the message. 1 This buffer contains the last character of the message. 5 Ñ Reserved, should be cleared.
PAGE 940
Part IV. Communications Processor Module Table 33-9. SPI TxBD Status and Control Field Descriptions (Continued) Bits Name Description 2 W Wrap (last BD in TxBD table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data using the BD pointed to by TBASE (top of the table). The number of BDs in this table is determined only by the W bit and overall space constraints of the dual-port RAM. 3 I Interrupt.
PAGE 941
Part IV. Communications Processor Module 8. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains Þve 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer]. 9. Execute the INIT RX AND TX PARAMETERS command by writing 0x2541_0000 to CPCR. 10. Write 0xFF to SPIE to clear any previous events. 11. Write 0x37 to SPIM to enable all possible SPI interrupts. 12.
PAGE 942
Part IV. Communications Processor Module remains open. If the master sends 5 or more bytes, the TxBD is closed after the Þfth byte. If the master sends 16 bytes and negates SPISEL, the RxBD is closed without triggering an out-of-buffers error. If the master sends more than 16 bytes, the RxBD is closed (full) and an out-of-buffers error occurs after the 17th byte is received. 33.10 Handling Interrupts in the SPI The following sequence should be followed to handle interrupts in the SPI: 1.
PAGE 943
Chapter 34 I2C Controller 340 340 The inter-integrated circuit (I2C¨) controller lets the MPC8260 exchange data with other I2C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCD displays. The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. It uses two signalsÑserial data (SDA) and serial clock (SCL)Ñto carry information between the integrated circuits connected to it.
PAGE 944
Part IV. Communications Processor Module The I2C receiver and transmitter are double-buffered, which corresponds to an effective two-character FIFO latency. In normal operation, the transmitter shifts the msb (bit 0) out Þrst. When the I2C is not enabled in the I2C mode register (I2MOD[EN] = 0), it consumes little power. 34.
PAGE 945
Part IV. Communications Processor Module When the I2C controller is master, the SCL clock output, taken directly from the I2C BRG, shifts receive data in and transmit data out through SDA. The transmitter arbitrates for the bus during transmission and aborts if it loses arbitration. When the I2C controller is a slave, the SCL clock input shifts data in and out through SDA. The SCL frequency can range from DC to BRGCLK/48. 34.
PAGE 946
Part IV. Communications Processor Module 34.3.1 I2C Master Write (Slave Read) If the MPC8260 is the master, prepare the transmit buffers and BDs before initiating a write. Initialize the Þrst transmit data byte with the slave address and write request (R/W = 0). If the MPC8260 is the slave target of the write, prepare receive buffers and BDs to await the masterÕs request. Figure 34-4 shows the timing for a master write.
PAGE 947
Part IV. Communications Processor Module If the MPC8260 is the slave target of the read, prepare the I2C transmit buffers and BDs and activate it by setting I2COM[STR]. Figure 34-5 shows the timing for a master read. N O S T A R T SDA Device Address A C R K S A T C O K P Data Byte Note: After the nth data byte, the master does not acknowledge the slave. Figure 34-5. I2C Master Read Timing A master read occurs as follows: 1. Set the masterÕs I2COM[STR] to initiate the read.
PAGE 948
Part IV. Communications Processor Module An MPC8260 I2C controller attempting a master read request could simultaneously be targeted for an external master write (slave read). Both operations trigger the controllerÕs I2CER[RXB] event, but only one operation wins the bus arbitration. To determine which operation caused the interrupt, software must verify that its transmit operation actually completed before assuming that the received data is the result of its read operation.
PAGE 949
Part IV. Communications Processor Module Table 34-1. I2MOD Field Descriptions (Continued) Bits Name Description 5Ð6 PDIV Predivider. Selects the clock division factor before it is input into the I2C BRG. The clock source for the I2C BRG is the BRGCLK generated from the CPM clock; see Section 9.8, ÒSystem Clock Control Register (SCCR).
PAGE 950
Part IV. Communications Processor Module Table 34-3 describes I2BRG Þelds. Table 34-3. I2BRG Field Descriptions Bits Name 0Ð7 DIV Description Division ratio 0Ð7. SpeciÞes the divide ratio of the BRG divider in the I2C clock generator. The output of the prescaler is divided by 2 * ([DIV0ÐDIV7] + 3) and the clock has a 50% duty cycle. DIV must be programmed to a minimum value of 3 if the digital Þlter is disabled and 6 if it is enabled. 34.4.
PAGE 951
Part IV. Communications Processor Module Bit 0 Field STR 1 2 3 4 5 Ñ 7 M/S Reset 0000_0000 R/W R/W Addr 6 0x1186C Figure 34-10. I2C Command Register (I2COM) Table 34-5 describes I2COM Þelds. Table 34-5. I2COM Field Descriptions Bits Name Description 0 STR Start transmit. In master mode, setting STR causes the I2C controller to start sending data from the I2C Tx buffers if they are ready.
PAGE 952
Part IV. Communications Processor Module Table 34-6. I2C Parameter RAM Memory Map (Continued) Offset 1 Name Width Description 0x06 MRBLR Hword Maximum receive buffer length. DeÞnes the maximum number of bytes the MPC8260 writes to a Rx buffer before moving to the next buffer. The MPC8260 writes fewer bytes to the buffer than the MRBLR value if an error or end-of-frame occurs. Buffers should not be smaller than MRBLR.
PAGE 953
Part IV. Communications Processor Module Figure 34-11 shows the RFCR/TFCR bit Þelds. Bit 0 Field 1 2 GBL Reset 3 4 BO 5 6 7 TC2 DTB Ñ 0000_0000 R/W R/W Addr I2C_BASE + 04 (RFCR)/I2C_BASE + 05 (TFCR) Figure 34-11. I2C Function Code Registers (RFCR/TFCR) Table 34-7 describes the RFCR/TFCR bit Þelds. Table 34-7. RFCR/TFCR Field Descriptions Bits 0Ð1 2 Name Description Ñ Reserved, should be cleared.
PAGE 954
Part IV. Communications Processor Module 34.7 The I2C Buffer Descriptor (BD) Table As shown in Figure 34-12, buffer descriptors (BDs) are organized into separate RxBD and TxBD tables in dual-port RAM. The tables have the same basic conÞguration as for the SCCs and SMCs and form circular queues that determine the order buffers are transferred. The CP uses BDs to conÞrm reception and transmission or to indicate error conditions so that the core knows buffers have been serviced.
PAGE 955
Part IV. Communications Processor Module 34.7.1.1 I2C Receive Buffer Descriptor (RxBD) Using RxBDs, the CP reports on each buffer received, closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer when the current one is full. It closes the buffer when a stop or start condition is found on the I2C bus or when an overrun error occurs. The core should write RxBD bits before the I2C controller is enabled.
PAGE 956
Part IV. Communications Processor Module 34.7.1.2 I2C Transmit Buffer Descriptor (TxBD) Transmit data is arranged in buffers referenced by TxBDs in the TxBD table. The Þrst word of the TxBD, shown in Figure 34-14, contains status and control bits. Offset + 0 0 1 2 3 4 5 R Ñ W I L S 6 7 8 9 10 11 Ñ Offset + 2 Data Length Offset + 4 Tx Buffer Pointer 12 13 14 15 NAK UN CL Offset + 6 Figure 34-14. I2C TxBD Table 34-10 describes I2C TxBD status and control bits. Table 34-10.
PAGE 957
Chapter 35 Parallel I/O Ports 350 350 The CPM supports four general-purpose I/O portsÑports A, B, C, and D. Each pin in the I/O ports can be conÞgured as a general-purpose I/O signal or as a dedicated peripheral interface signal. Port C is unique in that 16 of its pins can generate interrupts to the interrupt controller. Each pin can be conÞgured as an input or output and has a latch for data output, read or written at any time, and conÞgured as general-purpose I/O or a dedicated peripheral pin.
PAGE 958
Part IV. Communications Processor Module 35.2 Port Registers Each port has four memory-mapped, read/write, 32-bit control registers. 35.2.1 Port Open-Drain Registers (PODRAÐPODRD) The port open-drain register (PODR), shown in Figure 35-1, indicates a normal or wiredOR conÞguration of the port pins.
PAGE 959
Part IV. Communications Processor Module to PDATx is still stored in the output latch, but is prevented from reaching the port pin. In this case, when PDATx is read, the state of the port pin is read.
PAGE 960
Part IV. Communications Processor Module 35.2.4 Port Pin Assignment Register (PPAR) The port pin assignment register (PPAR) is cleared at system reset.
PAGE 961
Part IV.
PAGE 962
Part IV. Communications Processor Module 35.3 Port Block Diagram Figure 35-6 shows the functional block diagram.
PAGE 963
Part IV. Communications Processor Module 35.4.1 General Purpose I/O Pins Each one of the port pins is independently conÞgured as a general-purpose I/O pin if the corresponding port pin assignment register (PPAR) bit is cleared. Each pin is conÞgured as a dedicated on-chip peripheral pin if the corresponding PPAR bit is set.When the port pin is conÞgured as a general-purpose I/O pin, the signal direction for that pin is determined by the corresponding control bit in the port data direction register (PDIR).
PAGE 964
Part IV. Communications Processor Module PD4 Secondary option for SMC2 RxD GND PA8 Primary option for SMC2 RxD 0 MUX 0 MUX Pin PD4 1 1 Pin PA8 PPARD[4] == 1 & PSORD[4] == 1 & PDIRD[4] == 0 to SMC2 RxD PPARA[8] == 1 & PSORA[8] == 0 & PDIRA[8] == 0 Figure 35-7. Primary and Secondary Option Programming In the tables below, the default value for a primary option is simply a reference to the secondary option.
PAGE 965
Part IV. Communications Processor Module Table 35-5.
PAGE 966
Part IV. Communications Processor Module Table 35-5. Port AÑDedicated Pin Assignment (PPARA = 1) (Continued) Pin Function PSORA = 0 Pin PDIRA = 1 (Output) PA18 PDIRA = 0 (Input) PSORA = 1 Default PDIRA = 0 (Input, or Default PDIRA = 1 (Output) Input Inout if SpeciÞed) Input FCC1: TxD[7] UTOPIA 8 FCC1: TxD[15] UTOPIA 16 FCC1: TxD[0] MII/HDLC/transp nibble FCC1: TxD HDLC/Transp PA17 FCC1: RxD[7] UTOPIA 8 FCC1: RxD[15] UTOPIA 16 FCC1: RxD[0] MII/HDLC/transp. nibble FCC1: RxD HDLC/transp.
PAGE 967
Part IV. Communications Processor Module Table 35-5.
PAGE 968
Part IV. Communications Processor Module Table 35-6 shows the port B pin assignments. Table 35-6.
PAGE 969
Part IV. Communications Processor Module Table 35-6. Port B Dedicated Pin Assignment (PPARB = 1) (Continued) Pin Function PSORB = 0 Pin PDIRB = 1 (Output) PDIRB = 0 (Input) PSORB = 1 Default PDIRB = 0 (Input or Default PDIRB = 1 (Output) Input Inout if SpeciÞed) Input PB20 FCC2: RxD[6] UTOPIA 8 FCC2: RxD[1] MII/HDLC/transp. nibble GND TDM_A1-L1TXD[1] Nibble TDM_D2: L1RSYNC GND PB19 FCC2: RxD[5] UTOPIA 8 FCC2: RxD[2] MII/HDLC/transp.
PAGE 970
Part IV. Communications Processor Module Table 35-6. Port B Dedicated Pin Assignment (PPARB = 1) (Continued) Pin Function PSORB = 0 Pin PSORB = 1 Default PDIRB = 0 (Input or Default PDIRB = 1 (Output) Input Inout if SpeciÞed) Input PDIRB = 1 (Output) PDIRB = 0 (Input) PB7 FCC3: TXD[0] MII/HDLC/transp. nibble FCC3: TXD HDLC/transp. serial FCC2: RxD[3] UTOPIA 8 (primary option) by PC10 PB6 FCC3: TXD[1] MII/HDLC/transp.
PAGE 971
Part IV. Communications Processor Module Table 35-7.
PAGE 972
Part IV. Communications Processor Module Table 35-7.
PAGE 973
Part IV. Communications Processor Module Table 35-8 shows the port D pin assignments. Table 35-8.
PAGE 974
Part IV. Communications Processor Module Table 35-8.
PAGE 975
Part IV. Communications Processor Module Table 35-8.
PAGE 976
Part IV. Communications Processor Module 4. Write the corresponding SIMR (mask register) bit with a 1 to allow interrupts to be generated to the core. 5. The pin value can be read at any time using PDATC. Note After connecting CTS or CD to the SCC/FCC, the user must also choose the normal operation mode in GSMR[DIAG] to enable and disable SCC/FCC transmission and reception with these pins. The IDMA-DREQ lines in ports C can assert an external request to the CP instead of asserting an interrupt to the core.
PAGE 977
Appendix A Register Quick Reference Guide A0 A0 This section provides a brief guide to the core registers. A.1 PowerPC RegistersÑUser Registers The implements the user-level registers deÞned by the PowerPC architecture except those required for supporting ßoating-point operations (the ßoating-point register Þle (FPRs) and the ßoating-point status and control register (FPSCR)). User-level, PowerPC registers are listed in Table A-1 and Table A-2. Table A-2 lists user-level special-purpose registers (SPRs).
PAGE 978
Appendixes A.2 PowerPC RegistersÑSupervisor Registers All supervisor-level registers implemented on the MPC8260 are SPRs, except for the machine state register (MSR), described in Table A-3. Table A-3. Supervisor-Level PowerPC Registers (Non-SPR) Description Name Machine state register MSR Comments Serialize Access See the Programming Environments Manual and MPC603e RISC Microprocessor UserÕs Manual Write fetch sync Table A-4 lists supervisor-level SPRs defined by the PowerPC architecture.
PAGE 979
Appendixes A.3 MPC8260-SpeciÞc SPRs Table A-2 and Table A-5 list SPRs speciÞc to the MPC8260. Supervisor-level registers are described in Table A-5. Table A-5.
PAGE 980
Appendixes A-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
PAGE 981
INDEX no-pipeline mode, 8-26 one-level pipeline mode, 8-26 overview, 8-1 pipeline control, 8-26 port size device interfaces, 8-17 processor state signals, 8-32 PSDMR register, 10-21 single-MPC8260 bus mode, 8-2 TBST signal, 8-13 TCn signals, 8-13 terminology, 8-1 TESCRx registers, 10-33 TLBISYNC input, 8-33 TSIZn signals, 8-13 TTn signals, 8-10 write cycle data bus contents, 8-19 60x bus memory controller, see Memory controller Numerics 603e features list, 2-3 60x bus 60x-compatible mode 60x-compatible bus
PAGE 982
INDEX VBR traffic, 29-12 command, 29-90 ATM-to-ATM data forwarding, 29-37 ATM-to-TDM interworking, 29-34 buffer descriptors, 29-64 exceptions, 29-79 external rate mode, 29-6 FCCE, 29-87 FCCM, 29-87 features list, 29-2 FPSMR, 29-85 FTIRRx, 29-88 GFMR register, 29-85 global mode entry (GMODE), 29-41 internal rate mode, 29-6 interrupt queues, 29-79 maximum performance configuration, 29-92 OAM performance monitoring, 29-29, 29-60 OAM support, 29-27 operations and maintenance (OAM) support, 29-27 overview, 29-4
PAGE 983
INDEX Byte stuffing, 22-1 Byte-select signals, 10-75 system interface unit (SIU) periodic interrupt timer, 4-5 SIU block diagram, 4-1 software watchdog timer, 4-7 system configuration/protection logic, 4-3 time counter (TMCNT), 4-5 system PLL, 9-5 timers, 17-1 Branch processing unit overview, 2-6 BRGCLK, 34-2 BRn (base registers), 10-14 BSYNC (BISYNC SYNC) register, 22-7 BUFCMD (external address and command buffers), 10-42 Buffer descriptors ATM controller receive, 29-65, 29-69 transmit, 29-64, 29-74 BISYN
PAGE 984
INDEX Communications processor (CP) block diagram, 13-5 execution from RAM, 13-7 features list, 13-4 interfacing with the core, 13-6 memory map, 3-9 microcode execution from RAM, 13-7 microcode revision number, 13-10 peripheral interface, 13-6 PowerPC core interface, 13-6 RCCR, 13-7 REV_NUM, 13-10 RTSCR, 13-9 RTSR, 13-10 Communications processor module (CPM) ATM controller AAL1 sequence number protection table, 29-78 AALn RxBD, 29-6, 29-69 AALn TxBD, 29-5, 29-74 ABR flow control, 29-8, 29-20 address compres
PAGE 985
INDEX command register example, 13-15 CPCR, 13-11 opcodes, 13-13 overview, 13-11 communications processor (CP) block diagram, 13-5 execution from RAM, 13-7 features list, 13-4 interfacing with the core, 13-6 microcode execution from RAM, 13-7 microcode revision number, 13-10 peripheral interface, 13-6 PowerPC core interface, 13-6 RCCR, 13-7 REV_NUM, 13-10 RTSCR, 13-9 RTSR, 13-10 CPM multiplexing logic (CMX) block diagram, 15-2 overview, 15-1 dual-port RAM accessing dual-port RAM, 13-15 block diagram, 13-15
PAGE 986
INDEX master write (slave read), 34-4 multi-master considerations, 34-5 parameter RAM, 34-9 programming model, 34-6 registers, 34-6 RxBD, 34-13 slave read (master write), 34-4 slave write (master read), 34-4 transfers, 34-3 TxBD, 34-14 IDMA emulation auto buffer, 18-15 buffer chaining, 18-15 buffers, 18-23 bus exceptions, 18-27 commands, 18-26 controlling 60x bus bandwidth, 18-12 DACKx, 18-13 DCM, 18-18 DONEx, 18-14 DREQx, 18-13 DTS/STS programming, 18-20 dual-address transfers, 18-10 edge-sensitive mode, 1
PAGE 987
INDEX overview, 18-1 PDTEA, 18-4 PDTEM, 18-4 programming model, 18-3 registers, 18-3 SDMR, 18-4 SDSR, 18-3 serial configuration, 13-3 serial peripheral interface (SPI) block diagram, 33-1 clocking and pin functions, 33-2 commands, 33-12 configuring the SPI, 33-3 features list, 33-2 interrupt handling, 33-18 master mode, 33-3 maximum receive buffer length (MRBLR), 33-11 multi-master operation, 33-4 parameter RAM, 33-10 programming example master, 33-16 slave, 33-17 programming model, 33-6 RxBD, 33-14 slave m
PAGE 988
INDEX CxTx (chip-select signals), 10-74 F D DCM (IDMA channel mode), 18-18 Digital phase-locked loop (DPLL) operation, 19-22 DSR (data synchronization register) overview, 19-9 UART mode, 20-11 Dual-port RAM accessing dual-port RAM, 13-15 block diagram, 13-15 buffer descriptors, 13-17 memory map, 13-16 overview, 13-15 parameter RAM, 13-17 E EAMUX (external address multiplexing) signal, 10-41 EDO interface connection, MPC8260 to 60x bus, 10-92 Ethernet mode fast communications controller (FCC) address reco
PAGE 989
INDEX new features supported, 10-2 multi-channel controllers (MCCs), 27-1 processor core, 2-3 RISC timer tables, 13-19 serial communications controllers (SCCs) AppleTalk mode, 25-2 BISYNC mode, 22-2 general list, 19-2 HDLC mode, 21-2 transparent mode, 23-1 UART mode, 20-2 serial interface, 14-3 serial management controllers (SMCs) general list, 26-2 transparent mode, 26-21 UART mode, 26-11 UART mode, features not supported, 26-10 serial peripheral interface (SPI), 33-2 timers, 17-2 FPSMR register Ethernet,
PAGE 990
INDEX H HDLC mode accessing the bus, 21-19 bus controller, 21-17 collision detection, 21-17, 21-20 commands, 21-5 delayed RTS mode, 21-21 error handling, 21-6 fast communications controllers (FCCs) bit stuffing, 31-1 error control, 31-1 error handling, 31-6 FCCE, 31-14 FCCM, 31-14 FCCS, 31-16 features list, 31-2 FPSMR, 31-7 frame reception, 31-3 frame transmission, 31-2 overview, 31-1 parameter RAM, 31-4 programming model, 31-5 receive commands, 31-6 reception errors, 31-7 RxBD, 31-9 transmission errors, 31
PAGE 991
INDEX MDR (memory data register), 10-28 Memory controller address checking, 10-8 address latch enable (ALE), 10-11 address space checking, 10-8 architecture overview, 10-5 atomic bus operation, 10-10, 10-10 basic architecture, 10-5 basic operation, 10-8 boot chip-select operation, 10-61 controlling the timing of GPL1, GPL2, and CSx, 10-68 CSx timing example, 10-68 delayed read, 10-10 EDO interface connection, MPC8260 to 60x bus, 10-92 error checking and correction (ECC), 10-9 external master support, 10-101
PAGE 992
INDEX programming model, 10-13 PSDVAL, 10-12, 10-57 register descriptions, 10-13 SDRAM machine (synchronous DRAM machine) address multiplexing, 10-37 bank interleaving, 10-36 BSMA bit, 10-37 commands, JEDEC-standard, 10-35 common features, 10-6 configuration example, 10-48 implementation differences with UPMs and GPCM, 10-7 JEDEC-standard commands, 10-35 MODE-SET command timing, 10-46 overview, 10-33 page mode support, 10-36 parameters activate-to-read/write interval, 10-39 column address to first data out,
PAGE 993
INDEX serial peripheral interace (SPI) master mode, 33-3 slow go, 17-2 transparent mode overview, 32-1 serial communications controllers (SCCs), 23-1 serial management controllers (SMCs), 26-20 UART mode serial communications controllers (SCCs), 20-1 serial management controllers (SMCs), 26-10 MPTPR (memory refresh timer prescaler register), 10-32 Multi-channel controllers (MCCs) CHAMR HDLC mode, 27-10 transparent mode, 27-13 channel extra parameters, 27-5 commands, 27-16 data structure organization, 27-2 e
PAGE 994
INDEX PPC_ALRH (60x bus arbitration high-level register), 4-28 PPC_ALRL (60x bus arbitration low-level register), 4-29 Programming examples serial communications controllers (SCCs) GSMR (general SCC mode register) AppleTalk mode, 25-3 HDLC bus protocol, 21-23 PSMR (protocol-specific mode register) AppleTalk mode, 25-4 TODR (transmit-on-demand register) AppleTalk mode, 25-4 transparent mode, 23-13 UART mode, 20-22 transparent mode NMSI programming example, 26-29 Promiscuous mode, see Transparent mode Promisc
PAGE 995
INDEX transparent mode, 23-9 UART mode, 20-13 quick reference guide, A-1 reset mode, 5-5 reset status, 5-4 RFCR, 19-15 RISC timer tables RTER, 13-21 RTMR, 13-21 TM_CMD, 13-20 SCCE BISYNC mode, 22-15 Ethernet mode, 24-21 transparent mode, 23-12 UART mode, 20-19 SCCM BISYNC mode, 22-15 Ethernet mode, 24-21 transparent mode, 23-12 UART mode, 20-19 SCCS BISYNC mode, 22-16 transparent mode, 23-13 UART mode, 20-21 SDMA channels LDTEA, 18-4 LDTEM, 18-4 PDTEA, 18-4 PDTEM, 18-4 SDMR, 18-4 SDSR, 18-3 serial interface
PAGE 996
INDEX TxBD, 26-33 serial peripheral interface (SPI) SPCOM, 33-9 SPIE, 33-9 SPIM, 33-9 SPMODE, 33-6 system interface unit (SIU) BCR, 4-25 IMMR, 4-34 L_TESCR1, 4-38 L_TESCR2, 4-39 LCL_ACR, 4-29 LCL_ALRH, 4-30 LCL_ALRL, 4-30 PISCR, 4-42 PITC, 4-43 PITR, 4-44 PPC_ACR, 4-28 PPC_ALRH, 4-28 PPC_ALRL, 4-29 SCPRR_H, 4-19 SCPRR_L, 4-20 SICR, 4-17 SIEXR, 4-24 SIMR_H, 4-22 SIMR_L, 4-22 SIPNR_H, 4-21 SIPNR_L, 4-21 SIPRR, 4-18 SIUMCR, 4-31 SIVEC, 4-23 SWR, 4-7 SWSR, 4-36 SYPCR, 4-35 TESCR1, 4-36 TESCR2, 4-37 TMCNT, 4-41
PAGE 997
INDEX sending synchronization sequence, 22-9 TxBD, 22-14 Ethernet mode address recognition, 24-11 collision handling, 24-13 commands, 24-10 connecting to Ethernet, 24-4 error handling, 24-14 frame reception, 24-6 hash table algorithm, 24-13 loopback, 24-14 overview, 24-1 programming example, 24-23 programming the controller, 24-10 receive buffer, 24-17 transmit buffer, 24-19 HDLC mode accessing the bus, 21-19 bus controller, 21-17 collision detection, 21-17, 21-20 commands, 21-5 delayed RTS mode, 21-21 erro
PAGE 998
INDEX frame reception, 23-2 frame transmission, 23-2 inherent synchronization, 23-6 in-line synchronization, 23-6 overview, 23-1 programming example, 23-13 RxBD, 23-9 synchronization signals, 23-4 synchronization, user-controlled, 23-5 transmit synchronization, 23-3 TxBD, 23-10 UART mode commands, 20-6 control character insertion, 20-10 data handling, character and message-based, 20-5 error reporting, 20-6 features list, 20-2 fractional stop bits, 20-11 handling errors, 20-12 hunt mode, 20-10 memory map, 20
PAGE 999
INDEX SIUMCR (SIU module configuration register), 4-31 SIVEC (SIU interrupt vector register), 4-23 SMC memory map, 3-12 SMCE (SMC event) register GCI mode, 26-34 transparent mode, 26-28 UART mode, 26-18 SMCM (SMC mask) register GCI mode, 26-34 transparent mode, 26-28 UART mode, 26-18 SMCMRs (SMC mode registers), 26-3 SPCOM (SPI command) register, 33-9 SPI memory map, 3-12 SPIE (SPI event) register, 33-9 SPIM (SPI mask) register, 33-9 SPMODE (SPI mode) register, 33-6 SWR (software watchdog register), 4-7 SWS
PAGE 1000
INDEX PPC_ALRL, 4-29 programming model, 4-17 registers, 4-17 SCC relative priority, 4-12 SCPRR_H, 4-19 SCPRR_L, 4-20 SICR, 4-17 SIEXR, 4-24 signal multiplexing, 4-44 SIMR_H, 4-22, 4-22 SIPNR_H, 4-21 SIPNR_L, 4-21 SIPRR, 4-18 SIUMCR, 4-31 SIVEC, 4-23 software watchdog timer, 4-6 SWR, 4-7 SWSR, 4-36 SYPCR, 4-35 system protection, 4-2 TESCR1, 4-36 TESCR2, 4-37 time counter (TMCNT) function, 4-2 overview, 4-4 timers, 4-4 TMCNT, 4-41 TMCNTAL, 4-41 TMCNTSC, 4-40 T TBST (transfer burst) signal, 8-13 TCN (timer co
PAGE 1001
INDEX fractional stop bits, 20-11 handling errors, 20-12 hunt mode, 20-10 memory map, 20-4 normal asynchronous mode, 20-3 overview, 20-1 parameter RAM, 20-4 programming example, 20-22 RxBD, 20-15 serial management controllers character mode, 26-12 commands, 26-12 data handling, 26-12 error handling, 26-13 features list, 26-11 features not supported by SMCs, 26-10 frame format, 26-11 message-oriented mode, 26-12 overview, 26-10 parameter RAM, 26-6 programming example, 26-19 reception process, 26-12 RxBD, 26-
PAGE 1002
INDEX Index-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
PAGE 1003
Overview PowerPC Processor Core Memory Map System Interface Unit (SIU) Reset External Signals 60x Signals The 60x Bus Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.
PAGE 1004
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A GLO IND Overview PowerPC Processor Core Memory Map System Interface Unit (SIU) Reset External Signals 60x Signals The 60x Bus Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.
PAGE 1005
Attention! This book is a companion to the PowerPC Microprocessor Family: The Programming Environments, referred to as The Programming Environments Manual. Note that the companion Programming Environments Manual exists in two versions.
PAGE 1006