Processor Users Manual

x MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
7.2.5.2 Address Retry (ARTRY)............................................................................7-11
7.2.5.2.1 Address Retry (ARTRY)ÑOutput.........................................................7-11
7.2.5.2.2 Address Retry (ARTRY)ÑInput ...........................................................7-11
7.2.6 Data Bus Arbitration Signals..........................................................................7-12
7.2.6.1 Data Bus Grant (DBG) ...............................................................................7-12
7.2.6.1.1 Data Bus Grant (DBG)ÑInput ..............................................................7-12
7.2.6.1.2 Data Bus Grant (DBG)ÑOutput............................................................7-12
7.2.6.2 Data Bus Busy (DBB) ................................................................................7-13
7.2.6.2.1 Data Bus Busy (DBB)ÑOutput.............................................................7-13
7.2.6.2.2 Data Bus Busy (DBB)ÑInput................................................................7-13
7.2.7 Data Transfer Signals .....................................................................................7-13
7.2.7.1 Data Bus (D[0Ð63]) ....................................................................................7-13
7.2.7.1.1 Data Bus (D[0Ð63])ÑOutput.................................................................7-14
7.2.7.1.2 Data Bus (D[0Ð63])ÑInput ...................................................................7-14
7.2.7.2 Data Bus Parity (DP[0Ð7]) .........................................................................7-14
7.2.7.2.1 Data Bus Parity (DP[0Ð7])ÑOutput ......................................................7-14
7.2.7.2.2 Data Bus Parity (DP[0Ð7])ÑInput.........................................................7-15
7.2.8 Data Transfer Termination Signals ................................................................7-15
7.2.8.1 Transfer Acknowledge (TA) ......................................................................7-15
7.2.8.1.1 Transfer Acknowledge (TA)ÑInput......................................................7-15
7.2.8.1.2 Transfer Acknowledge (TA)ÑOutput ...................................................7-16
7.2.8.2 Transfer Error Acknowledge (TEA) ..........................................................7-16
7.2.8.2.1 Transfer Error Acknowledge (TEA)ÑInput..........................................7-16
7.2.8.2.2 Transfer Error Acknowledge (TEA)ÑOutput .......................................7-17
7.2.8.3 Partial Data Valid Indication (PSDVAL)...................................................7-17
7.2.8.3.1 Partial Data Valid (PSDVAL)ÑInput ...................................................7-17
7.2.8.3.2 Partial Data Valid (PSDVAL)ÑOutput.................................................7-18
Chapter 8
The 60x Bus
8.1 Terminology .........................................................................................................8-1
8.2 Bus Configuration.................................................................................................8-2
8.2.1 Single MPC8260 Bus Mode.............................................................................8-2
8.2.2 60x-Compatible Bus Mode...............................................................................8-3
8.3 60x Bus Protocol Overview..................................................................................8-4
8.3.1 Arbitration Phase ..............................................................................................8-5
8.3.2 Address Pipelining and Split-Bus Transactions ...............................................8-7
8.4 Address Tenure Operations ..................................................................................8-7
8.4.1 Address Arbitration ..........................................................................................8-7
8.4.2 Address Pipelining............................................................................................8-9
8.4.3 Address Transfer Attribute Signals ................................................................8-10