Processor Users Manual

xii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
9.8 System Clock Control Register (SCCR) ..............................................................9-8
9.9 System Clock Mode Register (SCMR) ................................................................9-9
9.10 Basic Power Structure ........................................................................................9-10
Chapter 10
Memory Controller
10.1 Features...............................................................................................................10-3
10.2 Basic Architecture ..............................................................................................10-5
10.2.1 Address and Address Space Checking ...........................................................10-8
10.2.2 Page Hit Checking..........................................................................................10-9
10.2.3 Error Checking and Correction (ECC) ...........................................................10-9
10.2.4 Parity Generation and Checking.....................................................................10-9
10.2.5 Transfer Error Acknowledge (TEA) Generation............................................10-9
10.2.6 Machine Check Interrupt (MCP) Generation .................................................10-9
10.2.7 Data Buffer Controls (BCTLx) ....................................................................10-10
10.2.8 Atomic Bus Operation..................................................................................10-10
10.2.9 Data Pipelining ............................................................................................10-10
10.2.10 External Memory Controller Support...........................................................10-11
10.2.11 External Address Latch Enable Signal (ALE)..............................................10-11
10.2.12 ECC/Parity Byte Select (PBSE) ...................................................................10-11
10.2.13 Partial Data Valid Indication (PSDVAL).....................................................10-12
10.3 Register Descriptions........................................................................................10-13
10.3.1 Base Registers (BR
x ) ...................................................................................10-14
10.3.2 Option Registers (ORx)................................................................................10-16
10.3.3 60x SDRAM Mode Register (PSDMR) .......................................................10-21
10.3.4 Local Bus SDRAM Mode Register (LSDMR) ............................................10-24
10.3.5 Machine A/B/C Mode Registers (MxMR) ...................................................10-26
10.3.6 Memory Data Register (MDR).....................................................................10-28
10.3.7 Memory Address Register (MAR) ...............................................................10-29
10.3.8 60x Bus-Assigned UPM Refresh Timer (PURT).........................................10-30
10.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)......................................10-30
10.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT) ....................................10-31
10.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT).................................10-32
10.3.12 Memory Refresh Timer Prescaler Register (MPTPR) .................................10-32
10.3.13 60x Bus Error Status and Control Registers (TESCRx)...............................10-33
10.3.14 Local Bus Error Status and Control Registers (L_TESCRx) .......................10-33
10.4 SDRAM Machine.............................................................................................10-33
10.4.1 Supported SDRAM Configurations .............................................................10-35
10.4.2 SDRAM Power-On Initialization .................................................................10-35
10.4.3 JEDEC-Standard SDRAM Interface Commands.........................................10-35
10.4.4 Page-Mode Support and Pipeline Accesses .................................................10-36