Processor Users Manual

MOTOROLA Chapter 3. Memory Map 3-5
Part I. Overview
Input/Output Port
10D00 PDIRA Port A data direction register 32 bits 35.2.3/35-3
10D04 PPARA Port A pin assignment register 32 bits 35.2.4/35-4
10D08 PSORA Port A special options register 32 bits 35.2.5/35-4
10D0C PODRA Port A open drain register 32 bits 35.2.1/35-2
10D10 PDATA Port A data register 32 bits 35.2.2/35-2
10D14Ð10D1F Reserved Ñ 12 bytes Ñ
10D20 PDIRB Port B data direction register 32 bits 35.2.3/35-3
10D24 PPARB Port B pin assignment register 32 bits 35.2.4/35-4
10D28 PSORB Port B special operation register 32 bits 35.2.5/35-4
10D2C PODRB Port B open drain register 32 bits 35.2.1/35-2
10D30 PDATB Port B data register 32 bits 35.2.2/35-2
10D34Ð10D3F Reserved Ñ 12 bytes Ñ
10D40 PDIRC Port C data direction register 32 bits 35.2.3/35-3
10D44 PPARC Port C pin assignment register 32 bits 35.2.4/35-4
10D48 PSORC Port C special operation register 32 bits 35.2.5/35-4
10D4C PODRC Port C open drain register 32 bits 35.2.1/35-2
10D50 PDATC Port C data register 32 bits 35.2.2/35-2
10D54Ð10D5F Reserved Ñ 12 bytes Ñ
10D60 PDIRD Port D data direction register 32 bits 35.2.3/35-3
10D64 PPARD Port D pin assignment register 32 bits 35.2.4/35-4
10D68 PSORD Port D special operation register 32 bits 35.2.5/35-4
10D6C PODRD Port D open drain register 32 bits 35.2.1/35-2
10D70 PDATD Port D data register 32 bits 35.2.2/35-2
CPM Timers
10D80 TGCR1 Timer 1 and timer 2 global
conÞguration register
8 bits 17.2.2/17-4
10D81 Reserved Ñ 3 bytes Ñ
10D84 TGCR2 Timer 3 and timer 4 global
conÞguration register
8 bits 17.2.2/17-4
10D85Ð10D8F Reserved Ñ 11 bytes Ñ
10D90 TMR1 Timer 1 mode register 16 bits 17.2.3/17-6
Table 3-1. Internal Memory Map (Continued)
Internal
Address
Abbreviation Name Size Section/Page Number