Processor Users Manual

3-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
11A08 PSMR1 SCC1 protocol-speciÞc mode register 16 bits 19.1.2/19-9
20.16/20-13 (UART)
21.8/21-7 (HDLC)
22.11/22-10 (BISYNC)
23.9/23-9 (Transparent)
24.17/24-15 (Ethernet)
11A0A Reserved Ñ 2 bytes Ñ
11A0C TODR1 SCC1 transmit-on-demand register 16 bits 19.1.4/19-9
11A0E DSR1 SCC1 data synchronization register 16 bits 19.1.3/19-9
11A10 SCCE1 SCC1 event register 16 bits 20.19/20-19 (UART)
21.11/21-12 (HDLC)
22.14/22-15 (BISYNC)
23.12/23-12 (Transparent)
24.20/24-21 (Ethernet)
11A14 SCCM1 SCC1 mask register 16 bits
11A17 SCCS1 SCC1 status register 8 bits 20.20/20-21 (UART)
21.12/21-14 (HDLC)
22.15/22-16 (BISYNC)
23.13/23-13 (Transparent)
11A18Ð11A1F Reserved Ñ 8 bytes Ñ
SCC2
11A20 GSMR_L2 SCC2 general mode register (low) 32 bits 19.1.1/19-3
11A24 GSMR_H2 SCC2 general mode register (high) 32 bits
11A28 PSMR2 SCC2 protocol-speciÞc mode register 16 bits 19.1.2/19-9
20.16/20-13 (UART)
21.8/21-7 (HDLC)
22.11/22-10 (BISYNC)
23.9/23-9 (Transparent)
24.17/24-15 (Ethernet)
11A2A Reserved Ñ 2 bytes Ñ
11A2C TODR2 SCC2 transmit-on-demand register 16 bits 19.1.4/19-9
11A2E DSR2 SCC2 data synchronization register 16 bits 19.1.3/19-9
11A30 SCCE2 SCC2 event register 16 bits 20.19/20-19 (UART)
21.11/21-12 (HDLC)
22.14/22-15 (BISYNC)
23.12/23-12 (Transparent)
24.20/24-21 (Ethernet)
11A34 SCCM2 SCC2 mask register 16 bits
11A37 SCCS2 SCC2 status register 8 bits 20.20/20-21 (UART)
21.12/21-14 (HDLC)
22.15/22-16 (BISYNC)
23.13/23-13 (Transparent)
11A38Ð11A3F Reserved Ñ 8 bytes Ñ
Table 3-1. Internal Memory Map (Continued)
Internal
Address
Abbreviation Name Size Section/Page Number