Processor Users Manual

3-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
11A77 SCCS4 SCC4 status register 8 bits 20.20/20-21 (UART)
21.12/21-14 (HDLC)
22.15/22-16 (BISYNC)
23.13/23-13 (Transparent)
11A78Ð11A7F Reserved Ñ 8 bytes Ñ
SMC1
11A82 SMCMR1 SMC1 mode register 16 bits 26.2.1/26-3
11A86 SMCE1 SMC1 event register 8 bits 26.3.11/26-18 (UART)
26.4.10/26-28 (Transparent)
26.5.9/26-34 (GCI)
11A8A SMCM1 SMC1 mask register 8 bits
11A8BÐ11A 91 Reserved Ñ 7 bytes Ñ
SMC2
11A92 SMCMR2 SMC2 mode register 16 bits 26.2.1/26-3
11A96 SMCE2 SMC2 event register 8 bits 26.3.11/26-18 (UART)
26.4.10/26-28 (Transparent)
26.5.9/26-34 (GCI)
11A9A SMCM2 SMC2 mask register 8 bits
11A9BÐ11A9F Reserved Ñ 5 bytes Ñ
SPI
11AA0 SPMODE SPI mode register 16 bits 33.4.1/33-6
11AA2 Reserved Ñ 4 bytes Ñ
11AA6 SPIE SPI event register 8 bits 33.4.2/33-9
11AA7 Reserved Ñ 24 bits Ñ
11AAA SPIM SPI mask register 8 bits 33.4.2/33-9
11AAB Reserved Ñ 24 bits Ñ
11AAD SPCOM SPI command register 8 bits 33.4.3/33-9
11AA7Ð11AFF Reserved Ñ 89 bytes Ñ
CPM Mux
11B00 CMXSI1CR CPM mux SI1 clock route register 8 bits 15.4.2/15-10
11B02 CMXSI2CR CPM mux SI2 clock route register 8 bits 15.4.3/15-11
11B03 Reserved Ñ 8 bits Ñ
11B04 CMXFCR CPM mux FCC clock route register 32 bits 15.4.4/15-12
11B08 CMXSCR CPM mux SCC clock route register 32 bits 15.4.5/15-14
11B0C CMXSMR CPM mux SMC clock route register 8 bits 15.4.6/15-17
11B0D Reserved Ñ 8 bits Ñ
Table 3-1. Internal Memory Map (Continued)
Internal
Address
Abbreviation Name Size Section/Page Number