Processor Users Manual

xiv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
10.6.4.1.4 Loop Control ........................................................................................10-76
10.6.4.1.5 Repeat Execution of Current RAM Word (REDO) ............................10-76
10.6.4.2 Address Multiplexing ...............................................................................10-77
10.6.4.3 Data Valid and Data Sample Control .......................................................10-77
10.6.4.4 Signals Negation.......................................................................................10-78
10.6.4.5 The Wait Mechanism ...............................................................................10-78
10.6.4.6 Extended Hold Time on Read Accesses ..................................................10-79
10.6.5 UPM DRAM Configuration Example..........................................................10-79
10.6.6 Differences between MPC8xx UPM and MPC8260 UPM ..........................10-80
10.7 Memory System Interface Example Using UPM .............................................10-81
10.7.0.1 EDO Interface Example ...........................................................................10-92
10.8 Handling Devices with Slow or Variable Access Times................................10-100
10.8.1 Hierarchical Bus Interface Example...........................................................10-100
10.8.2 Slow Devices Example...............................................................................10-100
10.9 External Master Support (60x-Compatible Mode).........................................10-101
10.9.1 60x-Compatible External Masters..............................................................10-101
10.9.2 MPC8260-Type External Masters..............................................................10-101
10.9.3 Extended Controls in 60x-Compatible Mode.............................................10-101
10.9.4 Using BNKSEL SIgnals in Single-MPC8260 Bus Mode ..........................10-102
10.9.5 Address Incrementing for External Bursting Masters ................................10-102
10.9.6 External Masters Timing ............................................................................10-102
10.9.6.1 Example of External Master Using the SDRAM Machine ....................10-104
Chapter 11
Secondary (L2) Cache Support
11.1 L2 Cache Configurations....................................................................................11-1
11.1.1 Copy-Back Mode............................................................................................11-1
11.1.2 Write-Through Mode......................................................................................11-2
11.1.3 ECC/Parity Mode ...........................................................................................11-4
11.2 L2 Cache Interface Parameters...........................................................................11-7
11.3 System Requirements When Using the L2 Cache Interface...............................11-7
11.4 L2 Cache Operation............................................................................................11-7
11.5 Timing Example .................................................................................................11-8
Chapter 12
IEEE 1149.1 Test Access Port
12.1 Overview ............................................................................................................12-1
12.2 TAP Controller ...................................................................................................12-2
12.3 Boundary Scan Register .....................................................................................12-3
12.4 Instruction Register...........................................................................................12-28