Processor Users Manual

4-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part II. ConÞguration and Reset
When a pending interrupt is handled, the user clears the corresponding SIPNR bit.
However, if an event register exists, the unmasked event register bits should be cleared
instead, causing the SIPNR bit to be cleared.
SIPNR bits are cleared by writing ones to them. Because the user can only clear bits in this
register, writing zeros to this register has no effect.
Note that the SCC/FCC/MCC SIPNR bit positions are not changed according to their
relative priority.
4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)
Each bit in the SIU interrupt mask register (SIMR) corresponds to a interrupt source. The
user masks an interrupt by clearing and enables an interrupt by setting the corresponding
SIMR bit. When a masked interrupt occurs, the corresponding SIPNR bit is set, regardless
of the SIMR bit although no interrupt request is passed to the core.
If an interrupt source requests interrupt service when the user clears its SIMR bit, the
request stops. If the user sets the SIMR bit later, a previously pending interrupt request is
processed by the core, according to its assigned priority. The SIMR can be read by the user
at any time.
Figure 4-16 shows the SIMR_H register.
Figure 4-17 shows SIMR_L.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10C1C
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Ñ IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Ñ TMCNT PIT Ñ
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10C1E
Figure 4-16. SIMR_H Register