Processor Users Manual

4-29 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part II. ConÞguration and Reset
PPC_ALRL, shown in Figure 4-24, deÞnes arbitration priority of 60x bus masters 8Ð15.
Priority Þeld 0 is the highest-priority arbitration level. For information about the MPC8260
bus master indexes, see the description of PPC_ACR[PRKM] in Table 4-10.
4.3.2.4 Local Bus Arbiter ConÞguration Register (LCL_ACR)
The local bus arbiter conÞguration register (LCL_ACR), shown in Figure 4-25, deÞnes the
arbiter modes and the parked master on the local bus.
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Priority Field 0 Priority Field 1 Priority Field 2 Priority Field 3
Reset 0000 0001 0010 0011
R/W R/W
Addr 0x1002C
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Priority Field 4 Priority Field 5 Priority Field 6 Priority Field 7
Reset 0100 0101 0110 0111
R/W R/W
Addr 0x1002E
Figure 4-23. PPC_ALRH
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Priority Field 8 Priority Field 9 Priority Field 10 Priority Field 11
Reset 1000 1001 1010 1011
R/W R/W
Addr 0x10030
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Priority Field 12 Priority Field 13 Priority Field 14 Priority Field 15
Reset 1100 1101 1110 1111
R/W R/W
Addr 0x10032
Figure 4-24. PPC_AALRL
Bit
0 1 2 3 4 5 6 7
Field Ñ DBGD Ñ PRKM
Reset 0000_0010
R/W R/W
Addr 0x10034
Figure 4-25. LCL_ACR