Processor Users Manual

MOTOROLA Contents xvii
CONTENTS
Paragraph
Number
Title
Page
Number
Chapter 16
Baud-Rate Generators (BRGs)
16.1 BRG Configuration Registers 1Ð8 (BRGCx).....................................................16-2
16.2 Autobaud Operation on a UART .......................................................................16-4
16.3 UART Baud Rate Examples ..............................................................................16-5
Chapter 17
Timers
17.1 Features ..............................................................................................................17-2
17.2 General-Purpose Timer Units.............................................................................17-2
17.2.1 Cascaded Mode ..............................................................................................17-3
17.2.2 Timer Global Configuration Registers (TGCR1 and TGCR2) ......................17-4
17.2.3 Timer Mode Registers (TMR1ÐTMR4).........................................................17-6
17.2.4 Timer Reference Registers (TRR1ÐTRR4)....................................................17-7
17.2.5 Timer Capture Registers (TCR1ÐTCR4) .......................................................17-8
17.2.6 Timer Counters (TCN1ÐTCN4).....................................................................17-8
17.2.7 Timer Event Registers (TER1ÐTER4) ...........................................................17-8
Chapter 18
SDMA Channels and IDMA Emulation
18.1 SDMA Bus Arbitration and Bus Transfers ........................................................18-2
18.2 SDMA Registers ................................................................................................18-3
18.2.1 SDMA Status Register (SDSR) .....................................................................18-3
18.2.2 SDMA Mask Register (SDMR) .....................................................................18-4
18.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA).................18-4
18.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM) .............18-4
18.3 IDMA Emulation................................................................................................18-5
18.4 IDMA Features...................................................................................................18-5
18.5 IDMA Transfers .................................................................................................18-6
18.5.1 Memory-to-Memory Transfers ......................................................................18-6
18.5.1.1 External Request Mode..............................................................................18-8
18.5.1.2 Normal Mode .............................................................................................18-9
18.5.2 Memory to/from Peripheral Transfers ...........................................................18-9
18.5.2.1 Dual-Address Transfers ...........................................................................18-10
18.5.2.1.1 Peripheral to Memory ..........................................................................18-10
18.5.2.1.2 Memory to Peripheral ..........................................................................18-10
18.5.2.2 Single Address (Fly-By) Transfers ..........................................................18-11
18.5.2.2.1 Peripheral-to-Memory Fly-By Transfers .............................................18-11
18.5.2.2.2 Memory-to-Peripheral Fly-By Transfers .............................................18-11