Processor Users Manual

xviii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
18.5.3 Controlling 60x Bus Bandwidth...................................................................18-12
18.6 IDMA Priorities................................................................................................18-12
18.7 IDMA Interface Signals....................................................................................18-12
18.7.1 DREQx and DACKx ....................................................................................18-13
18.7.1.1 Level-Sensitive Mode...............................................................................18-13
18.7.1.2 Edge-Sensitive Mode ...............................................................................18-13
18.7.2 DONEx .........................................................................................................18-14
18.8 IDMA Operation...............................................................................................18-14
18.8.1 Auto Buffer and Buffer Chaining.................................................................18-15
18.8.2 IDMAx Parameter RAM ..............................................................................18-16
18.8.2.1 DMA Channel Mode (DCM) ...................................................................18-18
18.8.2.2 Data Transfer Types as Programmed in DCM.........................................18-20
18.8.2.3 Programming DTS and STS.....................................................................18-20
18.8.3 IDMA Performance ......................................................................................18-22
18.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR).........................18-22
18.8.5 IDMA BDs ...................................................................................................18-23
18.9 IDMA Commands ............................................................................................18-26
18.9.1 start_idma Command....................................................................................18-26
18.9.2 stop_idma Command....................................................................................18-26
18.10 IDMA Bus Exceptions......................................................................................18-27
18.10.1 Externally Recognizing IDMA Operand Transfers......................................18-27
18.11 Programming the Parallel I/O Registers...........................................................18-28
18.12 IDMA Programming Examples........................................................................18-29
18.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)ÑIDMA2.................18-29
18.12.2 Memory-to-Peripheral Fly-By Mode (Both on 60x Bus)ÑIDMA3 ............18-30
Chapter 19
Serial Communications Controllers (SCCs)
19.1 Features...............................................................................................................19-2
19.1.1 The General SCC Mode Registers (GSMR1ÐGSMR4) .................................19-3
19.1.2 Protocol-Specific Mode Register (PSMR) .....................................................19-9
19.1.3 Data Synchronization Register (DSR)............................................................19-9
19.1.4 Transmit-on-Demand Register (TODR).........................................................19-9
19.2 SCC Buffer Descriptors (BDs) .........................................................................19-10
19.3 SCC Parameter RAM .......................................................................................19-13
19.3.1 SCC Base Addresses ....................................................................................19-15
19.3.2 Function Code Registers (RFCR and TFCR)...............................................19-15
19.3.3 Handling SCC Interrupts ..............................................................................19-16
19.3.4 Initializing the SCCs.....................................................................................19-17
19.3.5 Controlling SCC Timing with RTS, CTS, and CD ......................................19-18
19.3.5.1 Synchronous Protocols .............................................................................19-18