Processor Users Manual

7-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part III. The Hardware Interface

system can assert PSDVAL for one bus clock cycle and then negate

it to insert wait states during the next beat. (Note: when the

MPC8260 Processor is conÞgured for 1:1 clock mode and is

performing a burst read into the data cache, the MPC8260 requires

two wait state between the assertion of TS

and the Þrst assertion of

DVAL for that transaction, or 1 wait state for 1.5:1 clock mode.)

7.2.8.3.2 Partial Data Valid (PS

DVAL)ÑOutput

Following are the state meaning and timing comments for PSD

VAL as an output signal.

State Meaning AssertedÑIndicates that the data has been latched for a write

operation, or that the data is valid for a read operation, thus

terminating the current data beat. If it is the last or only data beat, this

also terminates the data tenure.

NegatedÑIndicates that the master must extend the current data beat

(insert wait states) until data can be provided or accepted by the

MPC8260.

Timing Comments AssertionÑOccurs on the clock in which the current data transfer

can be completed.

NegationÑOccurs after the clock cycle of the Þnal (or only) data

beat of the transfer. For a burst transfer, PS

DVAL may be negated

between beats to insert one or more wait states before the completion

of the next beat.