Processor Users Manual

8-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Note the following regarding Table 8-2:
¥ For reads, the processor cleans or ßushes during a snoop based on the TBST
input.
The processor cleans for single-beat reads (TBST
negated) to emulate read-with-no-
intent-to-cache operations.
¥ Castouts and snoop copybacks are generally marked as non-global and are not
snooped (except for reservation monitoring). However, other masters performing
DMA write operations with the same TT encoding and marked as a global WR
operation (whether global or non-global) will cancel an active reservation during a
snoop hit in the reservation register (independent of a snoop hit in the cache).
¥ A non-processor read can cause the internal processor to invalidate the
corresponding cache line if it exists.
01110 Read with
intent to
modify
Burst Burst Load miss, store miss,
or I-fetch
Flush Read, assert AA
CK
and T
A.
10010 WR w/ßush
atomic
Single-beat
write
Single-beat
write
stwcx Flush, cancel
reservation
Write, assert AA
CK
and T
A
10110 Reserved Not
applicable to
MPC8260
Not applicable
to MPC8260
Not applicable to
MPC8260
Not applicable
to MPC8260
Illegal
11010 Read
atomic
Single-beat
read or burst
Single-beat
read
lwarx (CI load) Clean or ßush Read, assert AA
CK
and T
A
11110 Read with
intent to
modify
atomic
Burst Burst lwarx (load miss) Flush Read, assert AA
CK
and T
A
00011 Reserved Ñ Not applicable
to MPC8260
Not applicable to
MPC8260
Not applicable
to MPC8260
Illegal
00111 Reserved Ñ Not applicable
to MPC8260
Not applicable to
MPC8260
Not applicable
to MPC8260
Illegal
01011 Read with
no intent to
cache
Single-beat
read or burst
Not applicable
to MPC8260
Not applicable to
MPC8260
Clean Read, assert AA
CK
and T
A
01111 Reserved Ñ Not applicable
to MPC8260
Not applicable to
MPC8260
Not applicable
to MPC8260
Illegal
1XX11 Reserved
for customer
Ñ Not applicable
to MPC8260
Not applicable to
MPC8260
Not applicable
to MPC8260
Illegal
1
TT1 can be interpreted as a read-versus-write indicator for the bus.
2
This column speciÞes the TT encoding for the general 60x protocol. The processor generates or snoops only a
subset of those encodings.
Table 8-2. Transfer Type Encoding (Continued)
TT[0Ð4]
1
60x Bus SpeciÞcation
2
MPC8260 as Bus Master
MPC8260 as
Snooper
MPC8260 as Slave
Command Transaction Bus Trans. Transaction Source Action on Hit Action on Slave Hit