Processor Users Manual

MOTOROLA Chapter 8. The 60x Bus 8-15
Part III. The Hardware Interface
The MPC8260 supports misaligned memory operations, although they may degrade
performance substantially. A misaligned memory address is one that is not aligned to the
size of the data being transferred (such as, a word read from an odd byte address). The
MPC8260Õs processor bus interface supports misaligned transfers within a word (32-bit
aligned) boundary, as shown in Table 8-7. Note that the 4-byte transfer in Table 8-7 is only
one example of misalignment. As long as the attempted transfer does not cross a word
boundary, the MPC8260 can transfer the data to the misaligned address within a single bus
transfer (for example, a half-word read from an odd byte-aligned address). It takes two bus
transfers to access data that crosses a word boundary.
Due to the performance degradation, misaligned memory operations should be avoided. In
addition to the double-word straddle boundary condition, the processorÕs address
translation logic can generate substantial exception overhead when the load/store multiple
and load/store string instructions access misaligned data. It is strongly recommended that
Table 8-6. Aligned Data Transfers
Program Transfer
Size
TSIZ[0Ð3] A[29Ð31]
Data Bus Byte Lanes
D0... ...D31 D32... ...D63
B0 B1 B2 B3 B4 B5 B6 B7
Byte 0 0 0 1 0 0 0 OP0
1
1
OPn: These lanes are read or written during that bus transaction. OP0 is the most-signiÞcant byte of a word
operand and OP7 is the least-signiÞcant byte.
Ñ
2
2
Ñ: These lanes are ignored during reads and driven with undeÞned data during writes.
ÑÑÑÑÑÑ
0 0 0 1 0 0 1 ÑOP1ÑÑÑÑÑÑ
0 0 0 1 0 1 0 ÑÑOP2ÑÑÑÑÑ
0 0 0 1 0 1 1 ÑÑÑOP3ÑÑÑÑ
0 0 0 1 1 0 0 ÑÑÑÑOP4ÑÑÑ
0 0 0 1 1 0 1 ÑÑÑÑÑOP5ÑÑ
0 0 0 1 1 1 0 ÑÑÑÑÑÑOP6Ñ
0 0 0 1 1 1 1 ÑÑÑÑÑÑÑOP7
Half-Word 0 0 1 0 0 0 0 OP0 OP1 Ñ Ñ ÑÑÑÑ
0 0 1 0 0 1 0 ÑÑOP2OP3ÑÑÑÑ
0 0 1 0 1 0 0 ÑÑÑÑOP4OP5ÑÑ
0 0 1 0 1 1 0 ÑÑÑÑÑÑOP6OP7
Word 0 1 0 0 0 0 0 OP0OP1OP2OP3ÑÑÑÑ
0 1 0 0 1 0 0 ÑÑÑÑOP4OP5OP6OP7
Double-Word 0 0 0 0 0 0 0 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7