Processor Users Manual

8-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part III. The Hardware Interface

Figure 8-7. Retry Cycle

As a bus master, the MPC8260 recognizes either an early or qualiÞed ARTRY and prevents

the data tenure associated with the retried address tenure. If the data tenure has begun, the

MPC8260 terminates the data tenure immediately even if the burst data has been received.

If the assertion of AR

TRY is received up to or on the bus cycle after the Þrst (or only)

assertion of T

A for the data tenure, the MPC8260 ignores the Þrst data beat. If it is a read

operation, the MPC8260 does not forward data internally to the cache, execution unit, or

any other MPC8260 internal storage. This address retry case succeeds because the data

tenure is aborted in time, and the entire transaction is rerun. This retry mechanism allows

the memory system to begin operating in parallel with the bus snoopers, provided external

devices do not present data sooner than the bus cycle before all snoop responses can be

determined and asserted on the bus.

Note that the system must ensure that the Þrst (or only) assertion of T

A for a data transfer

does not occur sooner than the cycle before the Þrst assertion of AR

TRY on the bus, (or

conversely, that AR

TRY is never asserted later than the cycle after the Þrst or only assertion

of T

A). This guarantees the relationship between TA and ARTRY such that, in case of an

address retry, the data may be cancelled in the chip before it can be forwarded internally to

the internal memory resources (registers or cache). Generally, the memory system must

CLKOUT

BR INT

ADDR + ATTR

BG INT

ABB

AACK

ARTRY

MPC8260 External MPC8260

External