Processor Users Manual

MOTOROLA Chapter 8. The 60x Bus 8-31

Part III. The Hardware Interface

Figure 8-11. Data Tenure Terminated by Assertion of TEA

MPC8260 interprets the following bus transactions as bus errors:

¥ Direct-store transactions, as indicated by the assertion of XA

TS.

¥ Bus errors asserted by slaves (internal or external).

8.6 Memory CoherencyÑMEI Protocol

The MPC8260 provides dedicated hardware to ensure memory coherency by snooping bus

transactions, by maintaining information about the status of data in a cache block, and by

the address retry capability. Each data cache block includes status bits that support the

modiÞed/exclusive/invalid, or MEI, cache-coherency protocol.

Asserting the global (GBL

) output signal indicates whether the current transaction must be

snooped by other snooping devices on the bus. Address bus masters assert GBL

to indicate

that the current transaction is a global access (that is, an access to memory shared by more

than one device). If GBL

is not asserted for the transaction, that transaction is not snooped.

When other devices detect the GBL

input asserted, they must respond by snooping any

addresses broadcast. Normally, GBL

reßects the M bit value speciÞed for the memory

reference in the corresponding translation descriptor. Care must be taken to minimize the

number of pages marked as global, because the retry protocol discussed in the previous

section used to enforce coherency can require signiÞcant bus bandwidth.

CLKOUT

ADDR + ATTR

AACK

DBG

Data

TEA

For Single For Burst