Processor Users Manual

9-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
9.2 Clock ConÞguration
To conÞgure the main PLL multiplication factor and the core, CPM, and 60x bus
frequencies, the MODCK[1Ð3] pins are sampled while H
RESET is asserted. Table 9-1
shows the eight basic conÞguration modes. Another 49 modes are available by using the
conÞguration pin (RSTCONF
) and driving four pins on the data bus.
Table 9-2 describes all possible clock conÞgurations when using the hard reset
conÞguration sequence. Note that clock conÞguration changes only after POR
is asserted.
Note also that basic modes are bolded in this table.
Table 9-1. Clock Default Modes
MODCK[1Ð3]
Input Clock
Frequency
CPM Multiplication
Factor
CPM
Frequency
Core Multiplication
Factor
Core
Frequency
000 33 MHz 3 100 MHz 4 133 MHz
001 33 MHz 3 100 MHz 5 166 MHz
010 33 MHz 4 133 MHz 4 133 MHz
011 33 MHz 4 133 MHz 5 166 MHz
100 66 MHz 2 133 MHz 2.5 166 MHz
101 66 MHz 2 133 MHz 3 200 MHz
110 66 MHz 2.5 166 MHz 2.5 166 MHz
111 66 MHz 2.5 166 MHz 3 200 MHz
Table 9-2. Clock Configuration Modes
MODCK_HÐMODCK[1Ð3]
Input Clock
Frequency
CPM Multiplication
Factor
CPM
Frequency
Core Multiplication
Factor
Core
Frequency
0001_000 33 MHz 2 66 MHz 4 133 MHz
0001_001 33 MHz 2 66 MHz 5 166 MHz
0001_010 33 MHz 2 66 MHz 6 200 MHz
0001_011 33 MHz 2 66 MHz 7 233 MHz
0001_100 33 MHz 2 66 MHz 8 266 MHz
0001_101 33 MHz 3 100 MHz 4 133 MHz
0001_110 33 MHz 3 100 MHz 5 166 MHz
0001_111 33 MHz 3 100 MHz 6 200 MHz
0010_000 33 MHz 3 100 MHz 7 233 MHz
0010_001 33 MHz 3 100 MHz 8 266 MHz
0010_010 33 MHz 4 133 MHz 4 133 MHz