Processor Users Manual

MOTOROLA Chapter 10. Memory Controller 10-39
Part III. The Hardware Interface
Figure 10-20. PRETOACT = 2 (2 Clock Cycles)
10.4.6.2 Activate to Read/Write Interval
This parameter, controlled by P/LSDMR[ACTTORW], deÞnes the earliest timing for
READ/WRITE command after an ACTIVATE command.
Figure 10-21. ACTTORW = 2 (2 Clock Cycles)
CLK
ALE
CS
SDRAS
SDCAS
WE
DQM
PRECHARGE
Command
ACTIVATE
MA11
MA10
MA[0Ð9]
RAy
RAy
Bank A
Command
Bank A
PRETOACT
= 2
CLK
ALE
CS
SDRAS
SDCAS
Rbz
WE
DQM
ACTIVATE
MA[0Ð11]
Command
ACTTORW = 2
DATA
D0 D1 D2 D3
WRITE
Command
Cbz