Processor Users Manual

MOTOROLA Chapter 10. Memory Controller 10-45
Part III. The Hardware Interface
Figure 10-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3
Figure 10-35. SDRAM Write-after-Write Pipelined, Page Hit
Figure 10-36. SDRAM Read-after-Write Pipelined, Page Hit
CLK
ALE
CS
SDRAS
SDCAS
MA[0Ð11]
Column1
WE
DQM
Data
D0
Z Column2
D0 D1
D1
DQM latency (affects negation only) = 2
CLK
ALE
CS
SDRAS
SDCAS
MA[0Ð11]
Column1
WE
DQM
Data
D0
D1
D2
D3
D1 D2 D3
D0
Column2
CLK
ALE
CS
SDRAS
SDCAS
MA[0Ð11]
Column1
WE
DQM
Data
D0
D1
D2
D3
D1 D2 D3
D0
Column2Z