Processor Users Manual

10-52 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Figure 10-40. GPCM-to-SRAM ConÞguration
10.5.1 Timing ConÞguration
If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx.
These attributes include the CSNT, ACS[0Ð1], SCY[0Ð3], TRLX, EHTR, and SETA Þelds.
Table 10-30 shows signal behavior and system response.
Table 10-30. GPCM Strobe Signal Behavior
Option Register Attributes Signal Behavior
TRLX Access ACS CSNT
Address to CS
Asserted
CS Negated to
Address Change
WE Negated to
Address/Data Invalid
Total Cycles
0 Read 00 x 0 0 x 2+SCY
1
1
SCY is the number of wait cycles from the option register.
0 Read 10 x 1/4*Clock 0 x 2+SCY
0 Read 11 x 1/2*Clock 0 x 2+SCY
0 Write 00 0 0 0 0 2+SCY
0 Write 10 0 1/4*Clock 0 0 2+SCY
0 Write 11 0 1/2*Clock 0 0 2+SCY
0 Write 00 1 0 0 -1/4*Clock 2+SCY
0 Write 10 1 1/4*Clock -1/4*Clock -1/4*Clock 2+SCY
0 Write 11 1 1/2*Clock -1/4*Clock -1/4*Clock 2+SCY
1 Read 00 x 0 0 x 2+2*SCY
1 Read 10 x (1+1/4)*Clock 0 x 3+2*SCY
1 Read 11 x (1+1/2)*Clock 0 x 3+2*SCY
1 Write 00 0 0 0 0 2+2*SCY
1 Write 10 0 (1+1/4)*Clock 0 0 3+2*SCY
1 Write 11 0 (1+1/2)*Clock 0 0 3+2*SCY
1 Write 00 1 0 0 -1-1/4*Clock 3+2*SCY
1 Write 10 1 (1+1/4)*Clock -1-1/4*Clock -1-1/4*Clock 4+2*SCY
1 Write 11 1 (1+1/2)*Clock -1-1/4*Clock -1-1/4*Clock 4+2*SCY
CE
WE[0–3]
OE
Address
Data
32-Bit Wide SRAM
D[0–31]
A[15–29]
GPL_x1/OE
WE[0–3]
CSx 128K
MPC8260